Re: [PATCH 15/21] arm64: KVM: Add panic handling

On 16 November 2015 at 14:11, Marc Zyngier wrote: > Add the panic handler, together with the small bits of assembly > code to call the kernel's panic implementation. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/hyp/hyp-entry.S | 11

Re: [PATCH 15/21] arm64: KVM: Add panic handling

On 16/11/15 15:53, Ard Biesheuvel wrote: > On 16 November 2015 at 14:11, Marc Zyngier wrote: >> Add the panic handler, together with the small bits of assembly >> code to call the kernel's panic implementation. >> >> Signed-off-by: Marc Zyngier >> ---

[PATCH] vhost: relax log address alignment

commit 5d9a07b0de512b77bf28d2401e5fe3351f00a240 ("vhost: relax used address alignment") fixed the alignment for the used virtual address, but not for the physical address used for logging. That's a mistake: alignment should clearly be the same for virtual and physical addresses, Signed-off-by:

Re: [PATCH v4 2/2] target-i386: add support to migrate vcpu's TSC rate

On Mon, Nov 16, 2015 at 10:30:08PM +0800, Haozhong Zhang wrote: > On 11/16/15 11:43, Eduardo Habkost wrote: > > On Mon, Nov 16, 2015 at 04:04:08PM +0800, Haozhong Zhang wrote: > > > This patch enables migrating vcpu's TSC rate. If KVM on the destination > > > machine supports TSC scaling, guest

[PATCH 15/21] arm64: KVM: Add panic handling

Add the panic handler, together with the small bits of assembly code to call the kernel's panic implementation. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/hyp-entry.S | 11 ++- arch/arm64/kvm/hyp/hyp.h | 1 + arch/arm64/kvm/hyp/switch.c| 35

[PATCH 18/21] arm64: KVM: Move away from the assembly version of the world switch

This is it. We remove all of the code that has now been rewritten. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/Makefile |2 - arch/arm64/kvm/hyp.S| 1071 +-- arch/arm64/kvm/vgic-v2-switch.S | 134 -

[PATCH 10/21] arm64: KVM: Add patchable function selector

KVM so far relies on code patching, and is likely to use it more in the future. The main issue is that our alternative system works at the instruction level, while we'd like to have alternatives at the function level. In order to cope with this, add the "hyp_alternate_select" macro that outputs a

[PATCH 09/21] arm64: KVM: Implement guest entry

Contrary to the previous patch, the guest entry is fairly different from its assembly counterpart, mostly because it is only concerned with saving/restoring the GP registers, and nothing else. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/Makefile | 1 +

[PATCH 08/21] arm64: KVM: Implement debug save/restore

Implement the debug save restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/Makefile | 1 + arch/arm64/kvm/hyp/debug-sr.c | 132 ++ arch/arm64/kvm/hyp/hyp.h | 13

[PATCH 07/21] arm64: KVM: Implement 32bit system register save/restore

Implement the 32bit system register save restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/hyp.h | 2 ++ arch/arm64/kvm/hyp/sysreg-sr.c | 41 + 2 files changed, 43

[PATCH 17/21] arm64: KVM: Map the kernel RO section into HYP

In order to run C code in HYP, we must make sure that the kernel's RO section in mapped into HYP (otherwise things break badly). Signed-off-by: Marc Zyngier --- arch/arm/kvm/arm.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/kvm/arm.c

[PATCH 06/21] arm64: KVM: Implement system register save/restore

Implement the system registe save restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/Makefile| 1 + arch/arm64/kvm/hyp/hyp.h | 3 ++ arch/arm64/kvm/hyp/sysreg-sr.c | 90

Re: [PATCH v4 2/2] target-i386: add support to migrate vcpu's TSC rate

On Mon, Nov 16, 2015 at 04:04:08PM +0800, Haozhong Zhang wrote: > This patch enables migrating vcpu's TSC rate. If KVM on the destination > machine supports TSC scaling, guest programs will observe a consistent > TSC rate across the migration. > > If TSC scaling is not supported on the

Re: [PATCH v4 1/2] target-i386: fallback vcpu's TSC rate to value returned by KVM

On Mon, Nov 16, 2015 at 04:04:07PM +0800, Haozhong Zhang wrote: > If no user-specified TSC rate is present, we will try to set > env->tsc_khz to the value returned by KVM_GET_TSC_KHZ. > > Signed-off-by: Haozhong Zhang > --- > target-i386/kvm.c | 25

Re: [PATCH 17/21] arm64: KVM: Map the kernel RO section into HYP

On Mon, Nov 16, 2015 at 01:11:55PM +, Marc Zyngier wrote: > In order to run C code in HYP, we must make sure that the kernel's > RO section in mapped into HYP (otherwise things break badly). Somewhat tangential, but do we have any strong guarantees that the hyp text is otherwise safe in its

Re: [PATCH 15/21] arm64: KVM: Add panic handling

On 16/11/15 14:32, Mark Rutland wrote: + /* Call panic for real */ + while (1) { + unsigned long str_va = (unsigned long)__hyp_panic_string; + + str_va -= HYP_PAGE_OFFSET; + str_va += PAGE_OFFSET; + __hyp_do_panic(str_va,

Re: [PATCH 15/21] arm64: KVM: Add panic handling

> diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c > index 06d3e20..cdc2a96 100644 > --- a/arch/arm64/kvm/hyp/switch.c > +++ b/arch/arm64/kvm/hyp/switch.c > @@ -140,3 +140,38 @@ int __hyp_text __guest_run(struct kvm_vcpu *vcpu) > > return exit_code; > } > + > +static

[PATCH 21/21] arm64: KVM: Remove weak attributes

As we've now switched to the new world switch implementation, remove the weak attributes, as nobody is supposed to override it anymore. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/debug-sr.c | 5 ++--- arch/arm64/kvm/hyp/hyp-entry.S | 3 ---

[PATCH 12/21] arm64: KVM: Implement fpsimd save/restore

Implement the fpsimd save restore, keeping the lazy part in assembler (as returning to C would be overkill). Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/Makefile | 1 + arch/arm64/kvm/hyp/entry.S | 32 +++- arch/arm64/kvm/hyp/fpsimd.S |

[PATCH 20/21] arm64: KVM: Cleanup asm-offset.c

As we've now rewritten most of our code-base in C, most of the KVM-specific code in asm-offset.c is useless. Delete-time again! Signed-off-by: Marc Zyngier --- arch/arm64/kernel/asm-offsets.c | 39 --- 1 file changed, 39 deletions(-)

[PATCH 02/21] arm64: KVM: Add a HYP-specific header file

In order to expose the various EL2 services that are private to the hypervisor, add a new hyp.h file. So far, it only contains mundane things such as section annotation and VA manipulation. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/hyp.h | 31

[PATCH 00/21] arm64: KVM: world switch in C

Once upon a time, the KVM/arm64 world switch was a nice, clean, lean and mean piece of hand-crafted assembly code. Over time, features have crept in, the code has become harder to maintain, and the smallest change is a pain to introduce. The VHE patches are a prime example of why this doesn't work

[PATCH 03/21] arm64: KVM: Implement vgic-v2 save/restore

Implement the vgic-v2 save restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/Makefile | 1 + arch/arm64/kvm/hyp/Makefile | 5 +++ arch/arm64/kvm/hyp/hyp.h| 3 ++

[PATCH 04/21] arm64: KVM: Implement vgic-v3 save/restore

Implement the vgic-v3 save restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/Makefile | 1 + arch/arm64/kvm/hyp/hyp.h| 3 + arch/arm64/kvm/hyp/vgic-v3-sr.c | 222

[PATCH 01/21] arm64: add macros to read/write system registers

From: Mark Rutland Rather than crafting custom macros for reading/writing each system register provide generics accessors, read_sysreg and write_sysreg, for this purpose. Unlike read_cpuid, calls to read_exception_reg are never expected to be optimized away or replaced

[PATCH 13/21] arm64: KVM: Implement TLB handling

Implement the TLB handling as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/Makefile | 1 + arch/arm64/kvm/hyp/tlb.c| 72 + 2 files changed, 73 insertions(+) create

[PATCH 05/21] arm64: KVM: Implement timer save/restore

Implement the timer save restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/Makefile | 1 + arch/arm64/kvm/hyp/hyp.h | 3 ++ arch/arm64/kvm/hyp/timer-sr.c | 68

Re: [PATCH 15/21] arm64: KVM: Add panic handling

On 16/11/15 14:16, Mark Rutland wrote: >> diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c >> index 06d3e20..cdc2a96 100644 >> --- a/arch/arm64/kvm/hyp/switch.c >> +++ b/arch/arm64/kvm/hyp/switch.c >> @@ -140,3 +140,38 @@ int __hyp_text __guest_run(struct kvm_vcpu *vcpu) >>

[PATCH 19/21] arm64: KVM: Turn system register numbers to an enum

Having the system register numbers as #defines has been a pain since day one, as the ordering is pretty fragile, and moving things around leads to renumbering and epic conflict resolutions. Now that we're mostly acessing the sysreg file in C, an enum is a much better type to use, and we can clean

[PATCH 11/21] arm64: KVM: Implement the core world switch

Implement the core of the world switch in C. Not everything is there yet, and there is nothing to re-enter the world switch either. But this already outlines the code structure well enough. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/Makefile | 1 +

[PATCH 14/21] arm64: KVM: HYP mode entry points

Add the entry points for HYP mode (both for hypercalls and exception handling). Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/Makefile| 1 + arch/arm64/kvm/hyp/hyp-entry.S | 189 + 2 files changed, 190 insertions(+)

[PATCH 16/21] arm64: KVM: Add compatibility aliases

So far, we've implemented the new world switch with a completely different namespace, so that we could have both implementation compiled in. Let's take things one step further by adding weak aliases that have the same names as the original implementation. The weak attributes allows the new

Re: [PATCH v4 2/2] target-i386: add support to migrate vcpu's TSC rate

On 11/16/15 11:43, Eduardo Habkost wrote: > On Mon, Nov 16, 2015 at 04:04:08PM +0800, Haozhong Zhang wrote: > > This patch enables migrating vcpu's TSC rate. If KVM on the destination > > machine supports TSC scaling, guest programs will observe a consistent > > TSC rate across the migration. > >

Re: [PATCH 15/21] arm64: KVM: Add panic handling

> >> + /* Call panic for real */ > >> + while (1) { > >> + unsigned long str_va = (unsigned long)__hyp_panic_string; > >> + > >> + str_va -= HYP_PAGE_OFFSET; > >> + str_va += PAGE_OFFSET; > >> + __hyp_do_panic(str_va, > >> + spsr, elr,

Re: [PATCH v4 1/2] target-i386: fallback vcpu's TSC rate to value returned by KVM

On 11/16/15 11:39, Eduardo Habkost wrote: > On Mon, Nov 16, 2015 at 04:04:07PM +0800, Haozhong Zhang wrote: > > If no user-specified TSC rate is present, we will try to set > > env->tsc_khz to the value returned by KVM_GET_TSC_KHZ. > > > > Signed-off-by: Haozhong Zhang

Re: [PATCH 17/21] arm64: KVM: Map the kernel RO section into HYP

On 16/11/15 14:27, Mark Rutland wrote: > On Mon, Nov 16, 2015 at 01:11:55PM +, Marc Zyngier wrote: >> In order to run C code in HYP, we must make sure that the kernel's >> RO section in mapped into HYP (otherwise things break badly). > > Somewhat tangential, but do we have any strong

Re: [PATCH] kvm/vmx: EPTP switching test

2015-11-15 18:00+0200, Michael S. Tsirkin: > This patch adds a new parameter: eptp_switching_test, which enables > > testing EPT switching on VMX if supported by hardware. All EPT entries > are initialized to the same value so this adds no useful functionality > by itself, but can be used to

Re: [PATCH] kvm/vmx: EPTP switching test

2015-11-16 19:59+0200, Michael S. Tsirkin: > On Mon, Nov 16, 2015 at 06:51:06PM +0100, > =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= wrote: >> 2015-11-15 18:00+0200, Michael S. Tsirkin: >> (And I think that eptp switching is expected to be used in conjuction >> with #VE, so it'd then make sense to

Re: [PATCH] kvm/vmx: EPTP switching test

On Mon, Nov 16, 2015 at 10:18 AM, =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= wrote: > 2015-11-16 19:59+0200, Michael S. Tsirkin: >> On Mon, Nov 16, 2015 at 06:51:06PM +0100, >> =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= wrote: >>> 2015-11-15 18:00+0200, Michael S. Tsirkin: >>>

Re: [PATCH] KVM: x86: Add lowest-priority support for vt-d posted-interrupts

2015-11-09 10:46+0800, Feng Wu: > Use vector-hashing to handle lowest-priority interrupts for > posted-interrupts. As an example, modern Intel CPUs use this > method to handle lowest-priority interrupts. (I don't think it's a good idea that the algorithm differs from non-PI lowest priority

Re: [PATCH] kvm/vmx: EPTP switching test

On Mon, Nov 16, 2015 at 06:51:06PM +0100, =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= wrote: > 2015-11-15 18:00+0200, Michael S. Tsirkin: > > This patch adds a new parameter: eptp_switching_test, which enables > > > > testing EPT switching on VMX if supported by hardware. All EPT entries > > are

Re: [PATCH v1 2/2] dma-mapping-common: add DMA attribute - DMA_ATTR_IOMMU_BYPASS

On Mon, Nov 16, 2015 at 12:42 AM, David Woodhouse wrote: > > On Sun, 2015-11-15 at 22:54 -0800, Benjamin Serebrin wrote: > > We looked into Intel IOMMU performance a while ago and learned a few > > useful things. We generally did a parallel 200 thread TCP_RR test, > > as

[PATCH v2 4/4] KVM: x86: fix ready_for_interrupt reporting in split IRQ chip case

This patch adds a call to kvm_vcpu_ready_for_interrupt_injection to ensure ready for interrupt is reported to user space correctly. This addresses a problem observed in QEMU when kvm->ready_for_interrupt is set but the x86 interrupt flag is clear. Reviewed-by: Steve Rutherford

[PATCH v2 3/4] KVM: x86: request interrupt window when IRQ chip is split

Before this patch, we incorrectly enter the guest without requesting an interrupt window if the IRQ chip is split between user space and the kernel. Because lapic_in_kernel no longer implies the PIC is in the kernel, this patch tests pic_in_kernel to determining whether an interrupt window should

[PATCH v2 2/4] KVM: x86: set KVM_REQ_EVENT on local interrupt request from user space

Set KVM_REQ_EVENT when a PIC in user space injects a local interrupt. Currently a request is only made when neither the PIC nor the APIC is in the kernel, which is not sufficient in the split IRQ chip case. This addresses a problem in QEMU where interrupts are delayed until another path invokes

[PATCH v2 1/4] KVM: x86: add new function kvm_vcpu_ready_for_interrupt_injection

This patch breaks out a new function kvm_vcpu_ready_for_interrupt_injection. This routine encapsulates the logic required to determine whether a vcpu is ready to accept an interrupt injection, which is now required on multiple paths. Reviewed-by: Steve Rutherford

RE: [PATCH] KVM: x86: always set accessed bit in shadow PTEs

Paolo Bonzini wrote on 2015-11-13: > Commit 7a1638ce4220 ("nEPT: Redefine EPT-specific link_shadow_page()", > 2013-08-05) says: > > Since nEPT doesn't support A/D bit, we should not set those bit > when building the shadow page table. > but this is not necessary. Even though nEPT doesn't

Re: [PATCH] virtio_ring: Shadow available ring flags & index

On 11/14/2015 7:41 AM, Venkatesh Srinivas wrote: > On Wed, Nov 11, 2015 at 02:34:33PM +0200, Michael S. Tsirkin wrote: >> On Tue, Nov 10, 2015 at 04:21:07PM -0800, Venkatesh Srinivas wrote: >>> Improves cacheline transfer flow of available ring header. >>> >>> Virtqueues are implemented as a pair

RE: [PATCH] kvm/vmx: EPTP switching test

Michael S. Tsirkin wrote on 2015-11-16: > This patch adds a new parameter: eptp_switching_test, which enables > testing EPT switching on VMX if supported by hardware. All EPT > entries are initialized to the same value so this adds no useful > functionality by itself, but can be used to test

[Bug 108021] New: Kernel Panic in the Virtual Machines running kernel 3.13.0-44-generic (Ubuntu)

https://bugzilla.kernel.org/show_bug.cgi?id=108021 Bug ID: 108021 Summary: Kernel Panic in the Virtual Machines running kernel 3.13.0-44-generic (Ubuntu) Product: Virtualization Version: unspecified Kernel Version: 2.6.32-47

[PATCH v5 2/3] target-i386: reorganize TSC rate setting code

Following two changes are made to the TSC rate setting code in kvm_arch_init_vcpu(): * The code is moved to a new function kvm_arch_set_tsc_khz(). * If setting user-specified TSC rate fails and the host TSC rate is inconsistent with the user-specified one, print a warning message.

[PATCH v5 3/3] target-i386: add support to migrate vcpu's TSC rate

This patch enables migrating vcpu's TSC rate. If KVM on the destination machine supports TSC scaling, guest programs will observe a consistent TSC rate across the migration. If TSC scaling is not supported on the destination machine, the migration will not be aborted and QEMU on the destination

[PATCH v5 0/3] target-i386: save/restore vcpu's TSC rate during migration

This patchset enables QEMU to save/restore vcpu's TSC rate during the migration on machine types pc-*-2.5 or newer. On the source machine: * If the vcpu's TSC rate is specified by the cpu option 'tsc-freq', then this user-specified TSC rate will be migrated. * Otherwise, the TSC rate

[PATCH v5 1/3] target-i386: fallback vcpu's TSC rate to value returned by KVM

If no user-specified TSC rate is present, we will try to set env->tsc_khz to the value returned by KVM_GET_TSC_KHZ. Signed-off-by: Haozhong Zhang --- target-i386/kvm.c | 12 1 file changed, 12 insertions(+) diff --git a/target-i386/kvm.c

Re: [PATCH v4 2/2] target-i386: add support to migrate vcpu's TSC rate

On 11/16/15 13:35, Eduardo Habkost wrote: > On Mon, Nov 16, 2015 at 10:30:08PM +0800, Haozhong Zhang wrote: > > On 11/16/15 11:43, Eduardo Habkost wrote: > > > On Mon, Nov 16, 2015 at 04:04:08PM +0800, Haozhong Zhang wrote: > > > > This patch enables migrating vcpu's TSC rate. If KVM on the

Re: [PATCH] vhost: relax log address alignment

On 11/16/2015 11:00 PM, Michael S. Tsirkin wrote: > commit 5d9a07b0de512b77bf28d2401e5fe3351f00a240 ("vhost: relax used > address alignment") fixed the alignment for the used virtual address, > but not for the physical address used for logging. > > That's a mistake: alignment should clearly be

Re: [PATCH net-next RFC V3 0/3] basic busy polling support for vhost_net

On 11/13/2015 05:20 PM, Jason Wang wrote: > > On 11/12/2015 08:02 PM, Felipe Franciosi wrote: >> Hi Jason, >> >> I understand your busy loop timeout is quite conservative at 50us. Did you >> try any other values? > I've also tried 20us. And results shows 50us was better in: > > - very small

Re: [PATCH v1 2/2] dma-mapping-common: add DMA attribute - DMA_ATTR_IOMMU_BYPASS

On Sun, 2015-11-15 at 22:54 -0800, Benjamin Serebrin wrote: > We looked into Intel IOMMU performance a while ago and learned a few > useful things.  We generally did a parallel 200 thread TCP_RR test, > as this churns through mappings quickly and uses all available cores. > > First, the main

Re: [PATCH V2 7/7] KVM, pkeys: disable PKU feature without ept

On 16/11/2015 08:51, Huaitong Han wrote: > This patch disables CPUID:PKU without ept. The commit message and probably the code too should say why. Paolo > Signed-off-by: Huaitong Han > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index

[PATCH 2/2] arm64: KVM: Add workaround for Cortex-A57 erratum 834220

Cortex-A57 parts up to r1p2 can misreport Stage 2 translation faults when a Stage 1 permission fault or device alignment fault should have been reported. This patch implements the workaround (which is to validate that the Stage-1 translation actually succeeds) by using code patching.

[PATCH 1/2] arm64: KVM: Fix AArch32 to AArch64 register mapping

When running a 32bit guest under a 64bit hypervisor, the ARMv8 architecture defines a mapping of the 32bit registers in the 64bit space. This includes banked registers that are being demultiplexed over the 64bit ones. On exception caused by an operation involving a 32bit register, the HW exposes

[PATCH 0/2] arm64: KVM: Fixes for 4.4-rc2

Here's a couple of fixes for KVM/arm64: - The first one addresses a misinterpretation of the architecture spec, leading to the mishandling of I/O accesses generated from an AArch32 guest using banked registers. - The second one is a workaround for a Cortex-A57 erratum. Both patches are

[PATCH v8 4/5] nvdimm acpi: build ACPI nvdimm devices

NVDIMM devices is defined in ACPI 6.0 9.20 NVDIMM Devices There is a root device under \_SB and specified NVDIMM devices are under the root device. Each NVDIMM device has _ADR which returns its handle used to associate MEMDEV structure in NFIT Currently, we do not support any function on _DSM,

[PATCH v8 2/5] acpi: support specified oem table id for build_header

Let build_header() support specified OEM table id so that we can build multiple SSDT later If the oem table id is not specified (aka, NULL), we use the default id instead as the previous behavior Signed-off-by: Xiao Guangrong --- hw/acpi/aml-build.c | 15

[PATCH v8 3/5] nvdimm acpi: build ACPI NFIT table

NFIT is defined in ACPI 6.0: 5.2.25 NVDIMM Firmware Interface Table (NFIT) Currently, we only support PMEM mode. Each device has 3 structures: - SPA structure, defines the PMEM region info - MEM DEV structure, it has the @handle which is used to associate specified ACPI NVDIMM device we will

[PATCH v8 5/5] nvdimm: add maintain info

Add NVDIMM maintainer Signed-off-by: Xiao Guangrong --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9e1fa72..da58bf4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -932,6 +932,13 @@ M: Jiri Pirko

[PATCH v8 0/5] implement vNVDIMM

This patchset can be found at: https://github.com/xiaogr/qemu.git nvdimm-v8 It is based on pci branch on Michael's tree and the top commit is: commit e3a4e177d9 (migration/ram: fix build on 32 bit hosts). Changelog in v8: We split the long patch series into the small parts, as you see now,

[PATCH v8 1/5] nvdimm: implement NVDIMM device abstract

Introduce "nvdimm" device which is based on pc-dimm device type Currently, nothing is specific for nvdimm but hotplug is disabled Signed-off-by: Xiao Guangrong --- default-configs/i386-softmmu.mak | 1 + default-configs/x86_64-softmmu.mak | 1 +

[PATCH v4 0/2] target-i386: save/restore vcpu's TSC rate during migration

This patchset enables QEMU to save/restore vcpu's TSC rate during the migration on machine types pc-*-2.5 or newer. On the source machine: * If the vcpu's TSC rate is specified by the cpu option 'tsc-freq', then this user-specified TSC rate will be migrated. * Otherwise, the TSC rate

[PATCH v4 1/2] target-i386: fallback vcpu's TSC rate to value returned by KVM

If no user-specified TSC rate is present, we will try to set env->tsc_khz to the value returned by KVM_GET_TSC_KHZ. Signed-off-by: Haozhong Zhang --- target-i386/kvm.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target-i386/kvm.c

[PATCH v4 2/2] target-i386: add support to migrate vcpu's TSC rate

This patch enables migrating vcpu's TSC rate. If KVM on the destination machine supports TSC scaling, guest programs will observe a consistent TSC rate across the migration. If TSC scaling is not supported on the destination machine, the migration will not be aborted and QEMU on the destination