scenario is a UEFI blob loaded with the -bios option in QEMU.
Note that the MMIO exit on writes to a read-only memory is ABI and can
be used to emulate block-erase style flash devices.
Cc: Ard Biesheuvel ard.biesheu...@linaro.org
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
it unconditionally.
Signed-off-by: Ard Biesheuvel ard.biesheu...@linaro.org
---
This fixes an issue I observed with UEFI running under QEMU/KVM using
NOR flash emulation and the upcoming KVM_CAP_READONLY_MEM support, where
NOR flash reads were mistaken for NOR flash writes, resulting in all read
accesses to go
On 9 September 2014 11:35, Marc Zyngier marc.zyng...@arm.com wrote:
Hi Ard,
On 2014-09-08 21:29, Ard Biesheuvel wrote:
The ISS encoding for an exception from a Data Abort has a WnR
bit[6] that indicates whether the Data Abort was caused by a
read or a write instruction. While
it unconditionally.
Instead of fixing both implementations of kvm_is_write_fault()
in place, reimplement it just once using kvm_vcpu_dabt_iswrite(),
which already does the right thing with respect to the WnR bit.
Also fix up the callers to pass 'vcpu'
Acked-by: Laszlo Ersek ler...@redhat.com
Signed-off-by: Ard
Read-only memory ranges may be backed by the zero page, so avoid
misidentifying it a a MMIO pfn.
Signed-off-by: Ard Biesheuvel ard.biesheu...@linaro.org
Fixes: b88657674d39 (ARM: KVM: user_mem_abort: support stage 2 MMIO page
mapping)
---
This fixes another issue I identified when testing QEMU
On 12 September 2014 19:25, kbuild test robot fengguang...@intel.com wrote:
tree: git://git.kernel.org/pub/scm/virt/kvm/kvm.git master
head: e20e1bde3bb158cd3d08b9d94a90d3cabf1ba7cb
commit: e20e1bde3bb158cd3d08b9d94a90d3cabf1ba7cb [11/11] KVM: check for
!is_zero_pfn() in kvm_is_mmio_pfn()
it refers
to the zero page is required to correctly distinguish the zero page
from other special RAM ranges that may also have the PG_reserved bit
set, but need to be treated as MMIO memory.
Signed-off-by: Ard Biesheuvel ard.biesheu...@linaro.org
---
arch/mips/mm/init.c | 1 +
arch/s390/mm/init.c | 1
On 12 September 2014 23:14, Andrew Morton a...@linux-foundation.org wrote:
On Fri, 12 Sep 2014 22:17:23 +0200 Ard Biesheuvel ard.biesheu...@linaro.org
wrote:
In order to make the static inline function is_zero_pfn() callable by
modules, export its symbol dependencies 'zero_pfn' and (for s390
On 18 September 2014 05:18, Laszlo Ersek ler...@redhat.com wrote:
On 09/18/14 13:44, Andreas Färber wrote:
Hello Laszlo,
Am 18.09.2014 um 10:23 schrieb Laszlo Ersek:
I've been made an offer that I couldn't refuse :) to organize a Birds
of a Feather session concerning OVMF at the KVM Forum
On 19 September 2014 10:03, Paolo Bonzini pbonz...@redhat.com wrote:
Il 19/09/2014 16:17, Ard Biesheuvel ha scritto:
(**) Ard's patches for the upstream host kernel (== KVM) have been...
ugh, not sure... applied to a maintainer tree? Ard? :)
Some are in kvm/master, which I think means
, e.g., whether or not to call get_page/put_page on
it etc. This means that returning false for the zero page is a mistake
and the patch above should be reverted.
Signed-off-by: Ard Biesheuvel ard.biesheu...@linaro.org
---
arch/ia64/kvm/kvm-ia64.c | 2 +-
arch/x86/kvm/mmu.c | 6
Instead of using kvm_is_mmio_pfn() to decide whether a host region
should be stage 2 mapped with device attributes, add a new static
function kvm_is_device_pfn() that disregards RAM pages with the
reserved bit set, as those should usually not be mapped as device
memory.
Signed-off-by: Ard
On 10 November 2014 11:53, Christoffer Dall christoffer.d...@linaro.org wrote:
Hi Ard,
On Mon, Nov 10, 2014 at 09:33:56AM +0100, Ard Biesheuvel wrote:
This reverts commit 85c8555ff0 (KVM: check for !is_zero_pfn() in
kvm_is_mmio_pfn()) and renames the function to kvm_is_reserved_pfn
On 10 November 2014 11:57, Christoffer Dall christoffer.d...@linaro.org wrote:
On Mon, Nov 10, 2014 at 09:33:55AM +0100, Ard Biesheuvel wrote:
Instead of using kvm_is_mmio_pfn() to decide whether a host region
should be stage 2 mapped with device attributes, add a new static
function
Memory regions may be incoherent with the caches, typically when the
guest has mapped a host system RAM backed memory region as uncached.
Add a flag KVM_MEMSLOT_INCOHERENT so that we can tag these memslots
and handle them appropriately when mapping them.
Signed-off-by: Ard Biesheuvel ard.biesheu
-off-by: Laszlo Ersek ler...@redhat.com
Signed-off-by: Ard Biesheuvel ard.biesheu...@linaro.org
---
arch/arm/include/asm/kvm_mmu.h | 5 +++--
arch/arm/kvm/mmu.c | 9 +++--
arch/arm64/include/asm/kvm_mmu.h | 5 +++--
3 files changed, 13 insertions(+), 6 deletions(-)
diff --git
to regions tagged as such are flushed to DRAM before being passed
to the guest.
Signed-off-by: Ard Biesheuvel ard.biesheu...@linaro.org
---
arch/arm/kvm/mmu.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index
On 17 November 2014 15:58, Ard Biesheuvel ard.biesheu...@linaro.org wrote:
Readonly memslots are often used to implement emulation of ROMs and
NOR flashes, in which case the guest may legally map these regions as
uncached.
To deal with the incoherency associated with uncached guest mappings
On 10 November 2014 09:33, Ard Biesheuvel ard.biesheu...@linaro.org wrote:
This reverts commit 85c8555ff0 (KVM: check for !is_zero_pfn() in
kvm_is_mmio_pfn()) and renames the function to kvm_is_reserved_pfn.
The problem being addressed by the patch above was that some ARM code
based
On 21 November 2014 at 12:24, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Mon, Nov 10, 2014 at 09:33:55AM +0100, Ard Biesheuvel wrote:
Instead of using kvm_is_mmio_pfn() to decide whether a host region
should be stage 2 mapped with device attributes, add a new static
function
On 9 December 2014 at 12:26, Christoffer Dall
christoffer.d...@linaro.org wrote:
From: Ard Biesheuvel ard.biesheu...@linaro.org
Instead of using kvm_is_mmio_pfn() to decide whether a host region
should be stage 2 mapped with device attributes, add a new static
function kvm_is_device_pfn
On 9 December 2014 at 13:38, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Tue, Dec 09, 2014 at 01:29:52PM +0100, Ard Biesheuvel wrote:
On 9 December 2014 at 12:26, Christoffer Dall
christoffer.d...@linaro.org wrote:
From: Ard Biesheuvel ard.biesheu...@linaro.org
Instead of using
.
Signed-off-by: Ard Biesheuvel ard.biesheu...@linaro.org
---
arch/arm64/kvm/sys_regs.c | 35 ++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 1e170eab6603..bde2b49a7cd8 100644
--- a/arch/arm64
.
Signed-off-by: Ard Biesheuvel ard.biesheu...@linaro.org
---
arch/arm64/kvm/hyp.S | 101 ++
arch/arm64/kvm/sys_regs.c | 28 -
2 files changed, 120 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S
---
arch/arm/kvm/mmu.c | 2 +-
arch/arm64/include/asm/kvm_arm.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 136662547ca6..fa8ec55220ea 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -1530,7 +1530,7
introduces a fast path
for EL2 to perform trivial sysreg writes on behalf of the guest, without the
need for a full world switch to the host and back.
The main purpose of these patches is to quantify the performance hit, and
verify whether the MAIR_EL1 handling works correctly.
Ard Biesheuvel (3
On 19 February 2015 at 13:40, Marc Zyngier marc.zyng...@arm.com wrote:
On 19/02/15 10:54, Ard Biesheuvel wrote:
---
arch/arm/kvm/mmu.c | 2 +-
arch/arm64/include/asm/kvm_arm.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm
On 19 February 2015 at 15:19, Marc Zyngier marc.zyng...@arm.com wrote:
On 19/02/15 13:44, Ard Biesheuvel wrote:
On 19 February 2015 at 13:40, Marc Zyngier marc.zyng...@arm.com wrote:
On 19/02/15 10:54, Ard Biesheuvel wrote:
---
arch/arm/kvm/mmu.c | 2 +-
arch/arm64/include/asm
On 19 February 2015 at 15:27, Alexander Graf ag...@suse.de wrote:
On 19.02.15 15:56, Ard Biesheuvel wrote:
On 19 February 2015 at 14:50, Alexander Graf ag...@suse.de wrote:
On 19.02.15 11:54, Ard Biesheuvel wrote:
This is a 0th order approximation of how we could potentially force
On 19 feb. 2015, at 17:55, Andrew Jones drjo...@redhat.com wrote:
On Thu, Feb 19, 2015 at 05:19:35PM +, Ard Biesheuvel wrote:
On 19 February 2015 at 16:57, Andrew Jones drjo...@redhat.com wrote:
On Thu, Feb 19, 2015 at 10:54:43AM +, Ard Biesheuvel wrote:
This is a 0th order
On 20 February 2015 at 14:29, Andrew Jones drjo...@redhat.com wrote:
On Thu, Feb 19, 2015 at 06:57:24PM +0100, Paolo Bonzini wrote:
On 19/02/2015 18:55, Andrew Jones wrote:
(I don't have an exact number for how many times it went to EL1
because
access_mair() doesn't have a trace
On 19 February 2015 at 16:57, Andrew Jones drjo...@redhat.com wrote:
On Thu, Feb 19, 2015 at 10:54:43AM +, Ard Biesheuvel wrote:
This is a 0th order approximation of how we could potentially force the guest
to avoid uncached mappings, at least from the moment the MMU is on. (Before
On 19 February 2015 at 14:50, Alexander Graf ag...@suse.de wrote:
On 19.02.15 11:54, Ard Biesheuvel wrote:
This is a 0th order approximation of how we could potentially force the guest
to avoid uncached mappings, at least from the moment the MMU is on. (Before
that, all of memory
On 5 March 2015 at 15:58, Catalin Marinas catalin.mari...@arm.com wrote:
On Thu, Mar 05, 2015 at 01:26:39PM +0100, Paolo Bonzini wrote:
On 05/03/2015 13:03, Catalin Marinas wrote:
I'd hate to have to do that. PCI should be entirely probeable
given that we tell the guest where the host
On 4 March 2015 at 12:35, Catalin Marinas catalin.mari...@arm.com wrote:
(please try to avoid top-posting)
On Mon, Mar 02, 2015 at 06:20:19PM -0800, Mario Smarduch wrote:
On 03/02/2015 08:31 AM, Christoffer Dall wrote:
However, my concern with these patches are on two points:
1. It's not
On 4 March 2015 at 13:29, Catalin Marinas catalin.mari...@arm.com wrote:
On Wed, Mar 04, 2015 at 12:50:57PM +0100, Ard Biesheuvel wrote:
On 4 March 2015 at 12:35, Catalin Marinas catalin.mari...@arm.com wrote:
On Mon, Mar 02, 2015 at 06:20:19PM -0800, Mario Smarduch wrote:
On 03/02/2015 08
On 24 February 2015 at 14:55, Andrew Jones drjo...@redhat.com wrote:
On Fri, Feb 20, 2015 at 04:36:26PM +0100, Andrew Jones wrote:
On Fri, Feb 20, 2015 at 02:37:25PM +, Ard Biesheuvel wrote:
On 20 February 2015 at 14:29, Andrew Jones drjo...@redhat.com wrote:
So looks like the 3 orders
On 26 March 2015 at 19:49, Ard Biesheuvel ard.biesheu...@linaro.org wrote:
On 26 March 2015 at 19:45, Stefano Stabellini
stefano.stabell...@eu.citrix.com wrote:
On Thu, 26 Mar 2015, Andrew Jones wrote:
On Wed, Mar 25, 2015 at 10:44:42AM +0100, Andrew Jones wrote:
Hello ARM virt maintainers
On 26 March 2015 at 19:45, Stefano Stabellini
stefano.stabell...@eu.citrix.com wrote:
On Thu, 26 Mar 2015, Andrew Jones wrote:
On Wed, Mar 25, 2015 at 10:44:42AM +0100, Andrew Jones wrote:
Hello ARM virt maintainers,
I'd like to start a discussion about supporting virt-what[1]. virt-what
(adding lists)
On 10 November 2015 at 10:45, Ard Biesheuvel <ard.biesheu...@linaro.org> wrote:
> Hi all,
>
> I wonder if this is a better way to address the problem. It looks at
> the nature of the memory rather than the nature of the mapping, which
> is probably a mo
On 11 November 2015 at 03:03, Laura Abbott wrote:
>
> PAGE_S2_DEVICE is a pgprot val and needs to be accessed using the proper
> accessors. Switch to these accessors to avoid errors with
> STRICT_MM_TYPECHECK.
>
> Signed-off-by: Laura Abbott
On 16 November 2015 at 14:11, Marc Zyngier wrote:
> Add the panic handler, together with the small bits of assembly
> code to call the kernel's panic implementation.
>
> Signed-off-by: Marc Zyngier
> ---
> arch/arm64/kvm/hyp/hyp-entry.S | 11
host
physical addresses, we can simply check whether the mapping is backed
by memory that is managed by the host kernel, and only perform the
D-cache maintenance if this is the case.
Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Tested-by: Pavel Fedin <p.fe...@samsung.
On 10 November 2015 at 13:22, Christoffer Dall
<christoffer.d...@linaro.org> wrote:
> On Tue, Nov 10, 2015 at 10:45:37AM +0100, Ard Biesheuvel wrote:
>> Hi all,
>>
>> I wonder if this is a better way to address the problem. It looks at
>> the nature of
On 10 November 2015 at 14:40, Christoffer Dall
<christoffer.d...@linaro.org> wrote:
> On Tue, Nov 10, 2015 at 02:15:45PM +0100, Ard Biesheuvel wrote:
>> On 10 November 2015 at 13:22, Christoffer Dall
>> <christoffer.d...@linaro.org> wrote:
>> > On Tue, N
On 4 November 2015 at 19:49, Christopher Covington wrote:
> On 11/04/2015 08:31 AM, Christoffer Dall wrote:
>> On Tue, Nov 03, 2015 at 01:39:44PM -0600, Rob Herring wrote:
>>> On Tue, Nov 3, 2015 at 1:17 PM, Mario Smarduch
>>> wrote:
On
Cc: Laszlo Ersek <ler...@redhat.com>
> Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
> Cc: Drew Jones <drjo...@redhat.com>
> Cc: Wei Huang <w...@redhat.com>
> Cc: Peter Maydell <peter.mayd...@linaro.org>
> Signed-off-by: Christoffer Dall <christoffer
On 31 August 2015 at 10:57, Christoffer Dall
<christoffer.d...@linaro.org> wrote:
> On Mon, Aug 31, 2015 at 10:46:59AM +0200, Ard Biesheuvel wrote:
>> On 30 August 2015 at 15:54, Christoffer Dall
>> <christoffer.d...@linaro.org> wrote:
>> > Provid
s a spin on the FVP Base model to check UEFI booting,
and everything seems to work fine. (I tested 2-level and 3-level)
I didn't test the KVM changes, so for all patches except those:
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheu...@lina
On 2 September 2015 at 11:42, Suzuki K. Poulose <suzuki.poul...@arm.com> wrote:
> On 02/09/15 10:38, Ard Biesheuvel wrote:
>>
>> On 13 August 2015 at 13:33, Suzuki K. Poulose <suzuki.poul...@arm.com>
>> wrote:
>>>
>>> From: "Suzuki K. Poulo
he case where we use the section maps. This
> patch adds a symbol to make it clear those cases.
>
That sentence does not make sense.
> Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
> Cc: Mark Rutland <mark.rutl...@arm.com>
> Cc: Catalin Marinas <catalin.mari...@arm.com
On 13 August 2015 at 19:29, Catalin Marinas wrote:
> On Thu, Aug 13, 2015 at 03:45:07PM +0100, Suzuki K. Poulose wrote:
>> On 13/08/15 13:28, Steve Capper wrote:
>> >On 13 August 2015 at 12:34, Suzuki K. Poulose
>> >wrote:
>> >> __enable_mmu:
>>
On 2 September 2015 at 11:48, Ard Biesheuvel <ard.biesheu...@linaro.org> wrote:
> On 13 August 2015 at 19:29, Catalin Marinas <catalin.mari...@arm.com> wrote:
>> On Thu, Aug 13, 2015 at 03:45:07PM +0100, Suzuki K. Poulose wrote:
>>> On 13/08/15 13:28, Steve Capper
On 5 October 2015 at 14:02, Suzuki K. Poulose <suzuki.poul...@arm.com> wrote:
> On 02/10/15 16:49, Catalin Marinas wrote:
>>
>> On Tue, Sep 15, 2015 at 04:41:18PM +0100, Suzuki K. Poulose wrote:
>>>
>>> From: Ard Biesheuvel <ard.biesheu...@linaro.
Hi Pavel,
Thanks for getting to the bottom of this.
On 1 December 2015 at 14:03, Pavel Fedin wrote:
> This function takes stage-II physical addresses (A.K.A. IPA), on input, not
> real physical addresses. This causes kvm_is_device_pfn() to return wrong
> values, depending
On 2 December 2015 at 19:50, Christoffer Dall
wrote:
> On Tue, Dec 01, 2015 at 04:03:52PM +0300, Pavel Fedin wrote:
>> This function takes stage-II physical addresses (A.K.A. IPA), on input, not
>> real physical addresses. This causes kvm_is_device_pfn() to return
On 4 December 2015 at 02:58, Ben Hutchings <b...@decadent.org.uk> wrote:
> On Wed, 2015-12-02 at 18:41 +0100, Ard Biesheuvel wrote:
>> Hi Pavel,
>>
>> Thanks for getting to the bottom of this.
>>
>> On 1 December 2015 at 14:03, Pavel Fedin <p.fe...@sa
On 3 December 2015 at 08:14, Pavel Fedin wrote:
> Hello!
>
>> > diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
>> > index 7dace90..51ad98f 100644
>> > --- a/arch/arm/kvm/mmu.c
>> > +++ b/arch/arm/kvm/mmu.c
>> > @@ -310,7 +310,8 @@ static void stage2_flush_ptes(struct
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