On 8 February 2011 17:13, Markus Armbruster arm...@redhat.com wrote:
As far as qdev's concerned, I can see two kinds of to-dos:
* Further develop qdev so that more of the machine init code can becomes
qdev declarations. Specific ideas welcome. Patches even more, as
always.
* Convert the
On 9 February 2011 08:11, Markus Armbruster arm...@redhat.com wrote:
Peter Maydell peter.mayd...@linaro.org writes:
Markus Armbruster arm...@redhat.com wrote:
I've said this before: at some point in time (sooner rather than
later, if you ask me), we need to shoot the stragglers.
...and my
On 10 February 2011 07:47, Anthony Liguori anth...@codemonkey.ws wrote:
So very concretely, I'm suggesting we do the following to target-i386:
2) get rid of the entire concept of machines. Creating a i440fx is
essentially equivalent to creating a bare machine.
Does that make any sense for
On 10 February 2011 10:13, Anthony Liguori anth...@codemonkey.ws wrote:
On 02/10/2011 10:04 AM, Peter Maydell wrote:
On 10 February 2011 08:36, Anthony Liguorianth...@codemonkey.ws wrote:
So you would model arm926ej-s as the chipset and then build up the
machines
by modifying parameters
On 10 February 2011 12:23, Anthony Liguori anth...@codemonkey.ws wrote:
But something interacts with each processor and dispatches the I/O
operations in the address space, no? I can't believe there are 2^32 address
lines coming off of every arm chip that each device connects.
Well, the AXI
On 10 February 2011 19:17, Scott Wood scottw...@freescale.com wrote:
On Thu, 10 Feb 2011 08:16:15 +
Peter Maydell peter.mayd...@linaro.org wrote:
On 10 February 2011 07:47, Anthony Liguori anth...@codemonkey.ws wrote:
So very concretely, I'm suggesting we do the following to target-i386
On 13 February 2011 16:56, Anthony Liguori anth...@codemonkey.ws wrote:
If we can move away from Bus abstraction and to a simpler interface
mechanism, then we can express peer relationships by just having bidirection
references. IOW:
-device cpus,northbridge=nb,id=cpus,count=16 -device
On 13 February 2011 22:43, Anthony Liguori anth...@codemonkey.ws wrote:
On 02/13/2011 03:24 PM, Peter Maydell wrote:
How would this work for systems with multiple CPUs which have different
views of the world? (ie their memory maps differ so that eg some RAM is
shared between them but some
On 17 February 2011 13:37, Anthony Liguori anth...@codemonkey.ws wrote:
An application has to explicitly support an encoding. It is not
transparent. UCS2/UTF-16 means that strings are not 'const char *'s but
'const wchar_t *' where typedef unsigned short wchar_t;.
QEMU assumes, in lots of
On 6 April 2011 20:00, Luiz Capitulino lcapitul...@redhat.com wrote:
On Wed, 06 Apr 2011 20:17:47 +0200
Jan Kiszka jan.kis...@siemens.com wrote:
HMP is currently x86-only, thus it's probably OK to model it after some
PC feature (though I don't know if there aren't NMI buttons with BP-only
On 6 April 2011 20:34, Anthony Liguori anth...@codemonkey.ws wrote:
http://publib.boulder.ibm.com/infocenter/lnxinfo/v3r0m0/index.jsp?topic=/liaai/crashdump/liaaicrashdumpnmiipmi.htm
If an OS is totally hosed (spinning with interrupts disabled), and NMI can
be used to generate a crash dump.
On 10 January 2011 07:45, Stefan Hajnoczi stefa...@gmail.com wrote:
On Mon, Jan 10, 2011 at 1:05 PM, Jes Sorensen jes.soren...@redhat.com wrote:
Just to add a bit more background. Last year we discussed the issue of
whether to aim for a KVM Forum in the same style as we had in 2010, or
whether
Implement support for using the KVM in-kernel GIC for ARM.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/a15mpcore.c |8 ++-
hw/arm/Makefile.objs |1 +
hw/kvm/arm_gic.c | 162 ++
3 files changed, 170 insertions
Add presave/postload hooks to the ARM GIC common base class.
These will be used by the KVM in-kernel GIC subclass to sync
state between kernel and userspace when migrating.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/arm_gic_common.c | 10 ++
hw/arm_gic_internal.h
feels any of the todo-type stuff
is a blocker to these patches being committed that would
be good to know too :-))
Git tree if preferred:
git://git.linaro.org/people/pmaydell/qemu-arm.git kvm-arm-v12
Peter Maydell (6):
linux-headers: Add ARM KVM headers (not for upstream)
ARM: KVM: Add support
Enable KVM on ARM hosts, now that all the necessary components
for it exist.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
configure |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure b/configure
index c4a7837..f87bcd6 100755
--- a/configure
+++ b
This commit adds the ARM KVM headers. This is not to go to QEMU
upstream -- the correct path there is that the KVM code will be
committed to a mainline upstream kernel, and then upstream QEMU
can do a bulk header update from the upstream kernel, which will
allow us to drop this temporary commit.
On 10 October 2012 18:23, Andreas Färber afaer...@suse.de wrote:
Am 10.10.2012 17:07, schrieb Peter Maydell:
Implement support for using the KVM in-kernel GIC for ARM.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/a15mpcore.c |8 ++-
hw/arm/Makefile.objs |1
On 13 October 2012 10:09, Blue Swirl blauwir...@gmail.com wrote:
On Wed, Oct 10, 2012 at 3:07 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
From: Christoffer Dall cd...@cs.columbia.edu
Add basic support for KVM on ARM architecture.
+#include device_tree.h
Is this used?
Don't think so
On 14 October 2012 01:04, Christoffer Dall
c.d...@virtualopensystems.com wrote:
Used to initialize the in-kernel interrupt controller. On ARM we need to
map the virtual generic interrupt controller (vGIC) into Hyp the guest's
physicall address space so the guest can access the virtual cpu
On 14 October 2012 01:04, Christoffer Dall
c.d...@virtualopensystems.com wrote:
On ARM (and possibly other architectures) some bits are specific to the
model being emulated for the guest and user space needs a way to tell
the kernel about those bits. An example is mmio device base addresses,
On 17 October 2012 21:23, Christoffer Dall
c.d...@virtualopensystems.com wrote:
On Wed, Oct 17, 2012 at 4:21 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
+for the emulated platofrm (see KVM_SET_DEVICE_ADDRESS), but before the CPU
is
+initally run.
initially.
thanks a bunch
On 14 October 2012 01:04, Christoffer Dall
c.d...@virtualopensystems.com wrote:
We need this two factor initialization step to support a sane user space
initialization of the emulated model. We simply follow the names of the
ioctls for the internal vgic implementation steps and check if we
On 13 October 2012 10:09, Blue Swirl blauwir...@gmail.com wrote:
On Wed, Oct 10, 2012 at 3:07 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
+#include hw/arm-misc.h
+
+const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
'static'. In fact, 'static' not used at all in this file
On 18 October 2012 18:41, Jan Kiszka jan.kis...@siemens.com wrote:
Minor: If you do
function()
{
#ifdef CONFIG_KVM
...
#endif
}
+
qemu_irq *arm_pic_init_cpu(ARMCPU *cpu)
{
+#ifdef CONFIG_KVM
+if (kvm_enabled()) {
+return qemu_allocate_irqs(kvm_arm_pic_cpu_handler, cpu,
On 19 October 2012 19:46, Christoffer Dall
c.d...@virtualopensystems.com wrote:
On Wed, Oct 17, 2012 at 4:29 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
This doesn't say whether userspace is allowed to make this ioctl
multiple times for the same device. This could be any
-by: Peter Maydell peter.mayd...@linaro.org
---
This would otherwise cause us to ignore the architectures which
have moved over to uapi/ (which for QEMU's purposes means everything
but x86...)
scripts/update-linux-headers.sh |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/scripts
.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/kvm.c | 83 ++
target-arm/kvm_arm.h | 32 +++
2 files changed, 115 insertions(+)
create mode 100644 target-arm/kvm_arm.h
diff --git a/target-arm/kvm.c b
From: Christoffer Dall cd...@cs.columbia.edu
Add basic support for KVM on ARM architecture.
Signed-off-by: Christoffer Dall cd...@cs.columbia.edu
[PMM: Minor tweaks and code cleanup, switch to ONE_REG]
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/arm_pic.c | 26
-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/kvm.c | 78 +++---
1 file changed, 75 insertions(+), 3 deletions(-)
diff --git a/target-arm/kvm.c b/target-arm/kvm.c
index f80c707..f7d2235 100644
--- a/target-arm/kvm.c
+++ b/target-arm/kvm.c
Enable KVM on ARM hosts, now that all the necessary components
for it exist.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
configure |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure b/configure
index fa5657f..8173367 100755
--- a/configure
+++ b
On 23 October 2012 11:48, Jan Kiszka jan.kis...@siemens.com wrote:
The current irqchip API is like this:
KVM_CREATE_IRQCHIP (without any parameters)
...
KVM_CREATE_VCPU
KVM_SET_IRQCHIP (or the other way around)
...
KVM_RUN
The arguments you cannot pass via KVM_CREATE_IRQCHIP - which is
This commit adds the ARM KVM headers. This is not to go to QEMU
upstream -- the correct path there is that the KVM code will be
committed to a mainline upstream kernel, and then upstream QEMU
can do a bulk header update from the upstream kernel, which will
allow us to drop this temporary commit.
architecture
Peter Maydell (7):
linux-headers: Add ARM KVM headers (not for upstream)
ARM KVM: save and load VFP registers from kernel
hw/arm_gic: Add presave/postload hooks
linux-headers: update with VGIC related headers (not for upstream)
target-arm: Use MemoryListener to identify GIC
On 23 October 2012 12:00, Jan Kiszka jan.kis...@siemens.com wrote:
BTW, I guess we will regret that one-reg ABI one day and have to
introduce a multi-reg version again for hot-standby, i.e. continuous
state migration. I know we also do this for c86 MSRs - that interface
has the same
On 25 October 2012 10:21, Xiao Guangrong
xiaoguangr...@linux.vnet.ibm.com wrote:
Sync the header files by using scripts/update-linux-headers.sh
I think it would be good if this kind of patch included in the commit
message the kernel tree/branch and commit hash that the sync was with.
thanks
--
On 26 October 2012 10:58, Paolo Bonzini pbonz...@redhat.com wrote:
Wiring which MSI-X interrupts go to which source controllers. If you
have one source controller per PCI bridge, you need to tell the kernel
the mapping between MSI messages interrupts and PCI bridges, and update
it whenever
On 26 October 2012 11:44, Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
On Fri, 2012-10-26 at 12:15 +0200, Paolo Bonzini wrote:
QEMU's MSI-X routing is not x86-specific, so it should use the same
KVM_SET_GSI_ROUTING ioctl that x86 uses.
Well, that's the thing, I haven't managed to
On 26 October 2012 12:57, Paolo Bonzini pbonz...@redhat.com wrote:
If you exclude old-style PCI pass-through and limit yourself to vhost
and VFIO, you can treat irqfd as the in-kernel source of the
interrupt. Then you need a mapping between MSIs and numbers used in
KVM_IRQFD (GSIs).
This is
On 26 October 2012 23:03, Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
So the GSI bit. We can assume that GSIs in that context are basically
our global interrupt number. This would apply to pretty much every
platform indeed.
The routing here, if I understand things correctly,
Ping?
(patchwork url http://patchwork.ozlabs.org/patch/193125/)
thanks
-- PMM
On 22 October 2012 13:54, Peter Maydell peter.mayd...@linaro.org wrote:
Recent kernels have moved to keeping the userspace headers
in uapi/ subdirectories. This breaks the detection of whether an
architecture has
On 22 October 2012 08:51, Christoffer Dall
c.d...@virtualopensystems.com wrote:
+struct kvm_device_address {
+ __u32 id;
+ __u64 addr;
+};
Ben suggested that this should either be a 64 bit id or have explicit
padding. Other than that I think that our current proposed ABI for
ARM
On 19 November 2012 15:01, Will Deacon will.dea...@arm.com wrote:
On Sat, Nov 10, 2012 at 03:43:13PM +, Christoffer Dall wrote:
+/*
+ * A15-specific CP15 registers.
+ * Important: Must be sorted ascending by CRn, CRM, Op1, Op2
+ */
+static const struct coproc_reg a15_regs[] = {
+
This commit adds the ARM KVM headers. This is not to go to QEMU
upstream -- the correct path there is that the KVM code will be
committed to a mainline upstream kernel, and then upstream QEMU
can do a bulk header update from the upstream kernel, which will
allow us to drop this temporary commit.
ARM Linux (like x86-64 Linux) can use transparent hugepages for
KVM if memory blocks are 2MiB aligned; set QEMU_VMALLOC_ALIGN
accordingly.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
oslib-posix.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/oslib-posix.c
Implement support for using the KVM in-kernel GIC for ARM.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/a15mpcore.c |8 ++-
hw/arm/Makefile.objs |1 +
hw/kvm/arm_gic.c | 169 ++
3 files changed, 177 insertions
interface at
http://git.linaro.org/gitweb?p=people/pmaydell/qemu-arm.git;a=shortlog;h=refs/heads/kvm-arm-v14
Christoffer Dall (1):
ARM: KVM: Add support for KVM on ARM architecture
Peter Maydell (7):
linux-headers: Add ARM KVM headers (not for upstream)
ARM KVM: save and load VFP registers
Enable KVM on ARM hosts, now that all the necessary components
for it exist.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
configure |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure b/configure
index 780b19a..2438d6d 100755
--- a/configure
+++ b
From: Christoffer Dall cd...@cs.columbia.edu
Add basic support for KVM on ARM architecture.
Signed-off-by: Christoffer Dall cd...@cs.columbia.edu
[PMM: Minor tweaks and code cleanup, switch to ONE_REG]
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/arm_pic.c | 26
-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/kvm.c | 78 +++---
1 file changed, 75 insertions(+), 3 deletions(-)
diff --git a/target-arm/kvm.c b/target-arm/kvm.c
index 8e4b989..4217ad6 100644
--- a/target-arm/kvm.c
+++ b/target-arm/kvm.c
Add presave/postload hooks to the ARM GIC common base class.
These will be used by the KVM in-kernel GIC subclass to sync
state between kernel and userspace when migrating.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Andreas Färber afaer...@suse.de
---
hw/arm_gic_common.c
.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/kvm.c | 83 ++
target-arm/kvm_arm.h | 32 +++
2 files changed, 115 insertions(+)
create mode 100644 target-arm/kvm_arm.h
diff --git a/target-arm/kvm.c b
On 20 November 2012 14:37, Alexander Graf ag...@suse.de wrote:
On 11/20/2012 02:55 PM, Christoffer Dall wrote:
On Tue, Nov 20, 2012 at 8:54 AM, Alexander Grafag...@suse.de wrote:
On 11/20/2012 02:31 PM, Peter Maydell wrote:
ARM Linux (like x86-64 Linux) can use transparent hugepages for
KVM
On 22 November 2012 15:58, Will Deacon will.dea...@arm.com wrote:
+++ b/tools/kvm/arm/aarch32/smp-pen.S
@@ -0,0 +1,30 @@
+#include kvm/kvm-arch.h
+
+#include arm-common/gic.h
+
+ .arm
+
+ .globl smp_pen_start
+ .globl smp_jump_addr
+ .globl smp_pen_end
+
+
On 22 November 2012 21:00, Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
Oh it's simple enough initially, just move the ioctl call from generic
kvm init to machine init. The problem is then to add an argument, since
that essentially means changing the ioctl number, but we need that for
On 29 November 2012 15:58, Marc Zyngier marc.zyng...@arm.com wrote:
A bug in the KVM GIC init code set the priority mask to the
highest possible value, while the reset value should be zero.
Now that the kernel bug is fixed, kvm-tool must properly configure
its GIC CPU interface in order to
On 27 November 2012 19:45, Alex Williamson alex.william...@redhat.com wrote:
kvm_check_extension() explodes when KVM isn't enabled so we need to
first test whether KVM is enabled. Use kvm_irqchip_in_kernel() for
this since it matches the test we do before using this result.
---
On 3 December 2012 10:36, Dong Aisheng b29...@freescale.com wrote:
The patch is mainly for implementing the vgic state save and retore function.
I'm not sure the current implementation method is the most proper way.
So i'd like to send out the patch for RFC on the direction and issues i met
On 3 December 2012 12:02, Peter Maydell peter.mayd...@linaro.org wrote:
By far the largest part of the save/restore work here is figuring out
what the right state to expose to userspace is so we can retain that
compatibility guarantee.
Some further thoughts on this...
What we're really
On 4 December 2012 11:44, Dong Aisheng b29...@freescale.com wrote:
On Mon, Dec 03, 2012 at 12:02:55PM +, Peter Maydell wrote:
Probably one way we could try to avoid this issue is also saving the
banked registers value in kernel, then using it as return value of ONE_REG
access of specified
On 4 December 2012 12:27, Dong Aisheng b29...@freescale.com wrote:
On Mon, Dec 03, 2012 at 01:22:07PM +, Peter Maydell wrote:
What we're really providing the guest here is a hardware-accelerated
software emulation of a no-virtualization GICv2. So it's better for
the state we expose
On 4 December 2012 13:37, Dong Aisheng b29...@freescale.com wrote:
On Tue, Dec 04, 2012 at 12:45:12PM +, Peter Maydell wrote:
On 4 December 2012 12:27, Dong Aisheng b29...@freescale.com wrote:
On Mon, Dec 03, 2012 at 01:22:07PM +, Peter Maydell wrote:
What we're really providing
On 7 December 2012 12:50, Cornelia Huck cornelia.h...@de.ibm.com wrote:
Signed-off-by: Cornelia Huck cornelia.h...@de.ibm.com
I think it would be good if commit messages for linux-headers
updates stated the kernel tree and commit that the updated headers
come from.
-- PMM
--
To unsubscribe from
On 4 July 2011 23:00, Raghavendra D Prabhu raghu.prabh...@gmail.com wrote:
This is to avoid gcc optimizating out the comparison in assert,
due to assumption of signed overflow being undefined by default
(-Werror=strict-overflow).
--- a/Makefile.hw
+++ b/Makefile.hw
@@ -9,7 +9,7 @@ include
On 5 July 2011 07:15, Markus Armbruster arm...@redhat.com wrote:
+ int fd, __attribute__((unused)) ret;
snprintf(reset_file, sizeof(reset_file),
/sys/bus/pci/devices/%04x:%02x:%02x.%01x/reset,
What about (void)write() and do away with ret?
If 'ret' has been used to
On 25 July 2011 10:32, Alexander Graf ag...@suse.de wrote:
On 25.07.2011, at 10:51, Avi Kivity wrote:
qemu_malloc() is type-unsafe as it returns a void pointer. Introduce
QEMU_NEW() (and QEMU_NEWZ()), which return the correct type.
What does this buy you over
type *x =
On 8 August 2011 13:56, Avi Kivity a...@redhat.com wrote:
QEMU deals with a lot of fixed width integer types; their names
(uint64_t etc) are clumsy to use and take up a lot of space.
Following Linux, introduce shorter names, for example U64 for
uint64_t.
Strongly disagree. uint64_t c are
On 8 August 2011 18:06, Avi Kivity a...@redhat.com wrote:
Somewhat clumsy since it needs a variable sized region.
@@ -119,7 +120,7 @@ void omap_sdrc_reset(struct omap_sdrc_s *s);
struct omap_gpmc_s;
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
void
On 9 August 2011 07:34, Avi Kivity a...@redhat.com wrote:
Also, my patchset focuses on mechanical transformations. It is already
risky enough in terms of regressions, I'm not going to rewrite/improve all
of qemu; if you want those callbacks removed, you will have to remove them
yourself.
On 8 August 2011 18:06, Avi Kivity a...@redhat.com wrote:
diff --git a/hw/tusb6010.h b/hw/tusb6010.h
new file mode 100644
index 000..6faa94d
--- /dev/null
+++ b/hw/tusb6010.h
@@ -0,0 +1,10 @@
+#ifndef TUSB6010_H
+#define TUSB6010_H
+
+typedef struct TUSBState TUSBState;
+TUSBState
On 9 August 2011 08:41, Avi Kivity a...@redhat.com wrote:
On 08/09/2011 10:37 AM, Peter Maydell wrote:
On 9 August 2011 07:34, Avi Kivitya...@redhat.com wrote:
Also, my patchset focuses on mechanical transformations. It is already
risky enough in terms of regressions, I'm not going
On 9 August 2011 10:02, Avi Kivity a...@redhat.com wrote:
+static const MemoryRegionOps omap_gpmc_ops = {
+ .read = omap_gpmc_read,
+ .write = omap_gpmc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+
On 9 August 2011 10:26, Avi Kivity a...@redhat.com wrote:
On 08/09/2011 12:23 PM, Peter Maydell wrote:
On 9 August 2011 10:02, Avi Kivitya...@redhat.com wrote:
+static const MemoryRegionOps omap_gpmc_ops = {
+ .read = omap_gpmc_read,
+ .write = omap_gpmc_write
On 8 August 2011 18:07, Avi Kivity a...@redhat.com wrote:
-static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
+static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
uint32_t val;
-
On 11 August 2011 17:29, Avi Kivity a...@redhat.com wrote:
-static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
uint32_t val;
-
On 8 August 2011 18:07, Avi Kivity a...@redhat.com wrote:
This tells the sysbus code it need not use IO_MEM_UNASSIGNED.
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/arm11mpcore.c | 7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/hw/arm11mpcore.c
On 7 August 2012 14:59, Avi Kivity a...@redhat.com wrote:
On 08/06/2012 08:20 PM, Peter Maydell wrote:
On 3 July 2012 10:01, Christoffer Dall c.d...@virtualopensystems.com wrote:
From: Christoffer Dall cd...@cs.columbia.edu
Userspace can inject IRQs and FIQs through the KVM_IRQ_LINE VM ioctl
On 7 August 2012 15:28, Avi Kivity a...@redhat.com wrote:
On 08/07/2012 05:12 PM, Peter Maydell wrote:
On 7 August 2012 14:59, Avi Kivity a...@redhat.com wrote:
What do you mean by per-vcpu version of KVM_IRQ_LINE?
The ARM VGIC implementation implements I need to raise per-CPU
interrupt X
On 2 August 2012 10:14, Jan Kiszka jan.kis...@web.de wrote:
On 2012-07-26 16:35, Peter Maydell wrote:
This patch series removes all uses of kvm_irqchip_in_kernel()
from architecture-independent code, by creating a set of more
specific functions instead to test for the particular aspects
On 7 August 2012 15:52, Cornelia Huck cornelia.h...@de.ibm.com wrote:
+static void sch_handle_clear_func(SubchDev *sch)
+{
+struct pmcw *p = sch-curr_status.pmcw;
+struct scsw *s = sch-curr_status.scsw;
+int path;
+
+/* Path management: In our simple css, we always choose
On 8 August 2012 07:25, Liu Ping Fan qemul...@gmail.com wrote:
+static inline void atomic_sub(int i, Atomic *v)
+{
+asm volatile(lock; subl %1,%0
+ : +m (v-counter)
+ : ir (i));
+}
NAK. We don't want random inline assembly implementations of locking
primitives in
On 8 August 2012 07:25, Liu Ping Fan qemul...@gmail.com wrote:
From: Liu Ping Fan pingf...@linux.vnet.ibm.com
lock:
qemu_device_tree_mutex
Looking at where it's used, this doesn't seem to have anything to do
with device trees (ie dtb, see www.devicetree.org) : poorly named lock?
-- PMM
--
On 8 August 2012 14:18, Paolo Bonzini pbonz...@redhat.com wrote:
Il 08/08/2012 15:09, Stefan Hajnoczi ha scritto:
No need to roll our own or copy the implementation from the kernel.
To some extent we need to because:
1. GCC atomics look ugly, :) do not provide rmb/wmb, and in some
versions
On 8 August 2012 20:16, Blue Swirl blauwir...@gmail.com wrote:
On Wed, Aug 8, 2012 at 8:17 AM, Cornelia Huck cornelia.h...@de.ibm.com
wrote:
On Tue, 7 Aug 2012 21:00:59 +
Blue Swirl blauwir...@gmail.com wrote:
Please use more descriptive names instead of acronyms, for example
Add presave/postload hooks to the ARM GIC common base class.
These will be used by the KVM in-kernel GIC subclass to sync
state between kernel and userspace when migrating.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/arm_gic_common.c | 10 ++
hw/arm_gic_internal.h
]
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/arm_pic.c | 28 +
target-arm/Makefile.objs |1 +
target-arm/cpu.h |1 +
target-arm/helper.c |2 +-
target-arm/kvm.c | 274 ++
5 files changed
Enable KVM on ARM hosts, now that all the necessary components
for it exist.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
configure |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure b/configure
index b9a0b27..f7a825a 100755
--- a/configure
+++ b
, the latter encodes
cpu number in the irq number), and we should standardise on one
approach or the other
Christoffer Dall (1):
ARM: KVM: Add support for KVM on ARM architecture
Peter Maydell (4):
linux-headers: Add ARM KVM headers (not for upstream)
hw/arm_gic: Add presave/postload hooks
hw
Implement support for using the KVM in-kernel GIC for ARM.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/a15mpcore.c | 11 +++-
hw/arm/Makefile.objs |1 +
hw/kvm/arm_gic.c | 153 ++
3 files changed, 164 insertions
Ping? I don't think this one quite made it into Avi's pullreq...
thanks
-- PMM
On 6 August 2012 18:05, Peter Maydell peter.mayd...@linaro.org wrote:
Move the init of the irqchip_inject_ioctl field of KVMState out of
kvm_irqchip_create() and into kvm_init(), so that kvm_set_irq()
can be used
On 13 August 2012 21:45, Marcelo Tosatti mtosa...@redhat.com wrote:
On Sun, Aug 12, 2012 at 02:13:52PM +0100, Peter Maydell wrote:
Ping? I don't think this one quite made it into Avi's pullreq...
Please post this with the rest of the code to support the new
s-irqchip_inject_ioctl value.
Er
On 14 August 2012 08:33, Jan Kiszka jan.kis...@web.de wrote:
Either you move both or none.
OK.
KVM_IRQ_LINE is old-style, deprecated, KVM_IRQ_LINE_STATUS (i.e
injection with feedback to allow lost-tick compensation) is the current
standard that other archs should pick up.
Can it be
On 14 August 2012 08:42, Jan Kiszka jan.kis...@web.de wrote:
On 2012-08-14 09:40, Peter Maydell wrote:
On 14 August 2012 08:33, Jan Kiszka jan.kis...@web.de wrote:
KVM_IRQ_LINE is old-style, deprecated, KVM_IRQ_LINE_STATUS (i.e
injection with feedback to allow lost-tick compensation
On 14 August 2012 09:09, Jan Kiszka jan.kis...@web.de wrote:
On 2012-08-14 09:52, Peter Maydell wrote:
Well, you appear to know what this variant ioctl does and why it's
better than KVM_IRQ_LINE, whereas I don't. I just want to deliver
an interrupt, KVM_IRQ_LINE lets me deliver an interrupt
On 14 August 2012 19:53, Anthony Liguori anth...@codemonkey.ws wrote:
Forget about !x86 platforms. They have their own way to do this sort of
thing. Think of this feature like a status LED on a motherboard. These
are very common and usually controlled by IO ports.
Please don't forget !x86
at:
git://git.kernel.org/pub/scm/virt/kvm/qemu-kvm.git uq/master
Jan Kiszka (3):
kvm: i8254: Cache kernel clock offset in KVMPITState
kvm: i8254: Finish time conversion fix
kvmvapic: Disable if there is insufficient memory
Peter Maydell (1):
update-linux
Move the init of the irqchip_inject_ioctl field of KVMState out of
kvm_irqchip_create() and into kvm_init(), so that kvm_set_irq()
can be used even when no irqchip is created (for architectures
that support async interrupt notification even without an in
kernel irqchip).
Signed-off-by: Peter
On 19 August 2012 05:34, Christoffer Dall c.d...@virtualopensystems.com wrote:
On Thu, Aug 16, 2012 at 2:25 PM, Alexander Graf ag...@suse.de wrote:
A single hva can have multiple gpas mapped, no? At least that's what I
gathered
from the discussion about my attempt to a function similar to
On 21 August 2012 09:19, Jan Kiszka jan.kis...@siemens.com wrote:
On 2012-08-15 13:08, Peter Maydell wrote:
Move the init of the irqchip_inject_ioctl field of KVMState out of
kvm_irqchip_create() and into kvm_init(), so that kvm_set_irq()
can be used even when no irqchip is created
On 23 August 2012 10:13, Marcelo Tosatti mtosa...@redhat.com wrote:
On Tue, Aug 21, 2012 at 12:27:51PM +0200, Jan Kiszka wrote:
On 2012-08-21 10:25, Peter Maydell wrote:
On 21 August 2012 09:19, Jan Kiszka jan.kis...@siemens.com wrote:
As it's not yet merged, some late comment
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