Re: [PATCH v2 19/21] arm64: KVM: Turn system register numbers to an enum

2015-12-02 Thread Marc Zyngier 
On 02/12/15 11:51, Christoffer Dall wrote:
> On Fri, Nov 27, 2015 at 06:50:13PM +, Marc Zyngier wrote:
>> Having the system register numbers as #defines has been a pain
>> since day one, as the ordering is pretty fragile, and moving
>> things around leads to renumbering and epic conflict resolutions.
>>
>> Now that we're mostly acessing the sysreg file in C, an enum is
>> a much better type to use, and we can clean things up a bit.
>>
>> Signed-off-by: Marc Zyngier 
>> ---
>>  arch/arm64/include/asm/kvm_asm.h | 76 -
>>  arch/arm64/include/asm/kvm_emulate.h |  1 -
>>  arch/arm64/include/asm/kvm_host.h| 81 
>> +++-
>>  arch/arm64/include/asm/kvm_mmio.h|  1 -
>>  arch/arm64/kernel/asm-offsets.c  |  1 +
>>  arch/arm64/kvm/guest.c   |  1 -
>>  arch/arm64/kvm/handle_exit.c |  1 +
>>  arch/arm64/kvm/hyp/debug-sr.c|  1 +
>>  arch/arm64/kvm/hyp/entry.S   |  3 +-
>>  arch/arm64/kvm/hyp/sysreg-sr.c   |  1 +
>>  arch/arm64/kvm/sys_regs.c|  1 +
>>  virt/kvm/arm/vgic-v3.c   |  1 +
>>  12 files changed, 87 insertions(+), 82 deletions(-)
>>
>> diff --git a/arch/arm64/include/asm/kvm_asm.h 
>> b/arch/arm64/include/asm/kvm_asm.h
>> index 5e37710..52b777b 100644
>> --- a/arch/arm64/include/asm/kvm_asm.h
>> +++ b/arch/arm64/include/asm/kvm_asm.h
>> @@ -20,82 +20,6 @@
>>  
>>  #include 
>>  
>> -/*
>> - * 0 is reserved as an invalid value.
>> - * Order *must* be kept in sync with the hyp switch code.
>> - */
>> -#define MPIDR_EL1   1   /* MultiProcessor Affinity Register */
>> -#define CSSELR_EL1  2   /* Cache Size Selection Register */
>> -#define SCTLR_EL1   3   /* System Control Register */
>> -#define ACTLR_EL1   4   /* Auxiliary Control Register */
>> -#define CPACR_EL1   5   /* Coprocessor Access Control */
>> -#define TTBR0_EL1   6   /* Translation Table Base Register 0 */
>> -#define TTBR1_EL1   7   /* Translation Table Base Register 1 */
>> -#define TCR_EL1 8   /* Translation Control Register */
>> -#define ESR_EL1 9   /* Exception Syndrome Register */
>> -#define AFSR0_EL1   10  /* Auxilary Fault Status Register 0 */
>> -#define AFSR1_EL1   11  /* Auxilary Fault Status Register 1 */
>> -#define FAR_EL1 12  /* Fault Address Register */
>> -#define MAIR_EL113  /* Memory Attribute Indirection 
>> Register */
>> -#define VBAR_EL114  /* Vector Base Address Register */
>> -#define CONTEXTIDR_EL1  15  /* Context ID Register */
>> -#define TPIDR_EL0   16  /* Thread ID, User R/W */
>> -#define TPIDRRO_EL0 17  /* Thread ID, User R/O */
>> -#define TPIDR_EL1   18  /* Thread ID, Privileged */
>> -#define AMAIR_EL1   19  /* Aux Memory Attribute Indirection 
>> Register */
>> -#define CNTKCTL_EL1 20  /* Timer Control Register (EL1) */
>> -#define PAR_EL1 21  /* Physical Address Register */
>> -#define MDSCR_EL1   22  /* Monitor Debug System Control Register */
>> -#define MDCCINT_EL1 23  /* Monitor Debug Comms Channel Interrupt Enable 
>> Reg */
>> -
>> -/* 32bit specific registers. Keep them at the end of the range */
>> -#define DACR32_EL2  24  /* Domain Access Control Register */
>> -#define IFSR32_EL2  25  /* Instruction Fault Status Register */
>> -#define FPEXC32_EL2 26  /* Floating-Point Exception Control 
>> Register */
>> -#define DBGVCR32_EL227  /* Debug Vector Catch Register */
>> -#define NR_SYS_REGS 28
>> -
>> -/* 32bit mapping */
>> -#define c0_MPIDR(MPIDR_EL1 * 2) /* MultiProcessor ID Register */
>> -#define c0_CSSELR   (CSSELR_EL1 * 2)/* Cache Size Selection Register */
>> -#define c1_SCTLR(SCTLR_EL1 * 2) /* System Control Register */
>> -#define c1_ACTLR(ACTLR_EL1 * 2) /* Auxiliary Control Register */
>> -#define c1_CPACR(CPACR_EL1 * 2) /* Coprocessor Access Control */
>> -#define c2_TTBR0(TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
>> -#define c2_TTBR0_high   (c2_TTBR0 + 1)  /* TTBR0 top 32 bits */
>> -#define c2_TTBR1(TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
>> -#define c2_TTBR1_high   (c2_TTBR1 + 1)  /* TTBR1 top 32 bits */
>> -#define c2_TTBCR(TCR_EL1 * 2)   /* Translation Table Base Control R. */
>> -#define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control 
>> Register */
>> -#define c5_DFSR (ESR_EL1 * 2)   /* Data Fault Status Register */
>> -#define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status 
>> Register */
>> -#define c5_ADFSR(AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
>> -#define c5_AIFSR(AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
>> -#define c6_DFAR (FAR_EL1 * 2)

Re: [PATCH v2 19/21] arm64: KVM: Turn system register numbers to an enum

2015-12-02 Thread Christoffer Dall 
On Fri, Nov 27, 2015 at 06:50:13PM +, Marc Zyngier wrote:
> Having the system register numbers as #defines has been a pain
> since day one, as the ordering is pretty fragile, and moving
> things around leads to renumbering and epic conflict resolutions.
> 
> Now that we're mostly acessing the sysreg file in C, an enum is
> a much better type to use, and we can clean things up a bit.
> 
> Signed-off-by: Marc Zyngier 
> ---
>  arch/arm64/include/asm/kvm_asm.h | 76 -
>  arch/arm64/include/asm/kvm_emulate.h |  1 -
>  arch/arm64/include/asm/kvm_host.h| 81 
> +++-
>  arch/arm64/include/asm/kvm_mmio.h|  1 -
>  arch/arm64/kernel/asm-offsets.c  |  1 +
>  arch/arm64/kvm/guest.c   |  1 -
>  arch/arm64/kvm/handle_exit.c |  1 +
>  arch/arm64/kvm/hyp/debug-sr.c|  1 +
>  arch/arm64/kvm/hyp/entry.S   |  3 +-
>  arch/arm64/kvm/hyp/sysreg-sr.c   |  1 +
>  arch/arm64/kvm/sys_regs.c|  1 +
>  virt/kvm/arm/vgic-v3.c   |  1 +
>  12 files changed, 87 insertions(+), 82 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/kvm_asm.h 
> b/arch/arm64/include/asm/kvm_asm.h
> index 5e37710..52b777b 100644
> --- a/arch/arm64/include/asm/kvm_asm.h
> +++ b/arch/arm64/include/asm/kvm_asm.h
> @@ -20,82 +20,6 @@
>  
>  #include 
>  
> -/*
> - * 0 is reserved as an invalid value.
> - * Order *must* be kept in sync with the hyp switch code.
> - */
> -#define  MPIDR_EL1   1   /* MultiProcessor Affinity Register */
> -#define  CSSELR_EL1  2   /* Cache Size Selection Register */
> -#define  SCTLR_EL1   3   /* System Control Register */
> -#define  ACTLR_EL1   4   /* Auxiliary Control Register */
> -#define  CPACR_EL1   5   /* Coprocessor Access Control */
> -#define  TTBR0_EL1   6   /* Translation Table Base Register 0 */
> -#define  TTBR1_EL1   7   /* Translation Table Base Register 1 */
> -#define  TCR_EL1 8   /* Translation Control Register */
> -#define  ESR_EL1 9   /* Exception Syndrome Register */
> -#define  AFSR0_EL1   10  /* Auxilary Fault Status Register 0 */
> -#define  AFSR1_EL1   11  /* Auxilary Fault Status Register 1 */
> -#define  FAR_EL1 12  /* Fault Address Register */
> -#define  MAIR_EL113  /* Memory Attribute Indirection 
> Register */
> -#define  VBAR_EL114  /* Vector Base Address Register */
> -#define  CONTEXTIDR_EL1  15  /* Context ID Register */
> -#define  TPIDR_EL0   16  /* Thread ID, User R/W */
> -#define  TPIDRRO_EL0 17  /* Thread ID, User R/O */
> -#define  TPIDR_EL1   18  /* Thread ID, Privileged */
> -#define  AMAIR_EL1   19  /* Aux Memory Attribute Indirection 
> Register */
> -#define  CNTKCTL_EL1 20  /* Timer Control Register (EL1) */
> -#define  PAR_EL1 21  /* Physical Address Register */
> -#define MDSCR_EL122  /* Monitor Debug System Control Register */
> -#define MDCCINT_EL1  23  /* Monitor Debug Comms Channel Interrupt Enable 
> Reg */
> -
> -/* 32bit specific registers. Keep them at the end of the range */
> -#define  DACR32_EL2  24  /* Domain Access Control Register */
> -#define  IFSR32_EL2  25  /* Instruction Fault Status Register */
> -#define  FPEXC32_EL2 26  /* Floating-Point Exception Control 
> Register */
> -#define  DBGVCR32_EL227  /* Debug Vector Catch Register */
> -#define  NR_SYS_REGS 28
> -
> -/* 32bit mapping */
> -#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
> -#define c0_CSSELR(CSSELR_EL1 * 2)/* Cache Size Selection Register */
> -#define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
> -#define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
> -#define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
> -#define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
> -#define c2_TTBR0_high(c2_TTBR0 + 1)  /* TTBR0 top 32 bits */
> -#define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
> -#define c2_TTBR1_high(c2_TTBR1 + 1)  /* TTBR1 top 32 bits */
> -#define c2_TTBCR (TCR_EL1 * 2)   /* Translation Table Base Control R. */
> -#define c3_DACR  (DACR32_EL2 * 2)/* Domain Access Control 
> Register */
> -#define c5_DFSR  (ESR_EL1 * 2)   /* Data Fault Status Register */
> -#define c5_IFSR  (IFSR32_EL2 * 2)/* Instruction Fault Status 
> Register */
> -#define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
> -#define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
> -#define c6_DFAR  (FAR_EL1 * 2)   /* Data Fault Address Register 
> */
> -#define c6_IFAR  (c6_DFAR + 1)   /*