On 19 February 2015 at 13:40, Marc Zyngier marc.zyng...@arm.com wrote:
On 19/02/15 10:54, Ard Biesheuvel wrote:
---
arch/arm/kvm/mmu.c | 2 +-
arch/arm64/include/asm/kvm_arm.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/kvm/mmu.c
On Tue, Jan 27, 2015 at 12:33:26PM +0530, Pranavkumar Sawargaonkar wrote:
In APM X-Gene, GIC register space is 64K aligned while the sizes mentioned
in the dt are 4K aligned. This breaks KVM when kernel is built with 64K page
size due to size alignment checking in vgic driver for VCPU Control
On Tue, Jan 27, 2015 at 1:03 AM, Pranavkumar Sawargaonkar
psawargaon...@apm.com wrote:
In APM X-Gene, GIC register space is 64K aligned while the sizes mentioned
in the dt are 4K aligned. This breaks KVM when kernel is built with 64K page
size due to size alignment checking in vgic driver for
On Thu, Feb 19, 2015 at 12:23:15PM -0600, Rob Herring wrote:
On Tue, Jan 27, 2015 at 1:03 AM, Pranavkumar Sawargaonkar
psawargaon...@apm.com wrote:
In APM X-Gene, GIC register space is 64K aligned while the sizes mentioned
in the dt are 4K aligned. This breaks KVM when kernel is built with
On 19 February 2015 at 14:50, Alexander Graf ag...@suse.de wrote:
On 19.02.15 11:54, Ard Biesheuvel wrote:
This is a 0th order approximation of how we could potentially force the guest
to avoid uncached mappings, at least from the moment the MMU is on. (Before
that, all of memory is
On Thu, Feb 19, 2015 at 10:54:43AM +, Ard Biesheuvel wrote:
This is a 0th order approximation of how we could potentially force the guest
to avoid uncached mappings, at least from the moment the MMU is on. (Before
that, all of memory is implicitly classified as Device-nGnRnE)
The idea
On 19/02/2015 18:55, Andrew Jones wrote:
(I don't have an exact number for how many times it went to EL1 because
access_mair() doesn't have a trace point.)
(I got the 62873 number by testing a 3rd kernel build that only had patch
3/3 applied to the base, and counting
