On Mon, Jun 22, 2015 at 06:41:32PM +0800, Zhichao Huang wrote:
Implement switching of the debug registers. While the number
of registers is massive, CPUs usually don't implement them all
(A15 has 6 breakpoints and 4 watchpoints, which gives us a total
of 22 registers only).
Notice that, for
On Mon, Jun 22, 2015 at 06:41:26PM +0800, Zhichao Huang wrote:
Add #ifndef __ASSEMBLY__ in hw_breakpoint.h, in order to use
the ARM_DSCR_MDBGEN macro from KVM assembly code.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
Reviewed-by: Alex Bennee alex.ben...@linaro.org
Acked-by:
On Mon, Jun 22, 2015 at 06:41:34PM +0800, Zhichao Huang wrote:
Enable trapping of the debug registers, allowing guests to use
the debug infrastructure.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/kvm/interrupts_head.S | 15 +--
1 file changed, 13
On Mon, Jun 22, 2015 at 06:41:25PM +0800, Zhichao Huang wrote:
pm_fake doesn't quite describe what the handler does (ignoring writes
and returning 0 for reads).
As we're about to use it (a lot) in a different context, rename it
with a (admitedly cryptic) name that make sense for all users.
On Mon, Jun 22, 2015 at 06:41:28PM +0800, Zhichao Huang wrote:
We now have multiple tables for the various system registers
we trap. Make sure we check the order of all of them, as it is
critical that we get the order right (been there, done that...).
Signed-off-by: Zhichao Huang
On Fri, Jun 26, 2015 at 02:16:18PM +0100, Andre Przywara wrote:
Currently we unconditionally create a virtual GICv2 in the guest.
Add a --irqchip= parameter to let the user specify a different GIC
type for the guest, when omitting this parameter it still defaults to
--irqchip=gicv2.
For now
This fixes two instances where a pgprot_t is used as the operand
of a bitwise operation. In order to comply with STRICT_MM_TYPECHECKS,
bitwise arithmetic on a pgprot_t should go via the pgprot_val()
accessor.
Cc: kvmarm@lists.cs.columbia.edu
Signed-off-by: Ard Biesheuvel
On Tue, Jun 30, 2015 at 06:04:50PM +0200, Ard Biesheuvel wrote:
This fixes two instances where a pgprot_t is used as the operand
of a bitwise operation. In order to comply with STRICT_MM_TYPECHECKS,
bitwise arithmetic on a pgprot_t should go via the pgprot_val()
accessor.
Cc:
Hi,
On 30/06/15 17:09, Will Deacon wrote:
On Fri, Jun 26, 2015 at 02:16:15PM +0100, Andre Przywara wrote:
Currently the ARM GIC checks the number of VCPUs against a fixed
limit, which is GICv2 specific. Don't pretend we know better than the
kernel and let's get rid of that explicit check.
On Mon, Jun 08, 2015 at 06:04:01PM +0100, Marc Zyngier wrote:
In order to be able to feed physical interrupts to a guest, we need
to be able to establish the virtual-physical mapping between the two
worlds.
The mapping is kept in a rbtree, indexed by virtual interrupts.
how many of these do
On Mon, Jun 08, 2015 at 06:03:56PM +0100, Marc Zyngier wrote:
As we now inject the timer interrupt when we're about to enter
the guest, it makes a lot more sense to make sure this happens
before the vgic code queues the pending interrupts.
Otherwise, we get the interrupt on the following
On Mon, Jun 08, 2015 at 06:04:05PM +0100, Marc Zyngier wrote:
So far, the only use of the HW interrupt facility is the timer,
implying that the active state is context-switched for each vcpu,
as the device is is shared across all vcpus.
This does not work for a device that has been assigned
On Mon, Jun 08, 2015 at 06:03:57PM +0100, Marc Zyngier wrote:
As we're about to introduce some serious GIC-poking to the vgic code,
it is important to make sure that we're going to poke the part of
the GIC that belongs to the CPU we're about to run on (otherwise,
we'd end up with some
On Mon, Jun 22, 2015 at 06:41:31PM +0800, Zhichao Huang wrote:
The trapping code keeps track of the state of the debug registers,
allowing for the switch code to implement a lazy switching strategy.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
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arch/arm/include/asm/kvm_asm.h |
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