Re: [PATCH v2 21/21] arm64: KVM: Remove weak attributes

On 02/12/15 11:47, Christoffer Dall wrote: > On Fri, Nov 27, 2015 at 06:50:15PM +, Marc Zyngier wrote: >> As we've now switched to the new world switch implementation, >> remove the weak attributes, as nobody is supposed to override >> it anymore. > > Why not remove the aliases and change the

Re: [PATCH v2 19/21] arm64: KVM: Turn system register numbers to an enum

On 02/12/15 11:51, Christoffer Dall wrote: > On Fri, Nov 27, 2015 at 06:50:13PM +, Marc Zyngier wrote: >> Having the system register numbers as #defines has been a pain >> since day one, as the ordering is pretty fragile, and moving >> things around leads to renumbering and epic conflict

Re: [PATCH v2 16/21] arm64: KVM: Add compatibility aliases

On 02/12/15 11:49, Christoffer Dall wrote: > On Fri, Nov 27, 2015 at 06:50:10PM +, Marc Zyngier wrote: >> So far, we've implemented the new world switch with a completely >> different namespace, so that we could have both implementation >> compiled in. >> >> Let's take things one step further

Re: [PATCH v2 10/21] arm64: KVM: Add patchable function selector

On Wed, Dec 02, 2015 at 01:19:22PM +, Marc Zyngier wrote: > On 02/12/15 11:53, Christoffer Dall wrote: > > On Wed, Dec 02, 2015 at 09:47:43AM +, Marc Zyngier wrote: > >> On 02/12/15 09:27, Christoffer Dall wrote: > >>> On Tue, Dec 01, 2015 at 06:51:00PM +, Marc Zyngier wrote: > On

Re: [PATCH v2 12/21] arm64: KVM: Implement fpsimd save/restore

On Wed, Dec 02, 2015 at 03:29:50PM +, Marc Zyngier wrote: > On 02/12/15 11:53, Christoffer Dall wrote: > > On Fri, Nov 27, 2015 at 06:50:06PM +, Marc Zyngier wrote: > >> Implement the fpsimd save restore, keeping the lazy part in > >> assembler (as returning to C would be overkill). > >> >

Re: [PATCH v2 21/21] arm64: KVM: Remove weak attributes

On Wed, Dec 02, 2015 at 03:21:49PM +, Marc Zyngier wrote: > On 02/12/15 11:47, Christoffer Dall wrote: > > On Fri, Nov 27, 2015 at 06:50:15PM +, Marc Zyngier wrote: > >> As we've now switched to the new world switch implementation, > >> remove the weak attributes, as nobody is supposed to

Re: [PATCH v4 18/21] KVM: ARM64: Add PMU overflow interrupt routing

On Wed, Dec 02, 2015 at 10:22:04AM +, Marc Zyngier wrote: > On 02/12/15 09:49, Shannon Zhao wrote: > > > > > > On 2015/12/2 16:45, Marc Zyngier wrote: > >> On 02/12/15 02:40, Shannon Zhao wrote: > > > On 2015/12/2 0:57, Marc Zyngier wrote: > >> On 01/12/15 16:26, Shannon

Re: [PATCH v2 12/21] arm64: KVM: Implement fpsimd save/restore

On 02/12/15 11:53, Christoffer Dall wrote: > On Fri, Nov 27, 2015 at 06:50:06PM +, Marc Zyngier wrote: >> Implement the fpsimd save restore, keeping the lazy part in >> assembler (as returning to C would be overkill). >> >> Signed-off-by: Marc Zyngier >> --- >>

Re: [PATCH v2 21/21] arm64: KVM: Remove weak attributes

On 02/12/15 16:21, Christoffer Dall wrote: > On Wed, Dec 02, 2015 at 03:21:49PM +, Marc Zyngier wrote: >> On 02/12/15 11:47, Christoffer Dall wrote: >>> On Fri, Nov 27, 2015 at 06:50:15PM +, Marc Zyngier wrote: As we've now switched to the new world switch implementation, remove

Re: [PATCH] KVM: arm/arm64: Revert to old way of checking for device mapping in stage2_flush_ptes().

Hi Pavel, Thanks for getting to the bottom of this. On 1 December 2015 at 14:03, Pavel Fedin wrote: > This function takes stage-II physical addresses (A.K.A. IPA), on input, not > real physical addresses. This causes kvm_is_device_pfn() to return wrong > values, depending

Re: [PATCH] KVM: arm/arm64: vgic: make vgic_io_ops static

On Thu, Nov 12, 2015 at 07:59:14PM +0800, Jisheng Zhang wrote: > vgic_io_ops is only referenced within vgic.c, so it can be declared > static. > > Signed-off-by: Jisheng Zhang Applied to queue, -Christoffer ___ kvmarm mailing list

Re: arm64 sched_clock cpu accounting

Hi Mario, On Wed, Nov 18, 2015 at 06:20:03PM -0800, Mario Smarduch wrote: > Also with tick accounting enabled, and periodic timer HZ set to 1000 no irq > time > is reported. That's with running a ping flood - 1200 int/s, not sure why > wouldn't any irq time be reported? The other two modes

Re: [PATCH v2] KVM: arm/arm64: Count guest exit due to various reasons

On Thu, Nov 26, 2015 at 10:09:43AM +, Amit Singh Tomar wrote: > From: Amit Tomar > > It would add guest exit statistics to debugfs, This can be helpful > while measuring KVM performance. > > Signed-off-by: Amit Singh Tomar > --- > Changes since

Re: [PATCH] KVM: arm/arm64: Revert to old way of checking for device mapping in stage2_flush_ptes().

On Wed, Dec 02, 2015 at 08:04:42PM +0100, Ard Biesheuvel wrote: > On 2 December 2015 at 19:50, Christoffer Dall > wrote: > > On Tue, Dec 01, 2015 at 04:03:52PM +0300, Pavel Fedin wrote: > >> This function takes stage-II physical addresses (A.K.A. IPA), on input, not >

Re: [PATCH v2] KVM: arm/arm64: Count guest exit due to various reasons

> I've applied this patch to queue with the naming changed. > Ok, Thanks! ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

Re: [PATCH] KVM: arm/arm64: Revert to old way of checking for device mapping in stage2_flush_ptes().

On 2 December 2015 at 19:50, Christoffer Dall wrote: > On Tue, Dec 01, 2015 at 04:03:52PM +0300, Pavel Fedin wrote: >> This function takes stage-II physical addresses (A.K.A. IPA), on input, not >> real physical addresses. This causes kvm_is_device_pfn() to return

Re: [PATCH] KVM: arm/arm64: Revert to old way of checking for device mapping in stage2_flush_ptes().

On Tue, Dec 01, 2015 at 04:03:52PM +0300, Pavel Fedin wrote: > This function takes stage-II physical addresses (A.K.A. IPA), on input, not > real physical addresses. This causes kvm_is_device_pfn() to return wrong > values, depending on how much guest and host memory maps match. This > results in

Re: [PATCH v4 18/21] KVM: ARM64: Add PMU overflow interrupt routing

On 02/12/15 02:40, Shannon Zhao wrote: > > > On 2015/12/2 0:57, Marc Zyngier wrote: >> On 01/12/15 16:26, Shannon Zhao wrote: >>> >>> >>> On 2015/12/1 23:41, Marc Zyngier wrote: > The reason is that when guest clear the overflow register, it will trap >> to kvm and call

RE: BUG ALERT: ARM32 KVM does not work in 4.4-rc3

Hello! > > My project involves ARM64, but from time to time i also test ARM32 > > KVM. I have discovered that it stopped working in 4.4-rc3. The same > > virtual machine works perfectly under current kvmarm/next, but gets > > stuck at random point under 4.4-rc3 from linux-stable. I'm not sure >

Re: [PATCH v2 10/21] arm64: KVM: Add patchable function selector

On Tue, Dec 01, 2015 at 06:51:00PM +, Marc Zyngier wrote: > On 01/12/15 15:39, Christoffer Dall wrote: > > On Fri, Nov 27, 2015 at 06:50:04PM +, Marc Zyngier wrote: > >> KVM so far relies on code patching, and is likely to use it more > >> in the future. The main issue is that our

Re: [PATCH v2 10/21] arm64: KVM: Add patchable function selector

On Fri, Nov 27, 2015 at 06:50:04PM +, Marc Zyngier wrote: > KVM so far relies on code patching, and is likely to use it more > in the future. The main issue is that our alternative system works > at the instruction level, while we'd like to have alternatives at > the function level. How about

Re: [PATCH v2 0/3] Introduce MSI hardware mapping for VFIO

On Tue, 2015-11-24 at 16:50 +0300, Pavel Fedin wrote: > On some architectures (e.g. ARM64) if the device is behind an IOMMU, and > is being mapped by VFIO, it is necessary to also add mappings for MSI > translation register for interrupts to work. This series implements the > necessary API to do

[PATCH v5 18/21] KVM: ARM64: Add PMU overflow interrupt routing

From: Shannon Zhao When calling perf_event_create_kernel_counter to create perf_event, assign a overflow handler. Then when perf event overflows, call kvm_vcpu_kick() to sync the interrupt. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c

[PATCH v5 17/21] KVM: ARM64: Add helper to handle PMCR register bits

From: Shannon Zhao According to ARMv8 spec, when writing 1 to PMCR.E, all counters are enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are disabled. When writing 1 to PMCR.P, reset all event counters, not including PMCCNTR, to zero. When writing 1 to

[PATCH v5 15/21] KVM: ARM64: Add reset and access handlers for PMSWINC register

From: Shannon Zhao Add access handler which emulates writing and reading PMSWINC register and add support for creating software increment event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 18 +-

[PATCH v5 16/21] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register

From: Shannon Zhao Add access handler which emulates writing and reading PMEVCNTRn and PMEVTYPERn. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 164 ++ 1 file changed, 164

[PATCH v5 21/21] KVM: ARM64: Add a new kvm ARM PMU device

From: Shannon Zhao Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement the kvm_device_ops for it. Signed-off-by: Shannon Zhao --- Documentation/virtual/kvm/devices/arm-pmu.txt | 16 + arch/arm64/include/uapi/asm/kvm.h

RE: [PATCH] KVM: arm/arm64: Revert to old way of checking for device mapping in stage2_flush_ptes().

Hello! > > diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c > > index 7dace90..51ad98f 100644 > > --- a/arch/arm/kvm/mmu.c > > +++ b/arch/arm/kvm/mmu.c > > @@ -310,7 +310,8 @@ static void stage2_flush_ptes(struct kvm *kvm, pmd_t > > *pmd, > > > > pte = pte_offset_kernel(pmd, addr);

[PATCH v5 06/21] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register

From: Shannon Zhao Add reset handler which gets host value of PMCEID0 or PMCEID1. Since write action to PMCEID0 or PMCEID1 is ignored, add a new case for this. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 29

[PATCH v5 01/21] ARM64: Move PMU register related defines to asm/pmu.h

From: Shannon Zhao To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel Signed-off-by: Shannon Zhao ---

[PATCH v5 02/21] KVM: ARM64: Define PMU data structure for each vcpu

From: Shannon Zhao Here we plan to support virtual PMU for guest by full software emulation, so define some basic structs and functions preparing for futher steps. Define struct kvm_pmc for performance monitor counter and struct kvm_pmu for performance monitor unit for

[PATCH v5 04/21] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

From: Shannon Zhao Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN except PMCR.E to zero. Add a common access handler for PMU registers which emulates writing and reading register and add emulation for PMCR.

[PATCH v5 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

From: Shannon Zhao When we use tools like perf on host, perf passes the event type and the id of this event type category to kernel, then kernel will map them to hardware event number and write this number to PMU PMEVTYPER_EL0 register. When getting the event number in

[PATCH v5 11/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register

From: Shannon Zhao Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMCNTENSET or PMCNTENCLR register. When writing to PMCNTENSET, call perf_event_enable to enable the perf event.

[PATCH v5 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register

From: Shannon Zhao Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for its reset handler. As it doesn't need to deal with the accessing action specially, it uses default case to emulate writing and reading PMSELR register. Signed-off-by: Shannon Zhao

[PATCH v5 09/21] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register

From: Shannon Zhao Since the reset value of PMXEVCNTR is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVCNTR register. When reading PMXEVCNTR, call perf_event_read_value to get the count value of the perf

[PATCH v5 10/21] KVM: ARM64: Add reset and access handlers for PMCCNTR register

From: Shannon Zhao Since the reset value of PMCCNTR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate reading and writing to PMCCNTR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 31

[PATCH v5 03/21] KVM: ARM64: Add offset defines for PMU registers

From: Shannon Zhao We are about to trap and emulate acccesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers and their AArch32 counterparts. Signed-off-by: Shannon Zhao ---

[PATCH v5 14/21] KVM: ARM64: Add reset and access handlers for PMUSERENR register

From: Shannon Zhao The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c

Re: arm64 sched_clock cpu accounting

On 12/2/2015 10:07 AM, Christoffer Dall wrote: > Hi Mario, > > On Wed, Nov 18, 2015 at 06:20:03PM -0800, Mario Smarduch wrote: >> Also with tick accounting enabled, and periodic timer HZ set to 1000 no irq >> time >> is reported. That's with running a ping flood - 1200 int/s, not sure why >>

Re: [PATCH v4 18/21] KVM: ARM64: Add PMU overflow interrupt routing

On 2015/12/2 16:45, Marc Zyngier wrote: > On 02/12/15 02:40, Shannon Zhao wrote: >> > >> > >> > On 2015/12/2 0:57, Marc Zyngier wrote: >>> >> On 01/12/15 16:26, Shannon Zhao wrote: >>> >>> >>> On 2015/12/1 23:41, Marc Zyngier wrote: >> > The reason is that when guest

Re: [PATCH v4 18/21] KVM: ARM64: Add PMU overflow interrupt routing

On 02/12/15 09:49, Shannon Zhao wrote: > > > On 2015/12/2 16:45, Marc Zyngier wrote: >> On 02/12/15 02:40, Shannon Zhao wrote: On 2015/12/2 0:57, Marc Zyngier wrote: >> On 01/12/15 16:26, Shannon Zhao wrote: On 2015/12/1 23:41, Marc Zyngier wrote:

Re: [PATCH v2 10/21] arm64: KVM: Add patchable function selector

On 02/12/15 09:27, Christoffer Dall wrote: > On Tue, Dec 01, 2015 at 06:51:00PM +, Marc Zyngier wrote: >> On 01/12/15 15:39, Christoffer Dall wrote: >>> On Fri, Nov 27, 2015 at 06:50:04PM +, Marc Zyngier wrote: KVM so far relies on code patching, and is likely to use it more in

Re: [PATCH v2 16/21] arm64: KVM: Add compatibility aliases

On Fri, Nov 27, 2015 at 06:50:10PM +, Marc Zyngier wrote: > So far, we've implemented the new world switch with a completely > different namespace, so that we could have both implementation > compiled in. > > Let's take things one step further by adding weak aliases that > have the same names

Re: [PATCH v2 10/21] arm64: KVM: Add patchable function selector

On Wed, Dec 02, 2015 at 09:47:43AM +, Marc Zyngier wrote: > On 02/12/15 09:27, Christoffer Dall wrote: > > On Tue, Dec 01, 2015 at 06:51:00PM +, Marc Zyngier wrote: > >> On 01/12/15 15:39, Christoffer Dall wrote: > >>> On Fri, Nov 27, 2015 at 06:50:04PM +, Marc Zyngier wrote: >

Re: [PATCH v2 15/21] arm64: KVM: Add panic handling

On Fri, Nov 27, 2015 at 06:50:09PM +, Marc Zyngier wrote: > Add the panic handler, together with the small bits of assembly > code to call the kernel's panic implementation. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/hyp/hyp-entry.S | 11 ++- >

Re: [PATCH v2 13/21] arm64: KVM: Implement TLB handling

On Fri, Nov 27, 2015 at 06:50:07PM +, Marc Zyngier wrote: > Implement the TLB handling as a direct translation of the assembly > code version. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/hyp/Makefile | 1 + > arch/arm64/kvm/hyp/tlb.c| 72 >

Re: [PATCH v2 14/21] arm64: KVM: HYP mode entry points

On Fri, Nov 27, 2015 at 06:50:08PM +, Marc Zyngier wrote: > Add the entry points for HYP mode (both for hypercalls and > exception handling). > > Signed-off-by: Marc Zyngier Reviewed-by: Christoffer Dall

Re: [PATCH v2 21/21] arm64: KVM: Remove weak attributes

On Fri, Nov 27, 2015 at 06:50:15PM +, Marc Zyngier wrote: > As we've now switched to the new world switch implementation, > remove the weak attributes, as nobody is supposed to override > it anymore. Why not remove the aliases and change the callers? -Christoffer > > Signed-off-by: Marc

Re: [PATCH v2 20/21] arm64: KVM: Cleanup asm-offset.c

On Fri, Nov 27, 2015 at 06:50:14PM +, Marc Zyngier wrote: > As we've now rewritten most of our code-base in C, most of the > KVM-specific code in asm-offset.c is useless. Delete-time again! > > Signed-off-by: Marc Zyngier Acked-by: Christoffer Dall

Re: [PATCH v2 19/21] arm64: KVM: Turn system register numbers to an enum

On Fri, Nov 27, 2015 at 06:50:13PM +, Marc Zyngier wrote: > Having the system register numbers as #defines has been a pain > since day one, as the ordering is pretty fragile, and moving > things around leads to renumbering and epic conflict resolutions. > > Now that we're mostly acessing the

Re: [PATCH v2 18/21] arm64: KVM: Move away from the assembly version of the world switch

On Fri, Nov 27, 2015 at 06:50:12PM +, Marc Zyngier wrote: > This is it. We remove all of the code that has now been rewritten. > > Signed-off-by: Marc Zyngier Acked-by: Christoffer Dall ___

Re: [PATCH v2 10/21] arm64: KVM: Add patchable function selector

On 02/12/15 11:53, Christoffer Dall wrote: > On Wed, Dec 02, 2015 at 09:47:43AM +, Marc Zyngier wrote: >> On 02/12/15 09:27, Christoffer Dall wrote: >>> On Tue, Dec 01, 2015 at 06:51:00PM +, Marc Zyngier wrote: On 01/12/15 15:39, Christoffer Dall wrote: > On Fri, Nov 27, 2015 at