Re: [PATCH v7 15/19] KVM: ARM64: Add access handler for PMUSERENR register

On 15/12/15 15:59, Shannon Zhao wrote: > > > On 2015/12/15 22:58, Marc Zyngier wrote: >> On 15/12/15 08:49, Shannon Zhao wrote: From: Shannon Zhao The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown. PMUSERENR_EL0 holds some bits which

Re: [PATCH v10 0/6] QEMU support for KVM Guest Debug on arm64

On 8 December 2015 at 18:32, Alex Bennée wrote: > Hi, > > Here is the latest patch set to support debugging of KVM guests on > arm64. The main changes are fixing arm32 compiles (mostly with stubs > for the upcomming arm32 debug) and the usual bunch of minor tweaks and >

[PATCH v7 10/19] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register

From: Shannon Zhao Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a handler to emulate writing PMCNTENSET or PMCNTENCLR register. When writing to PMCNTENSET, call perf_event_enable to enable the perf event.

[PATCH v7 16/19] KVM: ARM64: Add PMU overflow interrupt routing

From: Shannon Zhao When calling perf_event_create_kernel_counter to create perf_event, assign a overflow handler. Then when the perf event overflows, set the corresponding bit of guest PMOVSSET register. If this counter is enabled and its interrupt is enabled as well,

[PATCH v7 00/19] KVM: ARM64: Add guest PMU support

From: Shannon Zhao This patchset adds guest PMU support for KVM on ARM64. It takes trap-and-emulate approach. When guest wants to monitor one event, it will be trapped by KVM and KVM will call perf_event API to create a perf event and call relevant perf_event APIs to get

[PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

From: Shannon Zhao Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement the kvm_device_ops for it. Signed-off-by: Shannon Zhao --- Documentation/virtual/kvm/devices/arm-pmu.txt | 16 arch/arm64/include/uapi/asm/kvm.h

[PATCH v7 17/19] KVM: ARM64: Reset PMU state when resetting vcpu

From: Shannon Zhao When resetting vcpu, it needs to reset the PMU state to initial status. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/reset.c | 3 +++ include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c | 17 + 3 files

[PATCH v7 13/19] KVM: ARM64: Add access handler for PMSWINC register

From: Shannon Zhao Add access handler which emulates writing and reading PMSWINC register and add support for creating software increment event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 14 +-

[PATCH v7 01/19] ARM64: Move PMU register related defines to asm/pmu.h

From: Shannon Zhao To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel Signed-off-by: Shannon Zhao ---

Re: ARM64/KVM: Bad page state in process iperf

On 15/12/15 03:46, Bhushan Bharat wrote: > > Hi All, > > I am running "iperf" in KVM guest on ARM64 machine and observing below crash. > > = > $iperf -c 3.3.3.3 -P 4 -t 0 -i 5 -w 90k > > Client connecting

[PATCH v7 18/19] KVM: ARM64: Free perf event of PMU when destroying vcpu

From: Shannon Zhao When KVM frees VCPU, it needs to free the perf_event of PMU. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c| 1 + include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c| 21 + 3 files changed, 24

RE: ARM64/KVM: Bad page state in process iperf

> -Original Message- > From: Christoffer Dall [mailto:christoffer.d...@linaro.org] > Sent: Tuesday, December 15, 2015 2:59 PM > To: Bhushan Bharat-R65777 > Cc: kvmarm@lists.cs.columbia.edu; k...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org;

[PATCH v7 11/19] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register

From: Shannon Zhao Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a handler to emulate writing PMINTENSET or PMINTENCLR register. Signed-off-by: Shannon Zhao ---

[PATCH v7 09/19] KVM: ARM64: Add access handler for event counter register

From: Shannon Zhao These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which is mapped to PMEVCNTRn. The access handler translates all aarch32 register offsets to aarch64 ones and uses vcpu_sys_reg() to access their values to avoid taking care of big

[PATCH v7 04/19] KVM: ARM64: Add access handler for PMCR register

From: Shannon Zhao Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN except PMCR.E which is zero. Add an access handler for PMCR. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 39

[PATCH v7 15/19] KVM: ARM64: Add access handler for PMUSERENR register

From: Shannon Zhao The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown. PMUSERENR_EL0 holds some bits which decide whether PMU registers can be accessed from EL0. Add some check helpers to handle the access from EL0. Signed-off-by: Shannon Zhao

[PATCH v7 07/19] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

From: Shannon Zhao When we use tools like perf on host, perf passes the event type and the id of this event type category to kernel, then kernel will map them to hardware event number and write this number to PMU PMEVTYPER_EL0 register. When getting the event number in

[PATCH v7 02/19] KVM: ARM64: Define PMU data structure for each vcpu

From: Shannon Zhao Here we plan to support virtual PMU for guest by full software emulation, so define some basic structs and functions preparing for futher steps. Define struct kvm_pmc for performance monitor counter and struct kvm_pmu for performance monitor unit for

[PATCH v7 05/19] KVM: ARM64: Add access handler for PMSELR register

From: Shannon Zhao Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for its reset handler. When reading PMSELR, return the PMSELR.SEL field to guest. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 17

[PATCH v7 14/19] KVM: ARM64: Add helper to handle PMCR register bits

From: Shannon Zhao According to ARMv8 spec, when writing 1 to PMCR.E, all counters are enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are disabled. When writing 1 to PMCR.P, reset all event counters, not including PMCCNTR, to zero. When writing 1 to

[PATCH v7 08/19] KVM: ARM64: Add access handler for event typer register

From: Shannon Zhao These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER which is mapped to PMEVTYPERn or PMCCFILTR. The access handler translates all aarch32 register offsets to aarch64 ones and uses vcpu_sys_reg() to access their values to avoid taking

[PATCH v7 12/19] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register

From: Shannon Zhao Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use reset_unknown for its reset handler. Add a handler to emulate writing PMOVSSET or PMOVSCLR register. When writing non-zero value to PMOVSSET, pend PMU interrupt. Signed-off-by: Shannon

RE: ARM64/KVM: Bad page state in process iperf

Hi Mark, > -Original Message- > From: Marc Zyngier [mailto:marc.zyng...@arm.com] > Sent: Tuesday, December 15, 2015 3:05 PM > To: Bhushan Bharat-R65777 ; > kvmarm@lists.cs.columbia.edu; k...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org;

Re: ARM64/KVM: Bad page state in process iperf

On 15/12/15 09:53, Bhushan Bharat wrote: > Hi Mark, > >> -Original Message- >> From: Marc Zyngier [mailto:marc.zyng...@arm.com] >> Sent: Tuesday, December 15, 2015 3:05 PM >> To: Bhushan Bharat-R65777 ; >> kvmarm@lists.cs.columbia.edu; k...@vger.kernel.org;

RE: ARM64/KVM: Bad page state in process iperf

> -Original Message- > From: Marc Zyngier [mailto:marc.zyng...@arm.com] > Sent: Tuesday, December 15, 2015 3:50 PM > To: Bhushan Bharat-R65777 ; > kvmarm@lists.cs.columbia.edu; k...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org;

RE: ARM64/KVM: Bad page state in process iperf

> -Original Message- > From: Marc Zyngier [mailto:marc.zyng...@arm.com] > Sent: Tuesday, December 15, 2015 4:49 PM > To: Bhushan Bharat-R65777 ; > kvmarm@lists.cs.columbia.edu; k...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org;

Re: ARM64/KVM: Bad page state in process iperf

On 15/12/15 10:57, Bhushan Bharat wrote: > > >> -Original Message- >> From: Marc Zyngier [mailto:marc.zyng...@arm.com] >> Sent: Tuesday, December 15, 2015 3:50 PM >> To: Bhushan Bharat-R65777 ; >> kvmarm@lists.cs.columbia.edu; k...@vger.kernel.org;

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On Tue, Dec 15, 2015 at 03:59:31PM +, Marc Zyngier wrote: > On 15/12/15 15:50, Shannon Zhao wrote: > > > > > > On 2015/12/15 23:33, Marc Zyngier wrote: > >> On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > Add a new kvm device type

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On 2015/12/15 23:33, Marc Zyngier wrote: On 15/12/15 08:49, Shannon Zhao wrote: >From: Shannon Zhao > >Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement >the kvm_device_ops for it. > >Signed-off-by: Shannon Zhao >--- >

Re: [PATCH v7 15/19] KVM: ARM64: Add access handler for PMUSERENR register

On 2015/12/15 22:58, Marc Zyngier wrote: On 15/12/15 08:49, Shannon Zhao wrote: >From: Shannon Zhao > >The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown. > >PMUSERENR_EL0 holds some bits which decide whether PMU registers can be >accessed from EL0. Add

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On 15/12/15 15:50, Shannon Zhao wrote: > > > On 2015/12/15 23:33, Marc Zyngier wrote: >> On 15/12/15 08:49, Shannon Zhao wrote: From: Shannon Zhao Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement the kvm_device_ops for it.

Re: [PATCH v7 11/19] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use > reset_unknown for its reset handler. Add a handler to emulate writing > PMINTENSET or PMINTENCLR register. > > Signed-off-by: Shannon

Re: [PATCH v7 10/19] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use > reset_unknown for its reset handler. Add a handler to emulate writing > PMCNTENSET or PMCNTENCLR register. > > When writing to

Re: [PATCH v7 08/19] KVM: ARM64: Add access handler for event typer register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER > which is mapped to PMEVTYPERn or PMCCFILTR. > > The access handler translates all aarch32 register offsets to aarch64 > ones and uses

Re: [PATCH v7 12/19] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use > reset_unknown for its reset handler. Add a handler to emulate writing > PMOVSSET or PMOVSCLR register. > > When writing non-zero value to

Re: [PATCH v7 06/19] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > Add access handler which gets host value of PMCEID0 or PMCEID1 when > guest access these registers. Writing action to PMCEID0 or PMCEID1 is > ignored. > > Signed-off-by: Shannon Zhao

Re: [PATCH v7 13/19] KVM: ARM64: Add access handler for PMSWINC register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > Add access handler which emulates writing and reading PMSWINC > register and add support for creating software increment event. > > Signed-off-by: Shannon Zhao > --- >

Re: [PATCH v7 15/19] KVM: ARM64: Add access handler for PMUSERENR register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown. > > PMUSERENR_EL0 holds some bits which decide whether PMU registers can be > accessed from EL0. Add some check helpers to handle the access

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement > the kvm_device_ops for it. > > Signed-off-by: Shannon Zhao > --- >

Re: [PATCH v7 00/19] KVM: ARM64: Add guest PMU support

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > This patchset adds guest PMU support for KVM on ARM64. It takes > trap-and-emulate approach. When guest wants to monitor one event, it > will be trapped by KVM and KVM will call perf_event API to create a

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On 2015/12/16 4:47, Christoffer Dall wrote: > On Tue, Dec 15, 2015 at 03:59:31PM +, Marc Zyngier wrote: >> > On 15/12/15 15:50, Shannon Zhao wrote: >>> > > >>> > > >>> > > On 2015/12/15 23:33, Marc Zyngier wrote: > >> On 15/12/15 08:49, Shannon Zhao wrote: >> > From: Shannon