[PATCH 13/45] KVM: arm/arm64: vgic-new: Export register access interface

Userland can access the emulated GIC to save and restore its state for initialization or migration purposes. The kvm_io_bus API requires an absolute gpa, which does not fit the KVM_DEV_ARM_VGIC_GRP_DIST_REGS user API, that only provides relative offsets. So we explicitly iterate our register list

[PATCH 00/45] KVM: arm/arm64: Rework virtual GIC emulation

Hi, this is a rework of the new VGIC series. Many thanks to all reviewers, especially Christoffer. Major changes include a dependency on a new, separate arch_timer rework series [1], a total rework of the MMIO dispatching, which now uses much less kvm_io_bus devices, the proper handling of

[PATCH 35/45] KVM: arm/arm64: vgic-new: Add userland access to VGIC dist registers

Signed-off-by: Andre Przywara --- virt/kvm/arm/vgic/vgic_kvm_device.c | 50 - 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/virt/kvm/arm/vgic/vgic_kvm_device.c b/virt/kvm/arm/vgic/vgic_kvm_device.c index

[PATCH 09/45] KVM: arm/arm64: vgic-new: Add GICv2 world switch backend

From: Marc Zyngier Processing maintenance interrupts and accessing the list registers are dependent on the host's GIC version. Introduce vgic-v2.c to contain GICv2 specific functions. Implement the GICv2 specific code for syncing the emulation state into the VGIC registers.

[PATCH 18/45] KVM: arm/arm64: vgic-new: Add ACTIVE registers handlers

Signed-off-by: Andre Przywara Changelog RFC..v1: - handling queueing in write handler - remove IRQ lock from read handler --- virt/kvm/arm/vgic/vgic_mmio.c | 143 +- 1 file changed, 141 insertions(+), 2 deletions(-) diff --git

[PATCH 06/45] KVM: arm/arm64: vgic-new: Implement virtual IRQ injection

From: Christoffer Dall Provide a vgic_queue_irq() function which decides whether a given IRQ needs to be queued to a VCPU's ap_list. This should be called whenever an IRQ becomes pending or enabled, either as a result of userspace injection, from in-kernel emulated

[PATCH 30/45] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_NR_IRQS

From: Eric Auger This patch implements the KVM_DEV_ARM_VGIC_GRP_NR_IRQS group. This modality is supported by both VGIC V2 and V3 KVM device as will be other groups, hence the introduction of common helpers. Signed-off-by: Eric Auger Signed-off-by:

[PATCH 34/45] KVM: arm/arm64: vgic-new: vgic_kvm_device: implement kvm_vgic_addr

From: Eric Auger kvm_vgic_addr is used by the userspace to set the base address of the following register regions, as seen by the guest: - distributor(v2 and v3), - re-distributors (v3), - CPU interface (v2). Signed-off-by: Eric Auger

[PATCH 16/45] KVM: arm/arm64: vgic-new: Add PENDING registers handlers

Signed-off-by: Andre Przywara Changelog RFC..v1: - remove IRQ lock from read handler - remove TODO from clear pending handler --- virt/kvm/arm/vgic/vgic_mmio.c | 84 +-- 1 file changed, 82 insertions(+), 2 deletions(-) diff --git

[PATCH 10/45] KVM: arm/arm64: vgic-new: Add GICv3 world switch backend

From: Marc Zyngier As the GICv3 virtual interface registers differ from their GICv2 siblings, we need different handlers for processing maintenance interrupts and reading/writing to the LRs. Also as we store an IRQ's affinity directly as a MPIDR, we need a separate

[PATCH 07/45] KVM: arm/arm64: vgic-new: Add IRQ sorting

From: Christoffer Dall Adds the sorting function to cover the case where you have more IRQs to consider than you have LRs. We now consider priorities. Signed-off-by: Christoffer Dall Signed-off-by: Andre Przywara

[PATCH 17/45] KVM: arm/arm64: vgic-new: Add PRIORITY registers handlers

Signed-off-by: Andre Przywara --- virt/kvm/arm/vgic/vgic_mmio.c | 46 ++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/virt/kvm/arm/vgic/vgic_mmio.c b/virt/kvm/arm/vgic/vgic_mmio.c index 7010b15..8e1e051 100644 ---

[PATCH 08/45] KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework

From: Marc Zyngier Implement the framework for syncing IRQs between our emulation and the list registers, which represent the guest's view of IRQs. This is done in kvm_vgic_flush_hwstate and kvm_vgic_sync_hwstate, which gets called on guest entry and exit. The code talking

[PATCH 28/45] KVM: arm/arm64: vgic-new: Add GICv3 SGI system register trap handler

In contrast to GICv2 SGIs in a GICv3 implementation are not triggered by a MMIO write, but with a system register write. KVM knows about that register already, we just need to implement the handler and wire it up to the core KVM/ARM code. Signed-off-by: Andre Przywara

[PATCH 21/45] KVM: arm/arm64: vgic-new: Add SGIR register handler

Signed-off-by: Andre Przywara Changelog RFC..v1: - silently return on illegal TargetListFilter value (=3) --- virt/kvm/arm/vgic/vgic_mmio.c | 46 ++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git

[PATCH 23/45] KVM: arm/arm64: vgic-new: Add GICv3 MMIO handling framework

Describe the GICv3 distributor and redistributor registers in our structure. This adds a special macro to deal with the split of SGI/PPI in the redistributor and SPIs in the distributor, which allows us to reuse the existing GICv2 handlers for those registers which are compatible. Also we register

[PATCH 15/45] KVM: arm/arm64: vgic-new: Add ENABLE registers handlers

Signed-off-by: Andre Przywara Changelog RFC..v1: - use lower bits of address to determine IRQ number - remove TODO, confirmed to be fine --- virt/kvm/arm/vgic/vgic_mmio.c | 80 +-- 1 file changed, 78 insertions(+), 2 deletions(-)

[PATCH 33/45] KVM: arm/arm64: vgic-new: vgic_kvm_device: access to VGIC registers

From: Eric Auger This patch implements the switches for KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS API which allows the userspace to access VGIC registers. At that stage the interfaces with the MMIO API are not implemented: - vgic_attr_regs_access -

[PATCH 38/45] KVM: arm/arm64: vgic-new: vgic_init: implement kvm_vgic_hyp_init

From: Eric Auger Implements kvm_vgic_hyp_init and vgic_probe function. The vgic_global struct is enriched with new fields populated by those functions. Signed-off-by: Eric Auger Signed-off-by: Andre Przywara ---

[PATCH 40/45] KVM: arm/arm64: vgic-new: vgic_init: implement vgic_init

From: Eric Auger This patch allocates and initializes the data structures used to model the vgic distributor and virtual cpu interfaces. At that stage the number of IRQs and number of virtual CPUs is frozen. The following early_init functions are kept since they are

[PATCH 45/45] KVM: arm/arm64: vgic-new: enable build

Now that the new VGIC implementation has reached feature parity with the old one, add the new files to the build system and add a Kconfig option to switch between the two versions. We set the default to the new version to get maximum test coverage, in case people experience problems they can

[PATCH 41/45] KVM: arm/arm64: vgic-new: vgic_init: implement map_resources

From: Eric Auger map_resources is the last initialization step. It is executed on 1st VCPU run. At that stage the code checks the userspace has provided the base addresses for the relevant VGIC regions, which depend on the type of VGIC that is exposed to the guest. The

[PATCH 43/45] KVM: arm/arm64: vgic-new: Wire up irqfd injection

Connect to the new VGIC to the irqfd framework, so that we can inject IRQs. GSI routing and MSI routing is not yet implemented. Signed-off-by: Andre Przywara --- virt/kvm/arm/vgic/vgic_irqfd.c | 51 ++ 1 file changed, 51

[PATCH 44/45] KVM: arm/arm64: vgic-new: implement mapped IRQ handling

We now store the mapped hardware IRQ number in our struct, so we don't need the irq_phys_map for the new VGIC. Implement the hardware IRQ mapping on top of the reworked arch timer interface. Signed-off-by: Andre Przywara Changelog RFC..v1: - adapt to new arch_timer

[PATCH 42/45] KVM: arm/arm64: vgic-new: Add vgic_v2/v3_enable

From: Eric Auger Enable the VGIC operation by properly initialising the registers in the hypervisor GIC interface. Signed-off-by: Eric Auger Signed-off-by: Andre Przywara --- virt/kvm/arm/vgic/vgic-v2.c | 11 ++-

[PATCH 25/45] KVM: arm/arm64: vgic-new: Add GICv3 redistributor IIDR, TYPER handlers

The redistributor TYPER tells the OS about the associated MPIDR, also the LAST bit is crucial to determine the number of redistributors. Signed-off-by: Andre Przywara --- virt/kvm/arm/vgic/vgic_mmio.c | 50 +-- 1 file changed, 48

[PATCH 39/45] KVM: arm/arm64: vgic-new: vgic_init: implement vgic_create

From: Eric Auger This patch implements the vgic_creation function which is called on CREATE_IRQCHIP VM IOCTL (v2 only) or KVM_CREATE_DEVICE Signed-off-by: Eric Auger Signed-off-by: Andre Przywara ---

[PATCH 24/45] KVM: arm/arm64: vgic-new: Add GICv3 CTLR, IIDR, TYPER handlers

As in the GICv2 emulation we handle those three registers in one function. Signed-off-by: Andre Przywara Changelog RFC..v1: - kick VCPUs if distributor gets enabled --- virt/kvm/arm/vgic/vgic.h | 2 ++ virt/kvm/arm/vgic/vgic_mmio.c | 56

[PATCH 37/45] KVM: arm/arm64: vgic-new: Add userland GIC CPU interface access

Signed-off-by: Andre Przywara --- virt/kvm/arm/vgic/vgic_kvm_device.c | 72 - 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/virt/kvm/arm/vgic/vgic_kvm_device.c b/virt/kvm/arm/vgic/vgic_kvm_device.c index

[PATCH 29/45] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM device ops registration

From: Eric Auger This patch introduces the skeleton for the KVM device operations associated to KVM_DEV_TYPE_ARM_VGIC_V2 and KVM_DEV_TYPE_ARM_VGIC_V3. At that stage kvm_vgic_create is stubbed. Signed-off-by: Eric Auger Signed-off-by: Andre

[PATCH 32/45] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_ADDR

From: Eric Auger This patch implements the KVM_DEV_ARM_VGIC_GRP_ADDR group which enables to set the base address of GIC regions as seen by the guest. The kvm_vgic_addr function whci eventually assigns the chosen address to the internal structure still is stubbed.

[PATCH 36/45] KVM: arm/arm64: vgic-new: Add GICH_VMCR accessors

Signed-off-by: Andre Przywara --- include/kvm/vgic/vgic.h | 7 +++ virt/kvm/arm/vgic/vgic-v2.c | 29 + virt/kvm/arm/vgic/vgic-v3.c | 22 ++ virt/kvm/arm/vgic/vgic.c| 16 virt/kvm/arm/vgic/vgic.h

[PATCH 26/45] KVM: arm/arm64: vgic-new: Add GICv3 IDREGS register handler

Signed-off-by: Andre Przywara --- virt/kvm/arm/vgic/vgic_mmio.c | 21 +++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/virt/kvm/arm/vgic/vgic_mmio.c b/virt/kvm/arm/vgic/vgic_mmio.c index 7d275a7..dafa235 100644 ---

[PATCH 31/45] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_CTRL

From: Eric Auger This patch implements the KVM_DEV_ARM_VGIC_GRP_CTRL group API featuring KVM_DEV_ARM_VGIC_CTRL_INIT attribute. The vgic_init function is not yet implemented though. Signed-off-by: Eric Auger Signed-off-by: Andre Przywara

[PATCH 22/45] KVM: arm/arm64: vgic-new: Add SGIPENDR register handlers

Changelog RFC..v1: - remove IRQ lock from read handler - update pending bit on setting the first / clearing the last bit - queue virtual IRQ if necessary --- virt/kvm/arm/vgic/vgic_mmio.c | 64 +-- 1 file changed, 62 insertions(+), 2 deletions(-) diff

[PATCH 03/45] KVM: arm/arm64: pmu: abstract access to number of SPIs

Currently the PMU uses a member of the struct vgic_dist directly, which not only breaks abstraction, but will fail with the new VGIC. Abstract this access in the VGIC header file. Signed-off-by: Andre Przywara --- include/kvm/arm_vgic.h | 2 ++ virt/kvm/arm/pmu.c | 2

[PATCH 04/45] KVM: arm/arm64: vgic-new: Add data structure definitions

From: Christoffer Dall Add a new header file for the new and improved GIC implementation. The big change is that we now have a struct vgic_irq per IRQ instead of spreading all the information over various bitmaps. We include this new header conditionally from within

[PATCH 02/45] KVM: arm/arm64: Fix MMIO emulation data handling

From: Christoffer Dall When the kernel was handling a guest MMIO read access internally, we need to copy the emulation result into the run->mmio structure in order for the kvm_handle_mmio_return() function to pick it up and inject the result back into the

[PATCH 12/45] KVM: arm/arm64: vgic-new: Add MMIO handling framework

We register a kvm_io_bus device for the distributor and dispatch the calls to the actual register handler at runtime. Ideally we would register each register group directly with the kvm_io_bus framework, but currently we run into the limit of 1000 devices pretty quickly (with GICv3), so we use

[PATCH 11/45] KVM: arm/arm64: vgic-new: Implement kvm_vgic_vcpu_pending_irq

From: Eric Auger Tell KVM whether a particular VCPU has an IRQ that needs handling in the guest. This is used to decide whether a VCPU is runnable. Signed-off-by: Eric Auger Signed-off-by: Andre Przywara Changelog RFC..v1:

[PATCH 19/45] KVM: arm/arm64: vgic-new: Add CONFIG registers handlers

Signed-off-by: Andre Przywara --- virt/kvm/arm/vgic/vgic_mmio.c | 62 ++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/virt/kvm/arm/vgic/vgic_mmio.c b/virt/kvm/arm/vgic/vgic_mmio.c index 3c3dbce..a8a96c8 100644 ---

[PATCH 20/45] KVM: arm/arm64: vgic-new: Add TARGET registers handlers

Signed-off-by: Andre Przywara Changelog RFC..v1: - remove runtime VCPU determination from this v2-only register - fold in implementation of vgic_v2_irq_change_affinity() - replace ffs() with __ffs() --- virt/kvm/arm/vgic/vgic_mmio.c | 45

[PATCH 14/45] KVM: arm/arm64: vgic-new: Add CTLR, TYPER and IIDR handlers

Signed-off-by: Andre Przywara Changelog RFC..v1: - kick VCPUs is the distributor gets enabled - improve comment --- virt/kvm/arm/vgic/vgic.h | 3 +++ virt/kvm/arm/vgic/vgic_mmio.c | 50 ++- 2 files changed, 52 insertions(+),

[PATCH 01/45] KVM: arm/arm64: Get rid of vgic_cpu->nr_lr

From: Christoffer Dall The number of list registers is a property of the underlying system, not of emulated VGIC CPU interface. As we are about to move this variable to global state in the new vgic for clarity, move it from the legacy implementation as well to make

Re: [PATCH v2 04/17] arm64: Introduce pmd_thp_or_huge

On Thu, Apr 14, 2016 at 02:20:52PM +0100, Suzuki K Poulose wrote: > Add a helper to determine if a given pmd represents a huge page > either by hugetlb or thp, as we have for arm. This will be used > by KVM MMU code. > > Suggested-by: Mark Rutland > Cc: Catalin Marinas

Re: [PATCH v2 01/17] arm64: Reuse TCR field definitions for EL1 and EL2

On Thu, Apr 14, 2016 at 02:20:49PM +0100, Suzuki K Poulose wrote: > TCR_EL1, TCR_EL2 and VTCR_EL2, all share some field positions > (TG0, ORGN0, IRGN0 and SH0) and their corresponding value definitions. > > This patch makes the TCR_EL1 definitions reusable and uses them for TCR_EL2 > and VTCR_EL2

[PATCH 6/7] KVM: arm/arm64: remove irq_phys_map from the arch timer

Now that the interface between the arch timer and the VGIC does not require passing the irq_phys_map entry pointer anymore, let's remove it from the virtual arch timer and use the virtual IRQ number instead directly. The remaining pointer returned by kvm_vgic_map_phys_irq() will be removed in the

[PATCH 2/7] KVM: arm/arm64: directly pass virtual IRQ number on injecting mapped IRQ

When we want to inject a hardware mapped IRQ into a guest, we actually only need the virtual IRQ number from the irq_phys_map. So let's pass this number directly from the arch timer to the VGIC to avoid using the map as a parameter. Signed-off-by: Andre Przywara ---

[PATCH 7/7] KVM: arm/arm64: remove irq_phys_map pointer from kvm_vgic_map_phys_irq()

Now that the virtual arch timer does not care about the irq_phys_map anymore, let's rework kvm_vgic_map_phys_irq() to return an error value instead. Any reference to thap mapping can later be done by passing the correct combination of VCPU and virtual IRQ number. This makes the irq_phys_map

[PATCH 1/7] KVM: arm/arm64: remove unneeded map parameter for vgic_update_irq_pending()

We actually don't use the irq_phys_map parameter in vgic_update_irq_pending(), so let's just remove it. Signed-off-by: Andre Przywara --- virt/kvm/arm/vgic.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/virt/kvm/arm/vgic.c

[PATCH 4/7] KVM: arm/arm64: directly pass virtual IRQ number on kvm_vgic_unmap_phys_irq()

kvm_vgic_unmap_phys_irq() only needs the virtual IRQ number, so let's just pass that between the arch timer and the VGIC to get rid of the irq_phys_map pointer. Signed-off-by: Andre Przywara --- include/kvm/arm_vgic.h| 2 +- virt/kvm/arm/arch_timer.c | 2 +-

[PATCH 3/7] KVM: arm/arm64: directly pass virtual IRQ number on kvm_vgic_map_is_active()

For getting the active state of a mapped IRQ, we actually only need the virtual IRQ number, not the pointer to the mapping entry. Pass the virtual IRQ number from the arch timer to the VGIC directly. Signed-off-by: Andre Przywara --- include/kvm/arm_vgic.h| 2 +-

Re: [PATCH v7 1/6] KVM: arm/arm64: Add VGICv3 save/restore API documentation

On 7 December 2015 at 12:29, Pavel Fedin wrote: > From: Christoffer Dall > > Factor out the GICv3-specific documentation into a separate > documentation file. Add description for how to access distributor, > redistributor, and CPU interface