On Mon, May 09, 2016 at 05:50:56PM +0100, Catalin Marinas wrote:
> On Mon, May 09, 2016 at 05:33:10PM +0200, Christoffer Dall wrote:
> > On Wed, Apr 13, 2016 at 05:57:37PM +0100, Catalin Marinas wrote:
> > > The ARMv8.1 architecture extensions introduce support for hardware
> > > updates of the acc
On 5/9/16, 10:18 AM, "kvmarm-boun...@lists.cs.columbia.edu on behalf of Marc
Zyngier" wrote:
>On 06/05/16 11:45, Andre Przywara wrote:
>> Create a new file called vgic-mmio-v3.c and describe the GICv3
>> distributor and redistributor registers there.
>> This adds a special macro to deal wit
On 06/05/16 11:46, Andre Przywara wrote:
> Using the VMCR accessors we provide access to GIC CPU interface state
> to userland by wiring it up to the existing userland interface.
> [Marc: move and make VMCR accessors static, streamline MMIO handlers]
>
> Signed-off-by: Andre Przywara
> Signed-off
On 5/9/16, 8:47 AM, "Marc Zyngier" wrote:
>On 05/05/16 19:08, Chalamarla, Tirumalesh wrote:
>>
>>
>>
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>>
>> On 3/25/16, 7:14 PM, "kvmarm-boun...@lists.cs.columbia.edu on behalf of
>> Andre Przywara" > andre.przyw...@arm.com> wrote:
>>
>>> The ARM GICv3 ITS controller requires a sepa
On 06/05/16 11:45, Andre Przywara wrote:
> Create a new file called vgic-mmio-v3.c and describe the GICv3
> distributor and redistributor registers there.
> This adds a special macro to deal with the split of SGI/PPI in the
> redistributor and SPIs in the distributor, which allows us to reuse
> the
On 09/05/16 17:53, Chalamarla, Tirumalesh wrote:
>
>
>
>
>
> On 5/9/16, 8:47 AM, "Marc Zyngier" wrote:
>
>> On 05/05/16 19:08, Chalamarla, Tirumalesh wrote:
>>>
>>>
>>>
>>>
>>>
>>> On 3/25/16, 7:14 PM, "kvmarm-boun...@lists.cs.columbia.edu on behalf of
>>> Andre Przywara" >> andre.przyw...@
On Mon, May 09, 2016 at 05:33:10PM +0200, Christoffer Dall wrote:
> On Wed, Apr 13, 2016 at 05:57:37PM +0100, Catalin Marinas wrote:
> > The ARMv8.1 architecture extensions introduce support for hardware
> > updates of the access and dirty information in page table entries. With
> > VTCR_EL2.HA ena
On 05/05/16 19:08, Chalamarla, Tirumalesh wrote:
>
>
>
>
>
> On 3/25/16, 7:14 PM, "kvmarm-boun...@lists.cs.columbia.edu on behalf of Andre
> Przywara" andre.przyw...@arm.com> wrote:
>
>> The ARM GICv3 ITS controller requires a separate register frame to
>> cover ITS specific registers. Add
On Wed, Apr 13, 2016 at 05:57:37PM +0100, Catalin Marinas wrote:
> The ARMv8.1 architecture extensions introduce support for hardware
> updates of the access and dirty information in page table entries. With
> VTCR_EL2.HA enabled (bit 21), when the CPU accesses an IPA with the
> PTE_AF bit cleared
