Allow user to select who sends ipis and with which irq,
rather than just always sending irq=0 from cpu0.
Signed-off-by: Andrew Jones
---
v6:
- make sender/irq names more future-proof [drew]
- sanity check inputs [drew]
- introduce check_sender/irq and bad_sender/irq to more
cleanly do chec
Add some gicv2 support. This just adds init and enable
functions, allowing unit tests to start messing with it.
Reviewed-by: Andre Przywara
Signed-off-by: Andrew Jones
---
v6: added comments (register offset headers) [Alex]
v5: share/use only the modern register names [Andre]
v4:
- only take d
Reviewed-by: Alex Bennée
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/arm/asm/processor.h | 10 ++
lib/arm64/asm/processor.h | 10 ++
2 files changed, 20 insertions(+)
diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h
index bc46d1f980ee..959ecda5dc
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
v6: move the spurious check to its own check_ function [drew]
v5: use modern registers [Andre]
v4: properly mask irqnr in ipi_handler
v2: add more details in the output if a test fails,
report spurious interrupts if we get them
---
arm/
Signed-off-by: Andrew Jones
---
v6: move most gicv2/gicv3 wrappers to common code [Alex]
v5:
- fix copy+paste error in gicv3_write_eoir [drew]
- use modern register names [Andre]
v4:
- heavily comment gicv3_ipi_send_tlist() [Eric]
- changes needed for gicv2 iar/irqstat fix to other patch
v2:
Allow a thread to wait some specified amount of time. Can
specify in cycles, usecs, and msecs.
Reviewed-by: Alex Bennée
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/arm/asm/processor.h | 19 +++
lib/arm/processor.c | 15 +++
lib/arm64/asm/proc
Reviewed-by: Alex Bennée
Signed-off-by: Andrew Jones
---
v6:
- added comments [Alex]
- added stride parameter to gicv3_set_redist_base [Andre]
- redist-wait s/rwp/uwp/ and comment [Andre]
- removed unnecessary wait-for-rwps [Andre]
v5: use modern register names [Andre]
v4:
- only take defin
From: Peter Xu
These macros will be useful to do page alignment checks.
Reviewed-by: Andre Przywara
Signed-off-by: Peter Xu
[drew: also added SZ_64K and changed to shifts]
Signed-off-by: Andrew Jones
---
v6: change to shifts [Alex]
---
lib/libcflat.h | 6 ++
1 file changed, 6 insertions
mrs is always 64bit, so we should always use a 64bit register.
Sometimes we'll only want to return the lower 32, but not for
MPIDR, as that does define fields in the upper 32.
Reviewed-by: Alex Bennée
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
v5: switch arm32's get_mpidr to 'unsi
Make implementation equivalent to Linux's include/linux/stringify.h
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/libcflat.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/libcflat.h b/lib/libcflat.h
index 72b1bf9668ef..82005f5d014f 100644
--- a/lib/li
By adding support for launching with gicv3 we can break the 8 vcpu
limit. This patch adds support to smp code and also selects the
vgic model corresponding to the host. The vgic model may also be
manually selected by adding e.g. -machine gic-version=3 to
extra_params.
Reviewed-by: Alex Bennée
Rev
v6:
- rebased to latest master
- several other changes thanks to Andre and Alex, changes in
individual patch change logs
- some code cleanups
v5:
- fix arm32/gicv3 compile [drew]
- use modern register names [Andre]
- one Andre r-b
v4:
- Eric's r-b's
- Andre's suggestion to only take de
Hi Drew, Wei,
On 11/14/2016 05:05 AM, Andrew Jones wrote:
> On Fri, Nov 11, 2016 at 01:55:49PM -0600, Wei Huang wrote:
>>
>>
>> On 11/11/2016 01:43 AM, Andrew Jones wrote:
>>> On Tue, Nov 08, 2016 at 12:17:14PM -0600, Wei Huang wrote:
From: Christopher Covington
Ensure that reads o
On Fri, Nov 11, 2016 at 04:31:36PM +, Andre Przywara wrote:
> Hi,
>
> On 10/11/16 17:21, Andrew Jones wrote:
> > Signed-off-by: Andrew Jones
> >
> > ---
> > v5: use modern register names [Andre]
> > v4:
> > - only take defines from kernel we need now [Andre]
> > - simplify enable by not ca
On Fri, Nov 11, 2016 at 02:13:31PM +0100, Andrew Jones wrote:
> On Fri, Nov 11, 2016 at 11:13:46AM +, Andre Przywara wrote:
> > Hi,
> >
> > more a comment loosely related to this patch ...
> >
> > > diff --git a/arm/unittests.cfg b/arm/unittests.cfg
> > > index 3f6fa45c587e..68bf5cd6008f 1006
Hi Suzuki,
On Tue, Nov 08, 2016 at 01:56:21PM +, Suzuki K. Poulose wrote:
> diff --git a/arch/arm64/include/asm/cpucaps.h
> b/arch/arm64/include/asm/cpucaps.h
> index 87b4465..4174f09 100644
> --- a/arch/arm64/include/asm/cpucaps.h
> +++ b/arch/arm64/include/asm/cpucaps.h
> @@ -34,7 +34,8 @@
On Fri, Nov 11, 2016 at 01:41:37PM +, Marc Zyngier wrote:
> On 08/11/16 13:56, Suzuki K Poulose wrote:
> > This series adds supports to the kernel and KVM hyp to handle
> > systems without FP/ASIMD properly. At the moment the kernel
> > doesn't check if the FP unit is available before accessing
On 02/11/16 11:55, Vladimir Murzin wrote:
> This patch allows to build and use vGICv3 ITS in 32-bit mode.
>
> Signed-off-by: Vladimir Murzin
> Reviewed-by: Andre Przywara
> ---
> Documentation/virtual/kvm/api.txt |2 +-
> arch/arm/include/uapi/asm/kvm.h |2 ++
> arch/arm/kvm/Kconf
On 02/11/16 11:55, Vladimir Murzin wrote:
> Evaluate GITS_BASER_ENTRY_SIZE once as an int data (GITS_BASER's
> Entry Size is 5-bit wide only), so when used as divider no reference
> to __aeabi_uldivmod is generated when build for AArch32.
>
> Use unsigned long long for GITS_BASER_PAGE_SIZE_* since
On Fri, Nov 11, 2016 at 01:55:49PM -0600, Wei Huang wrote:
>
>
> On 11/11/2016 01:43 AM, Andrew Jones wrote:
> > On Tue, Nov 08, 2016 at 12:17:14PM -0600, Wei Huang wrote:
> >> From: Christopher Covington
> >>
> >> Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
> >> even for
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