Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

Hi Shanker, [auto build test ERROR on next-20161224] [also build test ERROR on v4.10-rc1] [cannot apply to arm64/for-next/core v4.9-rc8 v4.9-rc7 v4.9-rc6] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url:

Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

On 12/29/2016 04:43 PM, Christopher Covington wrote: +config QCOM_FALKOR_E1003_RESERVED_ASID + int + default 1 + depends on QCOM_FALKOR_ERRATUM_1003 Also, since this can't be changed via the menu, why bother putting it in? -- Qualcomm Datacenter Technologies, Inc. as an

Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

On 12/29/2016 04:43 PM, Christopher Covington wrote: -| Implementor| Component | Erratum ID | Kconfig | -++-+-+-+ -| ARM| Cortex-A53 | #826319 | ARM64_ERRATUM_826319

[PATCH v2 1/5] arm64: Define Falkor v1 CPU

From: Shanker Donthineni Define the MIDR implementer and part number field values for the Qualcomm Datacenter Technologies Falkor processor version 1 in the usual manner. Signed-off-by: Shanker Donthineni Signed-off-by: Christopher Covington

[PATCH v2 4/5] arm64: Use __tlbi_dsb() macros in KVM code

Refactor the KVM code to use the newly introduced __tlbi_dsb macros, which will allow an errata workaround that repeats tlbi dsb sequences to only change one location. This is not intended to change the generated assembly and comparing before and after vmlinux objdump shows no functional changes.

[PATCH v2 2/5] arm64: Work around Falkor erratum 1003

From: Shanker Donthineni On the Qualcomm Datacenter Technologies Falkor v1 CPU, memory accesses may allocate TLB entries using an incorrect ASID when TTBRx_EL1 is being updated. Changing the TTBRx_EL1[ASID] and TTBRx_EL1[BADDR] fields separately using a reserved ASID

[PATCH v2 5/5] arm64: Work around Falkor erratum 1009

During a TLB invalidate sequence targeting the inner shareable domain, Falkor may prematurely complete the DSB before all loads and stores using the old translation are observed; instruction fetches are not subject to the conditions of this erratum. Signed-off-by: Christopher Covington

[PATCH v2 3/5] arm64: Create and use __tlbi_dsb() macros

This refactoring will allow an errata workaround that repeats tlbi dsb sequences to only change one location. This is not intended to change the generated assembly and comparing before and after preprocessor output of arch/arm64/mm/mmu.c and vmlinux objdump show no functional changes.