Re: [Qemu-devel] [PATCH v3 1/4] ACPI: Add APEI GHES Table Generation support

Laszlo, very sorry for that, it was my mistake that missing your name. when I reply mail, I copy the "CC" list to the mail reply list, but forget to copy the "To" list. I will check your comments in detailed later and reply you. thanks again. On 2017/5/30 0:03, Laszlo Ersek wrote: > Hi, >

Re: [PATCH 07/31] KVM: arm/arm64: vgic-v3: Add accessors for the ICH_APxRn_EL2 registers

On Tue, May 30, 2017 at 05:17:01PM +0100, Marc Zyngier wrote: > On 03/05/17 16:58, Marc Zyngier wrote: > > On 03/05/17 16:32, Mark Rutland wrote: > >> On Wed, May 03, 2017 at 11:45:42AM +0100, Marc Zyngier wrote: > >>> +static void __hyp_text __vgic_v3_write_ap0rn(u32 val, int n) > >>> +{ > >>> +

Re: [PATCH 07/31] KVM: arm/arm64: vgic-v3: Add accessors for the ICH_APxRn_EL2 registers

On 03/05/17 16:58, Marc Zyngier wrote: > On 03/05/17 16:32, Mark Rutland wrote: >> On Wed, May 03, 2017 at 11:45:42AM +0100, Marc Zyngier wrote: >>> As we're about to access the Active Priority registers a lot more, >>> let's define accessors that take the register number as a parameter. >>> >>>

Re: [PATCH 26/31] KVM: arm64: vgic-v3: Add ICV_DIR_EL1 handler

On 30/05/17 11:15, Auger Eric wrote: > Marc, > > On 03/05/2017 12:46, Marc Zyngier wrote: >> Add a handler for writing the guest's view of the ICC_DIR_EL1 >> register, performing the deactivation of an interrupt if EOImode >> is set ot 1. >> >> Signed-off-by: Marc Zyngier

Re: [PATCH 30/31] KVM: arm64: Enable GICv3 common sysreg trapping via command-line

On 30/05/17 10:56, Auger Eric wrote: > Hi, > > On 03/05/2017 12:46, Marc Zyngier wrote: >> Now that we're able to safely handle common sysreg access, let's >> give the user the opportunity to enable it by passing a specific >> command-line option (vgic_v3.common_trap). >> >> Signed-off-by: Marc

Re: [PATCH 17/31] KVM: arm64: vgic-v3: Enable trapping of Group-1 system registers

On 30/05/17 10:07, Auger Eric wrote: > Hi Marc, > > On 03/05/2017 12:45, Marc Zyngier wrote: >> In order to be able to trap Group-1 GICv3 system registers, we need to >> set ICH_HCR_EL2.TALL1 begore entering the guest. This is conditionnaly > before, conditionally >> done after having restored

Re: [PATCH 14/31] KVM: arm64: vgic-v3: Add ICV_EOIR1_EL1 handler

On 30/05/17 08:48, Auger Eric wrote: > Hi Marc > > On 03/05/2017 12:45, Marc Zyngier wrote: >> Add a handler for writing the guest's view of the ICC_EOIR1_EL1 >> register. This involves dropping the priority of the interrupt, >> and deactivating it if required (EOImode == 0). >> >> Signed-off-by:

Re: [PATCH 15/31] KVM: arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler

Hi Eric, On 30/05/17 09:02, Auger Eric wrote: > Hi Marc, > > On 30/05/2017 09:48, Auger Eric wrote: >> H Marc, >> >> On 03/05/2017 12:45, Marc Zyngier wrote: >>> Add a handler for reading/writing the guest's view of the ICV_AP1Rn_EL1 >>> registers. We just map them to the corresponding

Re: [PATCH 09/10] KVM: arm/arm64: vgic: Implement forwarding setting

Hi Marc, On 30/05/2017 15:17, Marc Zyngier wrote: > On 30/05/17 13:54, Auger Eric wrote: >> Hi, >> >> On 25/05/2017 21:19, Marc Zyngier wrote: >>> On Wed, May 24 2017 at 10:13:22 pm BST, Eric Auger >>> wrote: Implements kvm_vgic_[set|unset]_forwarding.

Re: [PATCH 09/10] KVM: arm/arm64: vgic: Implement forwarding setting

On 30/05/17 13:54, Auger Eric wrote: > Hi, > > On 25/05/2017 21:19, Marc Zyngier wrote: >> On Wed, May 24 2017 at 10:13:22 pm BST, Eric Auger >> wrote: >>> Implements kvm_vgic_[set|unset]_forwarding. >>> >>> Handle low-level VGIC programming and consistent irqchip >>>

Re: [PATCH 09/10] KVM: arm/arm64: vgic: Implement forwarding setting

Hi, On 25/05/2017 21:19, Marc Zyngier wrote: > On Wed, May 24 2017 at 10:13:22 pm BST, Eric Auger > wrote: >> Implements kvm_vgic_[set|unset]_forwarding. >> >> Handle low-level VGIC programming and consistent irqchip >> programming. >> >> Signed-off-by: Eric Auger

Re: [PATCH 08/10] KVM: arm/arm64: vgic: Handle unshared mapped interrupts

Hi Marc, On 25/05/2017 21:14, Marc Zyngier wrote: > On Wed, May 24 2017 at 10:13:21 pm BST, Eric Auger > wrote: >> Virtual interrupts directly mapped to physical interrupts require >> some special care. Their pending and active state must be observed >> at distributor

Re: [PATCH 01/10] vfio: platform: Add automasked field to vfio_platform_irq

Hi Marc, On 25/05/2017 20:05, Marc Zyngier wrote: > Hi Eric, > > On Wed, May 24 2017 at 10:13:14 pm BST, Eric Auger > wrote: >> For direct EOI modality we will need to differentiate a userspace >> masking from the IRQ handler auto-masking. >> >> Signed-off-by: Eric Auger

Re: [PATCH 29/31] KVM: arm64: vgic-v3: Add ICV_PMR_EL1 handler

Hi, On 03/05/2017 12:46, Marc Zyngier wrote: > Add a handler for reading/writing the guest's view of the ICC_PMR_EL1 > register, which is located in the ICH_VMCR_EL2.VPMR field. > > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger Eric > --- >

Re: [PATCH 28/31] KVM: arm64: vgic-v3: Add ICV_CTLR_EL1 handler

Hi, On 03/05/2017 12:46, Marc Zyngier wrote: > Add a handler for reading/writing the guest's view of the ICV_CTLR_EL1 > register. only EOIMode and CBPR are of interest here, as all the other > bits directly come from ICH_VTR_EL2 and are Read-Only. > > Signed-off-by: Marc Zyngier

Re: [PATCH 27/31] KVM: arm64: vgic-v3: Add ICV_RPR_EL1 handler

Hi, On 03/05/2017 12:46, Marc Zyngier wrote: > Add a handler for reading the guest's view of the ICV_RPR_EL1 > register, returning the highest active priority. > > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger Eric > --- >

Re: [PATCH 26/31] KVM: arm64: vgic-v3: Add ICV_DIR_EL1 handler

Marc, On 03/05/2017 12:46, Marc Zyngier wrote: > Add a handler for writing the guest's view of the ICC_DIR_EL1 > register, performing the deactivation of an interrupt if EOImode > is set ot 1. > > Signed-off-by: Marc Zyngier > --- > virt/kvm/arm/hyp/vgic-v3-sr.c | 23

Re: [PATCH 25/31] arm64: Add workaround for Cavium Thunder erratum 30115

Hi, On 03/05/2017 12:46, Marc Zyngier wrote: > From: David Daney > > Some Cavium Thunder CPUs suffer a problem where a KVM guest may > inadvertently cause the host kernel to quit receiving interrupts. > > Use the Group-0/1 trapping in order to deal with it. > > [maz]:

Re: [PATCH 31/31] KVM: arm64: vgic-v3: Log which GICv3 system registers are trapped

Hi, On 03/05/2017 12:46, Marc Zyngier wrote: > In order to facilitate debug, let's log which class of GICv3 system > registers are trapped. > > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger Eric > --- > virt/kvm/arm/vgic/vgic-v3.c | 5 - >

Re: [PATCH 24/31] arm64: Add MIDR values for Cavium cn83XX SoCs

Hi, On 03/05/2017 12:45, Marc Zyngier wrote: > From: David Daney > > Signed-off-by: David Daney > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger Eric > --- > arch/arm64/include/asm/cputype.h |

Re: [PATCH 30/31] KVM: arm64: Enable GICv3 common sysreg trapping via command-line

Hi, On 03/05/2017 12:46, Marc Zyngier wrote: > Now that we're able to safely handle common sysreg access, let's > give the user the opportunity to enable it by passing a specific > command-line option (vgic_v3.common_trap). > > Signed-off-by: Marc Zyngier What is the

Re: [PATCH 22/31] KVM: arm64: vgic-v3: Enable trapping of Group-0 system registers

Hi, On 03/05/2017 12:45, Marc Zyngier wrote: > In order to be able to trap Group-0 GICv3 system registers, we need to > set ICH_HCR_EL2.TALL0 begore entering the guest. This is conditionnaly > done after having restored the guest's state, and cleared on exit. > > Signed-off-by: Marc Zyngier

Re: [PATCH 20/31] KVM: arm64: vgic-v3: Add ICV_IGNREN0_EL1 handler

Hi, On 03/05/2017 12:45, Marc Zyngier wrote: > Add a handler for reading/writing the guest's view of the ICC_IGRPEN0_EL1 > register, which is located in the ICH_VMCR_EL2.VENG0 field. > > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger Eric >

Re: [PATCH 19/31] KVM: arm64: vgic-v3: Add ICV_BPR0_EL1 handler

Hi, On 03/05/2017 12:45, Marc Zyngier wrote: > Add a handler for reading/writing the guest's view of the ICC_BPR0_EL1 > register, which is located in the ICH_VMCR_EL2.BPR0 field. > > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger Thanks Eric >

Re: [PATCH 21/31] KVM: arm64: vgic-v3: Add misc Group-0 handlers

Hi, On 03/05/2017 12:45, Marc Zyngier wrote: > A number of Group-0 registers can be handled by the same accessors > as that of Group-1, so let's add the required system register encodings > and catch them in the dispatching function. > > Signed-off-by: Marc Zyngier

Re: [PATCH 17/31] KVM: arm64: vgic-v3: Enable trapping of Group-1 system registers

Hi Marc, On 03/05/2017 12:45, Marc Zyngier wrote: > In order to be able to trap Group-1 GICv3 system registers, we need to > set ICH_HCR_EL2.TALL1 begore entering the guest. This is conditionnaly before, conditionally > done after having restored the guest's state, and cleared on exit. > >

Re: [PATCH 16/31] KVM: arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler

Hi, On 03/05/2017 12:45, Marc Zyngier wrote: > Add a handler for reading the guest's view of the ICV_HPPIR1_EL1 > register. This is a simple parsing of the available LRs, extracting the > highest available interrupt. > > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger

Re: [PATCH 15/31] KVM: arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler

Hi Marc, On 30/05/2017 09:48, Auger Eric wrote: > H Marc, > > On 03/05/2017 12:45, Marc Zyngier wrote: >> Add a handler for reading/writing the guest's view of the ICV_AP1Rn_EL1 >> registers. We just map them to the corresponding ICH_AP1Rn_EL2 registers. >> >> Signed-off-by: Marc Zyngier

Re: [PATCH 15/31] KVM: arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler

H Marc, On 03/05/2017 12:45, Marc Zyngier wrote: > Add a handler for reading/writing the guest's view of the ICV_AP1Rn_EL1 > registers. We just map them to the corresponding ICH_AP1Rn_EL2 registers. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/include/asm/sysreg.h |

Re: [PATCH 14/31] KVM: arm64: vgic-v3: Add ICV_EOIR1_EL1 handler

Hi Marc On 03/05/2017 12:45, Marc Zyngier wrote: > Add a handler for writing the guest's view of the ICC_EOIR1_EL1 > register. This involves dropping the priority of the interrupt, > and deactivating it if required (EOImode == 0). > > Signed-off-by: Marc Zyngier > --- >