Re: [RFC PATCH v2 00/38] Nested Virtualization on KVM/ARM

On Fri, Jul 28, 2017 at 4:13 PM, Bandan Das wrote: > Jintack Lim writes: > ... >>> >>> I'll share my experiment setup shortly. >> >> I summarized my experiment setup here. >> >>

Re: [RFC PATCH v2 00/38] Nested Virtualization on KVM/ARM

Jintack Lim writes: ... >> >> I'll share my experiment setup shortly. > > I summarized my experiment setup here. > > https://github.com/columbia/nesting-pub/wiki/Nested-virtualization-on-ARM-setup Thanks Jintack! I was able to test L2 boot up with these instructions.

[PATCH v2 15/16] KVM: arm64: Save ESR_EL2 on guest SError

When we exit a guest due to an SError the vcpu fault info isn't updated with the ESR. Today this is only done for traps. The v8.2 RAS Extensions define ISS values for SError. Update the vcpu's fault_info with the ESR on SError so that handle_exit() can determine if this was a RAS SError and

[PATCH v2 14/16] KVM: arm64: Take pending SErrors on entry to the guest

SErrors due to RAS are either taken as an SError, or deferred because of an Error Synchronization Barrier (ESB). Systems that support the RAS extensions are very likely to have firmware-first handling of these errors, taking all SErrors to EL3. Add {I,}ESB support to KVM and be prepared to handle

[PATCH v2 16/16] KVM: arm64: Handle deferred SErrors consumed on guest exit

On systems with VHE, the RAS extensions and IESB support, KVM gets an implicit ESB whenever it enters/exits a guest, because the host sets SCTLR_EL1.IESB. To prevent errors being lost, add code to __guest_exit() to read DISR_EL1, and save it in the kvm_vcpu_fault_info. Add code to handle_exit()

[PATCH v2 12/16] arm64: entry.S: Make eret restartable

To gain any benefit from IESB on exception return we must unmask SError over ERET instructions so that the SError is taken to EL1, instead of deferred. SErrors deferred like this would only be processed once we take another exception, at which point they may be overwritten by a new (less severe)

[PATCH v2 05/16] arm64: entry.S: move enable_step_tsk into kernel_exit

enable_step_tsk may enable single-step, so needs to mask debug exceptions to prevent us from single-stepping kernel_exit. This should be the callers problem. Earlier cleanup (2a2830703a23) moved disable_step_tsk into kernel_entry. enable_step_tsk has two callers, both immediately before

[PATCH v2 06/16] arm64: entry.S: convert elX_sync

el1_sync unmasks exceptions on a case-by-case basis, debug exceptions are unmasked, unless this was a debug exception. IRQs are unmasked for instruction and data aborts only if the interrupted context had irqs unmasked. Following our 'adi' order, el1_dbg should run with Debug and Interrupt

[PATCH v2 13/16] arm64: cpufeature: Enable Implicit ESB on entry/return-from EL1

ARM v8.2 adds a feature to add implicit error synchronization barriers whenever the CPU enters or returns from EL1. Add code to detect this feature and enable the SCTLR_EL1.IESB bit. The explicit ESBs on entry/return-from EL1 are replaced with nops by this feature. Platform level RAS support may

[PATCH v2 11/16] arm64: kernel: Handle deferred SError on kernel entry

Before we can enable Implicit ESB on exception level change, we need to handle deferred SErrors that may appear on exception entry. Add code to kernel_entry to synchronize errors then read and clear DISR_EL1. Call do_deferred_serror() if it had a non-zero value. (The IESB feature will allow this

[PATCH v2 04/16] arm64: entry.S: mask all exceptions during kernel_exit

Add a disable_daif call to kernel_exit to mask all exceptions before restoring registers that are overwritten by an exception. This should be done before we restore sp_el0, as any exception taken from EL1 will assume this register is set correctly. After this patch it is no longer necessary to

[PATCH v2 08/16] arm64: entry.S: move SError handling into a C function for future expansion

From: Xie XiuQi Today SError is taken using the inv_entry macro that ends up in bad_mode. SError can be used by the RAS Extensions to notify either the OS or firmware of CPU problems, some of which may have been corrected. To allow this handling to be added, add a

[PATCH v2 10/16] arm64: kernel: Survive corrected RAS errors notified by SError

On v8.0, SError is an uncontainable fatal exception. The v8.2 RAS extensions use SError to notify software about RAS errors, these can be contained by the ESB instruction. An ACPI system with firmware-first may use SError as its 'SEI' notification. Future patches may add code to 'claim' this

[PATCH v2 09/16] arm64: cpufeature: Detect CPU RAS Extentions

From: Xie XiuQi ARM's v8.2 Extentions add support for Reliability, Availability and Serviceability (RAS). On CPUs with these extensions system software can use additional barriers to isolate errors and determine if faults are pending. Add cpufeature detection and a barrier

[PATCH v2 07/16] arm64: entry.S: convert elX_irq

Following our 'adi' order, Interrupts should be processed with Debug and SError exceptions unmasked. Add a helper to unmask these two, (and fiq for good measure). Signed-off-by: James Morse --- arch/arm64/include/asm/assembler.h | 10 +- arch/arm64/kernel/entry.S

[PATCH v2 00/16] SError rework + v8.2 RAS and IESB cpufeature support

Hello, This series reworks the exception masking so that SError is unmasked ~all the time, and adds the RAS and IESB cpufeatures. The major change from v1 is the priority-order for DAIF exceptions after the SError rework is different due to IESB. The SError rework is needed for the esb in

[PATCH v2 03/16] arm64: unmask all exceptions from C code on CPU startup

On startup (and before any C code) __cpu_setup() resets the debug configuration register MDSCR_EL1 to disable MDE and KDE, it then umasks Debug exceptions. On first boot, once we get into the setup.c on CPU0, we unmask SError. IRQs are unmasked some time later by core code. FIQ is only unmasked

[PATCH v2 02/16] arm64: introduce an order for exceptions

Lets define an order for masking and unmasking exceptions. To support v8.2's RAS extentions, which are notified by SError, 'A' needs to be the highest priority, (so we can leave PSTATE.A unmasked over an eret). Debug should come next so our order is 'ADI'. Masking debug exceptions should cause