Re: [PATCH v4 20/21] KVM: arm64: Take any host SError before entering the guest

On Tue, Oct 31, 2017 at 11:43:42AM +, James Morse wrote: > Hi Christoffer, > > On 31/10/17 06:23, Christoffer Dall wrote: > > On Thu, Oct 19, 2017 at 03:58:06PM +0100, James Morse wrote: > >> On VHE systems KVM masks SError before switching the VBAR value. Any > >> host RAS error that the CPU

Re: [PATCH v5 04/30] arm64: KVM: Hide unsupported AArch64 CPU features from guests

On Tue, Oct 31, 2017 at 03:50:56PM +, Dave Martin wrote: > Currently, a guest kernel sees the true CPU feature registers > (ID_*_EL1) when it reads them using MRS instructions. This means > that the guest may observe features that are present in the > hardware but the host doesn't understand

[PATCH v5 20/30] arm64/sve: Preserve SVE registers around EFI runtime service calls

The EFI runtime services ABI allows EFI to make free use of the FPSIMD registers during EFI runtime service calls, subject to the callee-save requirements of the AArch64 procedure call standard. However, the SVE architecture allows upper bits of the SVE vector registers to be zeroed as a

[PATCH v5 26/30] arm64/sve: KVM: Hide SVE from CPU features exposed to guests

KVM guests cannot currently use SVE, because SVE is always configured to trap to EL2. However, a guest that sees SVE reported as present in ID_AA64PFR0_EL1 may legitimately expect that SVE works and try to use it. Instead of working, the guest will receive an injected undef exception, which may

[RFC PATCH v5 30/30] arm64/sve: signal: Include SVE when computing AT_MINSIGSTKSZ

The SVE context block in the signal frame needs to be considered too when computing the maximum possible signal frame size. Because the size of this block depends on the vector length, this patch computes the size based not on the thread's current vector length but instead on the maximum possible

[PATCH v5 28/30] arm64/sve: Add documentation

This patch adds basic documentation of the user/kernel interface provided by the for SVE. Signed-off-by: Dave Martin Reviewed-by: Catalin Marinas Cc: Alan Hayward Cc: Alex Bennée Cc: Mark Rutland

[RFC PATCH v5 29/30] arm64: signal: Report signal frame size to userspace via auxv

Stateful CPU architecture extensions may require the signal frame to grow to a size that exceeds the arch's MINSIGSTKSZ #define. However, changing this #define is an ABI break. To allow userspace the option of determining the signal frame size in a more forwards-compatible way, this patch adds a

[PATCH v5 27/30] arm64/sve: Detect SVE and activate runtime support

This patch enables detection of hardware SVE support via the cpufeatures framework, and reports its presence to the kernel and userspace via the new ARM64_SVE cpucap and HWCAP_SVE hwcap respectively. Userspace can also detect SVE using ID_AA64PFR0_EL1, using the cpufeatures MRS emulation. When

[PATCH v5 23/30] arm64/sve: Add sysctl to set the default vector length for new processes

Because of the effect of SVE on the size of the signal frame, the default vector length used for new processes involves a tradeoff between performance of SVE-enabled software on the one hand, and reliability of non-SVE-aware software on the other hand. For this reason, the best choice depends on

[PATCH v5 24/30] arm64/sve: KVM: Prevent guests from using SVE

Until KVM has full SVE support, guests must not be allowed to execute SVE instructions. This patch enables the necessary traps, and also ensures that the traps are disabled again on exit from the guest so that the host can still use SVE if it wants to. On guest exit, high bits of the SVE Zn

[PATCH v5 18/30] arm64/sve: Probe SVE capabilities and usable vector lengths

This patch uses the cpufeatures framework to determine common SVE capabilities and vector lengths, and configures the runtime SVE support code appropriately. ZCR_ELx is not really a feature register, but it is convenient to use it as a template for recording the maximum vector length supported by

[PATCH v5 25/30] arm64/sve: KVM: Treat guest SVE use as undefined instruction execution

When trapping forbidden attempts by a guest to use SVE, we want the guest to see a trap consistent with SVE not being implemented. This patch injects an undefined instruction exception into the guest in response to such an exception. Signed-off-by: Dave Martin Reviewed-by:

[PATCH v5 21/30] arm64/sve: ptrace and ELF coredump support

This patch defines and implements a new regset NT_ARM_SVE, which describes a thread's SVE register state. This allows a debugger to manipulate the SVE state, as well as being included in ELF coredumps for post-mortem debugging. Because the regset size and layout are dependent on the thread's

[PATCH v5 22/30] arm64/sve: Add prctl controls for userspace vector length management

This patch adds two arm64-specific prctls, to permit userspace to control its vector length: * PR_SVE_SET_VL: set the thread's SVE vector length and vector length inheritance mode. * PR_SVE_GET_VL: get the same information. Although these prctls resemble instruction set features in the SVE

[PATCH v5 17/30] arm64: cpufeature: Move sys_caps_initialised declarations

update_cpu_features() currently cannot tell whether it is being called during early or late secondary boot. This doesn't desperately matter for anything it currently does. However, SVE will need to know here whether the set of available vector lengths is known or still to be determined when

[PATCH v5 15/30] arm64/sve: Signal handling support

This patch implements support for saving and restoring the SVE registers around signals. A fixed-size header struct sve_context is always included in the signal frame encoding the thread's vector length at the time of signal delivery, optionally followed by a variable-layout structure encoding

[PATCH v5 16/30] arm64/sve: Backend logic for setting the vector length

This patch implements the core logic for changing a task's vector length on request from userspace. This will be used by the ptrace and prctl frontends that are implemented in later patches. The SVE architecture permits, but does not require, implementations to support vector lengths that are

[PATCH v5 07/30] arm64: fpsimd: Simplify uses of {set, clear}_ti_thread_flag()

The existing FPSIMD context switch code contains a couple of instances of {set,clear}_ti_thread(task_thread_info(task)). Since there are thread flag manipulators that operate directly on task_struct, this verbosity isn't strictly needed. For consistency, this patch simplifies the affected calls.

[PATCH v5 14/30] arm64/sve: Support vector length resetting for new processes

It's desirable to be able to reset the vector length to some sane default for new processes, since the new binary and its libraries may or may not be SVE-aware. This patch tracks the desired post-exec vector length (if any) in a new thread member sve_vl_onexec, and adds a new thread flag

[PATCH v5 09/30] arm64/sve: Low-level SVE architectural state manipulation functions

Manipulating the SVE architectural state, including the vector and predicate registers, first-fault register and the vector length, requires the use of dedicated instructions added by SVE. This patch adds suitable assembly functions for saving and restoring the SVE registers and querying the

[PATCH v5 08/30] arm64/sve: System register and exception syndrome definitions

The SVE architecture adds some system registers, ID register fields and a dedicated ESR exception class. This patch adds the appropriate definitions that will be needed by the kernel. Signed-off-by: Dave Martin Reviewed-by: Alex Bennée Reviewed-by:

[PATCH v5 19/30] arm64/sve: Preserve SVE registers around kernel-mode NEON use

Kernel-mode NEON will corrupt the SVE vector registers, due to the way they alias the FPSIMD vector registers in the hardware. This patch ensures that any live SVE register content for the task is saved by kernel_neon_begin(). The data will be restored in the usual way on return to userspace.

[PATCH v5 11/30] arm64/sve: Signal frame and context structure definition

This patch defines the representation that will be used for the SVE register state in the signal frame, and implements support for saving and restoring the SVE registers around signals. The same layout will also be used for the in-kernel task state. Due to the variability of the SVE vector

[PATCH v5 13/30] arm64/sve: Core task context handling

This patch adds the core support for switching and managing the SVE architectural state of user tasks. Calls to the existing FPSIMD low-level save/restore functions are factored out as new functions task_fpsimd_{save,load}(), since SVE now dynamically may or may not need to be handled at these

[PATCH v5 10/30] arm64/sve: Kconfig update and conditional compilation support

This patch adds CONFIG_ARM64_SVE to control building of SVE support into the kernel, and adds a stub predicate system_supports_sve() to control conditional compilation and runtime SVE support. system_supports_sve() just returns false for now: it will be replaced with a non-trivial implementation

[PATCH v5 12/30] arm64/sve: Low-level CPU setup

To enable the kernel to use SVE, SVE traps from EL1 to EL2 must be disabled. To take maximum advantage of the hardware, the full available vector length also needs to be enabled for EL1 by programming ZCR_EL2.LEN. (The kernel will program ZCR_EL1.LEN as required, but this cannot override the

[PATCH v5 05/30] arm64: efi: Add missing Kconfig dependency on KERNEL_MODE_NEON

The EFI runtime services ABI permits calls to EFI to clobber certain FPSIMD/NEON registers, as per the AArch64 procedure call standard. Saving/restoring the clobbered registers around such calls needs KERNEL_MODE_NEON, but the dependency is missing from Kconfig. This patch adds the missing

[PATCH v5 06/30] arm64: Port deprecated instruction emulation to new sysctl interface

Currently, armv8_deprected.c takes charge of the "abi" sysctl directory, which makes life difficult for other code that wants to register sysctls in the same directory. There is a "new" [1] sysctl registration interface that removes the need to define ctl_tables for parent directories explicitly,

[PATCH v5 03/30] arm64: signal: Verify extra data is user-readable in sys_rt_sigreturn

Currently sys_rt_sigreturn() verifies that the base sigframe is readable, but no similar check is performed on the extra data to which an extra_context record points. This matters because the extra data will be read with the unprotected user accessors. However, this is not a problem at present

[PATCH v5 04/30] arm64: KVM: Hide unsupported AArch64 CPU features from guests

Currently, a guest kernel sees the true CPU feature registers (ID_*_EL1) when it reads them using MRS instructions. This means that the guest may observe features that are present in the hardware but the host doesn't understand or doesn't provide support for. A guest may legimitately try to use

[PATCH v5 01/30] regset: Add support for dynamically sized regsets

Currently the regset API doesn't allow for the possibility that regsets (or at least, the amount of meaningful data in a regset) may change in size. In particular, this results in useless padding being added to coredumps if a regset's current size is smaller than its theoretical maximum size.

[PATCH v5 02/30] arm64: fpsimd: Correctly annotate exception helpers called from asm

A couple of FPSIMD exception handling functions that are called from entry.S are currently not annotated as such. This is not a big deal since asmlinkage does nothing on arm/arm64, but fixing the annotations is more consistent and may help avoid future surprises. This patch adds appropriate

[PATCH v5 00/30] ARM Scalable Vector Extension (SVE)

This series implements Linux kernel support for the ARM Scalable Vector Extension (SVE). [1] It supersedes the previous v3: see [3] for link and full cover letter. This is a minor update to v4, but does contain a couple of important fixes. As in previous postings, the last two patches (here

Re: [PATCH v4 13/21] arm64: cpufeature: Enable IESB on exception entry/return for firmware-first

On Thu, Oct 19, 2017 at 03:57:59PM +0100, James Morse wrote: > ARM v8.2 has a feature to add implicit error synchronization barriers > whenever the CPU enters or returns from an exception level. Add code to > detect this feature and enable the SCTLR_ELx.IESB bit. > > This feature causes RAS

Re: [PATCH v2 2/8] arm: KVM: Add optimized PIPT icache flushing

On Sat, Oct 21, 2017 at 05:18:17PM +0200, Christoffer Dall wrote: > On Fri, Oct 20, 2017 at 05:54:40PM +0100, Mark Rutland wrote: > > On Fri, Oct 20, 2017 at 05:53:39PM +0100, Marc Zyngier wrote: > > > On 20/10/17 17:27, Mark Rutland wrote: > > > > On Fri, Oct 20, 2017 at 04:48:58PM +0100, Marc

Re: [PATCH v4 12/21] arm64: kernel: Survive corrected RAS errors notified by SError

On Thu, Oct 19, 2017 at 03:57:58PM +0100, James Morse wrote: > Prior to v8.2, SError is an uncontainable fatal exception. The v8.2 RAS > extensions use SError to notify software about RAS errors, these can be > contained by the ESB instruction. > > An ACPI system with firmware-first may use

Re: [PATCH v4 11/21] arm64: cpufeature: Detect CPU RAS Extentions

On Thu, Oct 19, 2017 at 03:57:57PM +0100, James Morse wrote: > From: Xie XiuQi > > ARM's v8.2 Extentions add support for Reliability, Availability and > Serviceability (RAS). On CPUs with these extensions system software > can use additional barriers to isolate errors and

Re: [PATCH v4 20/21] KVM: arm64: Take any host SError before entering the guest

Hi Christoffer, On 31/10/17 06:23, Christoffer Dall wrote: > On Thu, Oct 19, 2017 at 03:58:06PM +0100, James Morse wrote: >> On VHE systems KVM masks SError before switching the VBAR value. Any >> host RAS error that the CPU knew about before world-switch may become >> pending as an SError during

Re: [PATCH v4 02/28] arm64: KVM: Hide unsupported AArch64 CPU features from guests

Dave Martin writes: > Currently, a guest kernel sees the true CPU feature registers > (ID_*_EL1) when it reads them using MRS instructions. This means > that the guest may observe features that are present in the > hardware but the host doesn't understand or doesn't

Re: [PATCH v4 00/21] SError rework + RAS for firmware first support

On Tue, Oct 31, 2017 at 07:35:35AM +0100, Christoffer Dall wrote: > Hi James, Catalin, and Will, > > On Thu, Oct 19, 2017 at 03:57:46PM +0100, James Morse wrote: > > Hello, > > > > The aim of this series is to enable IESB and add ESB-instructions to let us > > kick any pending RAS errors into

Re: [PATCH v6 0/9] vITS Migration fixes and reset

On Mon, Oct 30, 2017 at 08:59:36AM +0100, Auger Eric wrote: > Hi Christoffer, > > On 30/10/2017 07:20, Christoffer Dall wrote: > > Hi Eric, > > > > On Thu, Oct 26, 2017 at 05:23:02PM +0200, Eric Auger wrote: > >> This series fixes various bugs observed when saving/restoring the > >> ITS state

Re: [PATCH v4 00/21] SError rework + RAS for firmware first support

Hi James, Catalin, and Will, On Thu, Oct 19, 2017 at 03:57:46PM +0100, James Morse wrote: > Hello, > > The aim of this series is to enable IESB and add ESB-instructions to let us > kick any pending RAS errors into firmware to be handled by firmware-first. > > Not all systems will have this

Re: [PATCH v4 15/21] KVM: arm64: Set an impdef ESR for Virtual-SError using VSESR_EL2.

On Thu, Oct 19 2017 at 4:58:01 pm BST, James Morse wrote: > Prior to v8.2's RAS Extensions, the HCR_EL2.VSE 'virtual SError' feature > generated an SError with an implementation defined ESR_EL1.ISS, because we > had no mechanism to specify the ESR value. > > On Juno this

Re: [PATCH v4 21/21] KVM: arm64: Trap RAS error registers and set HCR_EL2's TERR & TEA

On Thu, Oct 19 2017 at 4:58:07 pm BST, James Morse wrote: > From: Dongjiu Geng > > ARMv8.2 adds a new bit HCR_EL2.TEA which routes synchronous external > aborts to EL2, and adds a trap control bit HCR_EL2.TERR which traps > all Non-secure EL1&0 error

Re: [PATCH v4 21/21] KVM: arm64: Trap RAS error registers and set HCR_EL2's TERR & TEA

On Thu, Oct 19, 2017 at 03:58:07PM +0100, James Morse wrote: > From: Dongjiu Geng > > ARMv8.2 adds a new bit HCR_EL2.TEA which routes synchronous external > aborts to EL2, and adds a trap control bit HCR_EL2.TERR which traps > all Non-secure EL1&0 error record accesses to

Re: [PATCH v4 20/21] KVM: arm64: Take any host SError before entering the guest

Hi James, On Thu, Oct 19, 2017 at 03:58:06PM +0100, James Morse wrote: > On VHE systems KVM masks SError before switching the VBAR value. Any > host RAS error that the CPU knew about before world-switch may become > pending as an SError during world-switch, and only be taken once we enter > the

Re: [PATCH v4 19/21] KVM: arm64: Handle RAS SErrors from EL2 on guest exit

On Thu, Oct 19, 2017 at 03:58:05PM +0100, James Morse wrote: > We expect to have firmware-first handling of RAS SErrors, with errors > notified via an APEI method. For systems without firmware-first, add > some minimal handling to KVM. > > There are two ways KVM can take an SError due to a guest,

Re: [PATCH v4 19/21] KVM: arm64: Handle RAS SErrors from EL2 on guest exit

On Thu, Oct 19 2017 at 4:58:05 pm BST, James Morse wrote: > We expect to have firmware-first handling of RAS SErrors, with errors > notified via an APEI method. For systems without firmware-first, add > some minimal handling to KVM. > > There are two ways KVM can take an