On 11/12, Shanker Donthineni wrote:
> The ARM architecture defines the memory locations that are permitted
> to be accessed as the result of a speculative instruction fetch from
> an exception level for which all stages of translation are disabled.
> Specifically, the core is permitted to
VTTBR_BADDR_MASK is used to sanity check the size and alignment of the
VTTBR address. It seems to currently be off by one, thereby only
allowing up to 47-bit addresses (instead of 48-bit) and also
insufficiently checking the alignment. This patch fixes it.
As an example, with 4k pages, before
Hi Christopher,
On 12/10/17 11:41, Christoffer Dall wrote:
The debug save/restore functions can be improved by using the has_vhe()
static key instead of the instruction alternative. Using the static key
uses the same paradigm as we're going to use elsewhere, it makes the
code more readable,
Hi Drew,
On 13/11/17 16:14, Andrew Jones wrote:
> On Mon, Nov 13, 2017 at 12:29:46PM +0100, Christoffer Dall wrote:
>> On Thu, Nov 09, 2017 at 06:14:56PM +, James Morse wrote:
>>> On 19/10/17 15:57, James Morse wrote:
Known issues:
* KVM-Migration: VDISR_EL2 is exposed to userspace
Hi Christoffer,
On 13/11/17 11:29, Christoffer Dall wrote:
> On Thu, Nov 09, 2017 at 06:14:56PM +, James Morse wrote:
>> On 19/10/17 15:57, James Morse wrote:
>>> Known issues:
>> [...]
>>> * KVM-Migration: VDISR_EL2 is exposed to userspace as DISR_EL1, but how
>>> should
>>>HCR_EL2.VSE
Hi Dongjiu Geng,
On 10/11/17 19:54, Dongjiu Geng wrote:
> This series patches mainly do below things:
>
> 1. Trap RAS ERR* registers Accesses to EL2 from Non-secure EL1,
>KVM will will do a minimum simulation, there registers are simulated
>to RAZ/WI in KVM.
> 2. Route synchronous
Hi Dongjiu Geng,
On 10/11/17 19:54, Dongjiu Geng wrote:
> If it is not RAS SError, directly inject virtual SError,
> which will keep the old way. If it is RAS SError, firstly
> let host ACPI module to handle it.
> For the ACPI handling,
> if the error address is invalid, APEI driver will not
>
Hi Christoffer,
On 12/10/17 11:41, Christoffer Dall wrote:
We currently have a separate read-modify-write of the HCR_EL2 on entry
to the guest for the sole purpose of setting the VF and VI bits, if set.
Since this is most rarely the case (only when using userspace IRQ chip
and interrupts are in
