[PATCH v2] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

The DCache clean & ICache invalidation requirements for instructions to be data coherence are discoverable through new fields in CTR_EL0. The following two control bits DIC and IDC were defined for this purpose. No need to perform point of unification cache maintenance operations from software on

Re: [PATCH] arm64: Add support for new control bits CTR_EL0.IDC and CTR_EL0.IDC

Hi Shanker, Thank you for the patch! Yet something to improve: [auto build test ERROR on linus/master] [also build test ERROR on v4.16-rc2 next-20180219] [cannot apply to arm64/for-next/core] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url

Re: [PATCH 00/11] APEI in_nmi() rework and arm64 SDEI wire-up

On Thu, Feb 15, 2018 at 06:55:55PM +, James Morse wrote: > Hello! > > The aim of this series is to wire arm64's SDEI into APEI. > > What's SDEI? Its ARM's "Software Delegated Exception Interface" [0]. It's > used by firmware to tell the OS about firmware-first RAS events. > > These Software

Re: [PATCH] arm64: Add support for new control bits CTR_EL0.IDC and CTR_EL0.IDC

Thanks Catalin for your comments. On 02/19/2018 11:18 AM, Catalin Marinas wrote: > On Mon, Feb 19, 2018 at 10:35:30AM -0600, Shanker Donthineni wrote: >> On 02/19/2018 08:38 AM, Catalin Marinas wrote: >>> On the patch, I'd rather have an alternative framework entry for no VAU >>> cache maint

Re: [PATCH v4 24/40] KVM: arm64: Rewrite system register accessors to read/write functions

Hi Christoffer, On 15/02/18 21:03, Christoffer Dall wrote: From: Christoffer Dall Currently we access the system registers array via the vcpu_sys_reg() macro. However, we are about to change the behavior to some times modify the register file directly, so let's change

Re: [PATCH v4 17/40] KVM: arm64: Move userspace system registers into separate function

Hi Christoffer, On 15/02/18 21:03, Christoffer Dall wrote: There's a semantic difference between the EL1 registers that control operation of a kernel running in EL1 and EL1 registers that only control userspace execution in EL0. Since we can defer saving/restoring the latter, move them into

Re: [PATCH] arm64: Add support for new control bits CTR_EL0.IDC and CTR_EL0.IDC

On Mon, Feb 19, 2018 at 10:35:30AM -0600, Shanker Donthineni wrote: > On 02/19/2018 08:38 AM, Catalin Marinas wrote: > > On the patch, I'd rather have an alternative framework entry for no VAU > > cache maint required and some ret instruction at the beginning of the > > cache maint function rather

Re: [PATCH] arm64: Add support for new control bits CTR_EL0.IDC and CTR_EL0.IDC

Hi Will, On 02/19/2018 08:43 AM, Will Deacon wrote: > Hi Shanker, > > On Fri, Feb 16, 2018 at 06:57:46PM -0600, Shanker Donthineni wrote: >> Two point of unification cache maintenance operations 'DC CVAU' and >> 'IC IVAU' are optional for implementors as per ARMv8 specification. >> This patch

Re: [PATCH] arm64: Add support for new control bits CTR_EL0.IDC and CTR_EL0.IDC

Hi Catalin, On 02/19/2018 08:38 AM, Catalin Marinas wrote: > On Fri, Feb 16, 2018 at 06:57:46PM -0600, Shanker Donthineni wrote: >> Two point of unification cache maintenance operations 'DC CVAU' and >> 'IC IVAU' are optional for implementors as per ARMv8 specification. >> This patch parses the

Re: [PATCH v3 17/41] KVM: arm64: Remove noop calls to timer save/restore from VHE switch

Hi Christoffer, Sorry for the late reply. On 13/02/18 22:31, Christoffer Dall wrote: On Fri, Feb 09, 2018 at 05:53:43PM +, Julien Grall wrote: Hi Christoffer, On 01/12/2018 12:07 PM, Christoffer Dall wrote: The VHE switch function calls __timer_enable_traps and __timer_disable_traps

Re: [PATCH v4 03/40] KVM: arm64: Avoid storing the vcpu pointer on the stack

Hi Christoffer, On 15/02/18 21:02, Christoffer Dall wrote: We already have the percpu area for the host cpu state, which points to the VCPU, so there's no need to store the VCPU pointer on the stack on every context switch. We can be a little more clever and just use tpidr_el2 for the percpu

[PATCH] KVM: arm/arm64: No need to zero CNTVOFF in kvm_timer_vcpu_put() for VHE

In AArch64/AArch32, the virtual counter uses a fixed virtual offset of zero in the following situations as per ARMv8 specifications: 1) HCR_EL2.E2H is 1, and CNTVCT_EL0/CNTVCT are read from EL2. 2) HCR_EL2.{E2H, TGE} is {1, 1}, and either: — CNTVCT_EL0 is read from Non-secure EL0 or EL2. —

Re: [PATCH] arm64: Add support for new control bits CTR_EL0.IDC and CTR_EL0.IDC

Hi Shanker, On Fri, Feb 16, 2018 at 06:57:46PM -0600, Shanker Donthineni wrote: > Two point of unification cache maintenance operations 'DC CVAU' and > 'IC IVAU' are optional for implementors as per ARMv8 specification. > This patch parses the updated CTR_EL0 register definition and adds > the

Re: [PATCH v4 10/19] KVM: arm/arm64: Do not use kern_hyp_va() with kvm_vgic_global_state

On Fri, Feb 16, 2018 at 09:33:39AM +, Marc Zyngier wrote: > On 16/02/18 09:05, Christoffer Dall wrote: > > On Thu, Feb 15, 2018 at 01:22:56PM +, Marc Zyngier wrote: > >> On 15/01/18 15:36, Christoffer Dall wrote: > >>> On Thu, Jan 04, 2018 at 06:43:25PM +, Marc Zyngier wrote: >

Re: [PATCH] arm64: Add support for new control bits CTR_EL0.IDC and CTR_EL0.IDC

On Fri, Feb 16, 2018 at 06:57:46PM -0600, Shanker Donthineni wrote: > Two point of unification cache maintenance operations 'DC CVAU' and > 'IC IVAU' are optional for implementors as per ARMv8 specification. > This patch parses the updated CTR_EL0 register definition and adds > the required

Re: [PATCH 1/4] iommu: Add virtio-iommu driver

Hi Jean, On 14.02.2018 15:53, Jean-Philippe Brucker wrote: The virtio IOMMU is a para-virtualized device, allowing to send IOMMU requests such as map/unmap over virtio-mmio transport without emulating page tables. This implementation handles ATTACH, DETACH, MAP and UNMAP requests. The bulk of