On Thu, 2 May 2019 11:53:34 +0100
Jean-Philippe Brucker wrote:
> On 02/05/2019 07:58, Auger Eric wrote:
> > Hi Jean-Philippe,
> >
> > On 5/1/19 12:38 PM, Jean-Philippe Brucker wrote:
> >> On 08/04/2019 13:18, Eric Auger wrote:
> >>> +int iommu_cache_invalidate(struct iommu_domain *domain,
On 02/05/2019 07:58, Auger Eric wrote:
> Hi Jean-Philippe,
>
> On 5/1/19 12:38 PM, Jean-Philippe Brucker wrote:
>> On 08/04/2019 13:18, Eric Auger wrote:
>>> +int iommu_cache_invalidate(struct iommu_domain *domain, struct device *dev,
>>> + struct iommu_cache_invalidate_info
Hi Andrew,
I have a few remarks. I don't think it's anything major, nor that the
approach need to be changed.
On 01/05/2019 17:31, Andrew Murray wrote:
> ARMv8 provides support for chained PMU counters, where an event type
> of 0x001E is set for odd-numbered counters, the event counter will
>
On Wed, May 01, 2019 at 05:20:49PM +0100, Marc Zyngier wrote:
> On 01/05/2019 17:10, Kristina Martsenko wrote:
> > When a VCPU doesn't have pointer auth, we want to hide all four pointer
> > auth ID register fields from the guest, not just one of them.
> >
> > Fixes: 384b40caa8af ("KVM:
Hi Jean-Philippe,
On 5/1/19 12:38 PM, Jean-Philippe Brucker wrote:
> On 08/04/2019 13:18, Eric Auger wrote:
>> +int iommu_cache_invalidate(struct iommu_domain *domain, struct device *dev,
>> + struct iommu_cache_invalidate_info *inv_info)
>> +{
>> +int ret = 0;
>> +
>> +
