Hi,
On RISC-V, we can only use ASID if there are more ASIDs than CPUs. If there
aren't enough ASIDs (or if there is only 1), then ASID feature is disabled and
0 is used everywhere.
Best,
Gary
> -Original Message-
> From: Palmer Dabbelt
> Sent: Wednesday, June 5, 2019 21:42
> To: julie
On Mon, 10 Jun 2019 13:45:02 +0100
Jean-Philippe Brucker wrote:
> On 07/06/2019 18:43, Jacob Pan wrote:
> >>> So it seems we agree on the following:
> >>> - iommu_unregister_device_fault_handler() will never fail
> >>> - iommu driver cleans up all pending faults when handler is
> >>> unregistered
On 10/06/2019 17:24, James Morse wrote:
> SError that occur during world-switch's entry to the guest will be
> accounted to the guest, as the exception is masked until we enter the
> guest... but we want to attribute the SError as precisely as possible.
>
> Reading DISR_EL1 before guest entry requ
Hi James,
On 10/06/2019 17:30, James Morse wrote:
> During __guest_exit() we need to consume any SError left pending by the
> guest so it doesn't contaminate the host. With v8.2 we use the
> ESB-instruction. For systems without v8.2, we use dsb+isb and unmask
> SError. We do this on every guest ex
Hi James,
On 10/06/2019 17:30, James Morse wrote:
During __guest_exit() we need to consume any SError left pending by the
guest so it doesn't contaminate the host. With v8.2 we use the
ESB-instruction. For systems without v8.2, we use dsb+isb and unmask
SError. We do this on every guest exit.
U
During __guest_exit() we need to consume any SError left pending by the
guest so it doesn't contaminate the host. With v8.2 we use the
ESB-instruction. For systems without v8.2, we use dsb+isb and unmask
SError. We do this on every guest exit.
Use the same dsb+isr_el1 trick, this lets us know if a
The KVM indirect vectors support is a little complicated. Different CPUs
may use different exception vectors for KVM that are generated at boot.
Adding new instructions involves checking all the possible combinations
do the right thing.
To make changes here easier to review lets state what we expe
SError that occur during world-switch's entry to the guest will be
accounted to the guest, as the exception is masked until we enter the
guest... but we want to attribute the SError as precisely as possible.
Reading DISR_EL1 before guest entry requires free registers, and using
ESB+DISR_EL1 to con
Hello,
This series started as a workaround for Neoverse-N1 #1349291, but has
become an improvement in RAS error accounting for KVM on arm64.
Neoverse-N1 affected by #1349291 may report an Uncontained RAS Errors
as Unrecoverable. [0] This is the difference between killing the thread and
killing th
On systems with v8.2 we switch the 'vaxorcism' of guest SError with an
alternative sequence that uses the ESB-instruction, then reads DISR_EL1.
This saves the unmasking and remasking of asyncronous exceptions.
We do this after we've saved the guest registers and restored the
host's. Any SError tha
Neoverse-N1 affected by #1349291 may report an Uncontained RAS Error
as Unrecoverable. The kernel's architecture code already considers
Unrecoverable errors as fatal as without kernel-first support no
further error-handling is possible.
Now that KVM attributes SError to the host/guest more precise
The EL2 vector hardening feature causes KVM to generate vectors for
each type of CPU present in the system. The generated sequences already
do some of the early guest-exit work (i.e. saving registers). To avoid
duplication the generated vectors branch to the original vector just
after the preamble.
The ESB-instruction is a nop on CPUs that don't implement the RAS
extensions. This lets us use it in places like the vectors without
having to use alternatives.
If someone disables CONFIG_ARM64_RAS_EXTN, this instruction still has
its RAS extensions behaviour, but we no longer read DISR_EL1 as thi
Hi Andrew,
@@ -398,27 +531,43 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu
*vcpu, u64 select_idx)
/* Software increment event does't need to be backed by a perf event */
if (eventsel == ARMV8_PMUV3_PERFCTR_SW_INCR &&
- select_idx != ARMV8_PMU_CYCLE_IDX)
+
On 22/05/2019 17:26, Andrew Murray wrote:
On Wed, May 22, 2019 at 05:07:31PM +0100, Marc Zyngier wrote:
On 22/05/2019 16:30, Andrew Murray wrote:
We currently use pmc->bitmask to determine the width of the pmc - however
it's superfluous as the pmc index already describes if the pmc is a cycl
On 07/06/2019 18:43, Jacob Pan wrote:
>>> So it seems we agree on the following:
>>> - iommu_unregister_device_fault_handler() will never fail
>>> - iommu driver cleans up all pending faults when handler is
>>> unregistered
>>> - assume device driver or guest not sending more page response
>>> _aft
On Wed, May 22, 2019 at 04:30:17PM +0100, Andrew Murray wrote:
> The ARMv8 Performance Monitors Extension includes an architectural
> event type named CHAIN which allows for chaining counters together.
>
> Let's extract the test for this event into a header file such that
> other users, such as KV
Hi Andrew,
On 22/05/2019 16:30, Andrew Murray wrote:
> ARMv8 provides support for chained PMU counters, where an event type
> of 0x001E is set for odd-numbered counters, the event counter will
> increment by one for each overflow of the preceding even-numbered
> counter. Let's emulate this in KVM
This routine is a one-liner and doesn't really need to be function and
can be implemented as a macro.
Suggested-by: Dave Martin
Reviewed-by: Dave Martin
Signed-off-by: Viresh Kumar
---
V2->V3:
- Pass "vqs" instead of "&vqs" to vq_present().
- Added Reviewed-by from Dave.
V1->V2:
- The previous
On Mon, Jun 10, 2019 at 03:20:30PM +0530, Viresh Kumar wrote:
> On 10-06-19, 10:09, Dave Martin wrote:
> > You could drop the extra level of indirection on vqs now. The only
> > thing it achieves is to enforce the size of the array via type-
> > checkout, but the macro can't easily do that (unless
On 10-06-19, 10:09, Dave Martin wrote:
> You could drop the extra level of indirection on vqs now. The only
> thing it achieves is to enforce the size of the array via type-
> checkout, but the macro can't easily do that (unless you can think
> of another way to do it).
>
> Otherwise, looks good.
On Mon, Jun 10, 2019 at 11:36:33AM +0530, Viresh Kumar wrote:
> This routine is a one-liner and doesn't really need to be function and
> should be rather implemented as a macro.
>
> Suggested-by: Dave Martin
> Signed-off-by: Viresh Kumar
> ---
> V1->V2:
> - The previous implementation was fixing
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