Hi all,
I have been playing with the latest branch of Linux RT (5.2-rt1) and notice the
following splat when starting a KVM guest.
[ 122.336254] 003: BUG: sleeping function called from invalid context at
kernel/locking/rtmutex.c:968
[ 122.336263] 003: in_atomic(): 1, irqs_disabled(): 0,
Hi Eric,
On 23/07/2019 16:10, Auger Eric wrote:
> Hi Marc,
>
> On 6/11/19 7:03 PM, Marc Zyngier wrote:
>> When performing an MSI injection, let's first check if the translation
>> is already in the cache. If so, let's inject it quickly without
>> going through the whole translation process.
>>
Hi Marc,
On 6/11/19 7:03 PM, Marc Zyngier wrote:
> On a successful translation, preserve the parameters in the LPI
> translation cache. Each translation is reusing the last slot
> in the list, naturally evincting the least recently used entry.
evicting
>
> Signed-off-by: Marc Zyngier
> ---
>
Hi Marc,
On 6/11/19 7:03 PM, Marc Zyngier wrote:
> Now that we have a cache of MSI->LPI translations, it is pretty
> easy to implement kvm_arch_set_irq_inatomic (this cache can be
> parsed without sleeping).
>
> Hopefully, this will improve some LPI-heavy workloads.
>
> Signed-off-by: Marc
Hi Marc,
On 6/11/19 7:03 PM, Marc Zyngier wrote:
> When performing an MSI injection, let's first check if the translation
> is already in the cache. If so, let's inject it quickly without
> going through the whole translation process.
>
> Signed-off-by: Marc Zyngier
> ---
>
Hi Marc,
On 6/11/19 7:03 PM, Marc Zyngier wrote:
> If a vcpu disables LPIs at its redistributor level, we need to make sure
> we won't pend more interrupts. For this, we need to invalidate the LPI
> translation cache.
>
> Signed-off-by: Marc Zyngier
Reviewed-by: Eric Auger
Thanks
Eric
> ---
Hi Marc,
On 6/11/19 7:03 PM, Marc Zyngier wrote:
> In order to avoid leaking vgic_irq structures on teardown, we need to
> drop all references to LPIs before deallocating the cache itself.
>
> This is done by invalidating the cache on vgic teardown.
>
> Signed-off-by: Marc Zyngier
> ---
>
Hi Marc,
On 7/23/19 2:43 PM, Marc Zyngier wrote:
> On 23/07/2019 13:25, Auger Eric wrote:
>> Hi Marc,
>>
>> On 7/22/19 12:54 PM, Marc Zyngier wrote:
>>> Hi Eric,
>>>
>>> On 01/07/2019 13:38, Auger Eric wrote:
Hi Marc,
On 6/11/19 7:03 PM, Marc Zyngier wrote:
> The LPI
Hi Marc,
On 6/11/19 7:03 PM, Marc Zyngier wrote:
> Add the basic data structure that expresses an MSI to LPI
> translation as well as the allocation/release hooks.
>
> THe size of the cache is arbitrarily defined as 4*nr_vcpus.
The
>
> Signed-off-by: Marc Zyngier
> ---
> include/kvm/arm_vgic.h
On 23/07/2019 13:25, Auger Eric wrote:
> Hi Marc,
>
> On 7/22/19 12:54 PM, Marc Zyngier wrote:
>> Hi Eric,
>>
>> On 01/07/2019 13:38, Auger Eric wrote:
>>> Hi Marc,
>>>
>>> On 6/11/19 7:03 PM, Marc Zyngier wrote:
The LPI translation cache needs to be discarded when an ITS command
may
Hi Marc,
On 6/11/19 7:03 PM, Marc Zyngier wrote:
> There's a number of cases where we need to invalidate the caching
> of translations, so let's add basic support for that.
>
> Signed-off-by: Marc Zyngier
Reviewed-by: Eric Auger
Thanks
Eric
> ---
> virt/kvm/arm/vgic/vgic-its.c | 23
Hi Marc,
On 7/22/19 12:54 PM, Marc Zyngier wrote:
> Hi Eric,
>
> On 01/07/2019 13:38, Auger Eric wrote:
>> Hi Marc,
>>
>> On 6/11/19 7:03 PM, Marc Zyngier wrote:
>>> The LPI translation cache needs to be discarded when an ITS command
>>> may affect the translation of an LPI (DISCARD and MAPD
On Tue, 11 Jun 2019 18:03:27 +0100
Marc Zyngier wrote:
Hi,
> It recently became apparent[1] that our LPI injection path is not as
> efficient as it could be when injecting interrupts coming from a VFIO
> assigned device.
>
> Although the proposed patch wasn't 100% correct, it outlined at least
On 2019-07-23 09:17, Julien Thierry wrote:
Hi Zenghui,
On 18/07/2019 09:15, Zenghui Yu wrote:
We use "pmc->idx" and the "chained" bitmap to determine if the pmc
is
chained, in kvm_pmu_pmc_is_chained(). But idx might be
uninitialized
(and random) when we doing this decision, through a
Hi Zenghui,
On 18/07/2019 09:15, Zenghui Yu wrote:
> We use "pmc->idx" and the "chained" bitmap to determine if the pmc is
> chained, in kvm_pmu_pmc_is_chained(). But idx might be uninitialized
> (and random) when we doing this decision, through a KVM_ARM_VCPU_INIT
> ioctl ->
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