Hi Drew,
On 5/18/2020 3:05 PM, Andrew Jones wrote:
On Sun, May 17, 2020 at 06:09:00PM +0800, Jingyi Wang wrote:
Triggers PPIs by setting up a 10msec timer and test the latency.
For this test can be time consuming, we add time limit for loop_test
to make sure each test should be done in a
On Thu, 14 May 2020 10:45:53 +0100, Andre Przywara wrote:
> On arm and arm64 we expose the Motorola RTC emulation to the guest,
> but never advertised this in the device tree.
>
> EDK-2 seems to rely on this device, but on its hardcoded address. To
> make this more future-proof, add a DT node
This abstraction was introduced to hide the difference between arm and
arm64 but, with the former no longer supported, this abstraction can be
removed and the canonical kernel API used directly instead.
Signed-off-by: Andrew Scull
CC: Marc Zyngier
CC: James Morse
CC: Suzuki K Poulose
---
On 05/19/2020 10:40 AM, Anshuman Khandual wrote:
This adds basic building blocks required for ID_MMFR5 CPU register which
provides information about the implemented memory model and memory
management support in AArch32 state. This is added per ARM DDI 0487F.a
specification.
Cc: Catalin Marinas
On Wed, Apr 22, 2020 at 01:00:50PM +0100, Marc Zyngier wrote:
> We currently assume that an exception is delivered to EL1, always.
> Once we emulate EL2, this no longer will be the case. To prepare
> for this, add a target_mode parameter.
>
> While we're at it, merge the computing of the target
On 05/19/2020 10:40 AM, Anshuman Khandual wrote:
This adds basic building blocks required for ID_DFR1 CPU register which
provides top level information about the debug system in AArch32 state.
This is added per ARM DDI 0487F.a specification.
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Marc
Hi all,
Is there any plan for enabling SMMU HTTU?
I have seen the patch locates in the SVA series patch, which adds
support for HTTU:
https://www.spinics.net/lists/arm-kernel/msg798694.html
HTTU reduces the number of access faults on SMMU fault queue
(permission faults also benifit from
This adds basic building blocks required for ID_PFR2 CPU register which
provides information about the AArch32 programmers model which must be
interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added
per ARM DDI 0487F.a specification.
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Marc
This adds basic building blocks required for ID_MMFR5 CPU register which
provides information about the implemented memory model and memory
management support in AArch32 state. This is added per ARM DDI 0487F.a
specification.
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Marc Zyngier
Cc: Mark
This series is primarily motivated from an adhoc list from Mark Rutland
during our previous ID_ISAR6 discussion [1]. The current proposal also
accommodates some more suggestions from Will and Suzuki.
This series adds missing 32 bit system registers (ID_PFR2, ID_DFR1 and
ID_MMFR5), adds missing
This adds basic building blocks required for ID_DFR1 CPU register which
provides top level information about the debug system in AArch32 state.
This is added per ARM DDI 0487F.a specification.
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: James Morse
Cc: Suzuki K
On Mon, May 18, 2020 at 1:50 AM Anastassios Nanos
wrote:
>
> On Mon, May 18, 2020 at 10:50 AM Marc Zyngier wrote:
> >
> > On 2020-05-18 07:58, Anastassios Nanos wrote:
> > > To spawn KVM-enabled Virtual Machines on Linux systems, one has to use
> > > QEMU, or some other kind of VM monitor in
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