Hi Sean,
On 10/21/22 6:42 AM, Sean Christopherson wrote:
On Tue, Oct 11, 2022, Gavin Shan wrote:
This adds KVM_REQ_RING_SOFT_FULL, which is raised when the dirty
"This" is basically "This patch", which is generally frowned upon. Just state
what changes are being made.
Ok.
ring of the
Hi Oliver,
On Thu, Oct 20, 2022 at 12:08 PM Oliver Upton wrote:
>
> On Wed, Oct 19, 2022 at 10:41:54PM -0700, Reiji Watanabe wrote:
> > Use FIELD_GET() macro to extract ID register fields for existing
> > aarch64 selftests code. No functional change intended.
> >
> > Signed-off-by: Reiji
On Tue, Oct 11, 2022, Gavin Shan wrote:
> Some architectures (such as arm64) need to dirty memory outside of the
> context of a vCPU. Of course, this simply doesn't fit with the UAPI of
> KVM's per-vCPU dirty ring.
What is the point of using the dirty ring in this case? KVM still burns a pile
of
On Tue, Oct 11, 2022, Gavin Shan wrote:
> This adds KVM_REQ_RING_SOFT_FULL, which is raised when the dirty
"This" is basically "This patch", which is generally frowned upon. Just state
what changes are being made.
> ring of the specific VCPU becomes softly full in kvm_dirty_ring_push().
> The
On Thu, Oct 20, 2022 at 9:33 AM Mark Brown wrote:
>
> On Wed, Oct 19, 2022 at 02:11:26PM -0500, Rob Herring wrote:
> > Convert all the SPE register defines to automatic generation. No
> > functional changes.
> >
> > New registers and fields for SPEv1.2 are added with the conversion.
> >
> > Some
On Wed, Oct 19, 2022 at 10:41:58PM -0700, Reiji Watanabe wrote:
> Currently, debug-exceptions test unnecessarily tracks some test stages
> using GUEST_SYNC(). The code for it needs to be updated as test cases
> are added or removed. Stop doing the unnecessary stage tracking,
> as they are not so
On Wed, Oct 19, 2022 at 10:41:56PM -0700, Reiji Watanabe wrote:
> Remove the hard-coded {break,watch}point #0 from the guest_code() in
> debug-exceptions to allow {break,watch}point number to be specified.
> Change reset_debug_state() to zeroing all dbg{b,w}{c,v}r_el0 registers
> so that
On Wed, Oct 19, 2022 at 10:41:54PM -0700, Reiji Watanabe wrote:
> Use FIELD_GET() macro to extract ID register fields for existing
> aarch64 selftests code. No functional change intended.
>
> Signed-off-by: Reiji Watanabe
> ---
> tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c | 3 ++-
>
On Wed, Oct 19, 2022 at 06:20:32AM +0800, Gavin Shan wrote:
> Hi Peter,
>
> On 10/19/22 12:07 AM, Peter Xu wrote:
> > On Tue, Oct 11, 2022 at 02:14:42PM +0800, Gavin Shan wrote:
[...]
> > IMHO it'll be great to start with something like below to describe the
> > userspace's responsibility to
On Wed, Oct 19, 2022 at 02:11:26PM -0500, Rob Herring wrote:
> Convert all the SPE register defines to automatic generation. No
> functional changes.
>
> New registers and fields for SPEv1.2 are added with the conversion.
>
> Some of the PMBSR MSS field defines are kept as the automatic
Paolo,
Here's a couple of additional fixes for 6.1. The ITS one is pretty
annoying as it prevents a VM from being restored if it has a
convoluted device topology. Definitely a stable candidate.
Note that I can't see that you have pulled the first set of fixes
which I sent last week[1]. In order
When using hVHE, we end-up with two TTBRs at EL2. That's great,
but we're not quite ready for this just yet.
Disable TTBR1_EL2 by setting TCR_EL2.EPD1 so that we only
translate via TTBR0_EL2.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/arm.c | 8 +++-
1 file changed, 7 insertions(+), 1
Obviously, in order to be able to use VHE whilst at EL2, we need
to set HCR_EL2.E2H. Do so when ARM64_KVM_HVHE is set.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/arm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index
Just like we repainted the early arm64 code, we need to update
the CPTR_EL2 accesses that are taking place in the nVHE code
when hVHE is used, making them look as if they were CPACR_EL1
accesses. Just like the VHE code.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_arm.h|
Just like the rest of the timer code, we need to shift the enable
bits around when HCR_EL2.E2H is set, which is the case in hVHE mode.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/nvhe/timer-sr.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git
Add the arm64_sw.hvhe=1 option to force the use of the hVHE mode
in the hypervisor code only.
This enables the hVHE mode of operation when using KVM on VHE
hardware.
Signed-off-by: Marc Zyngier
---
arch/arm64/kernel/idreg-override.c | 11 +++
1 file changed, 11 insertions(+)
diff
El2 stage-1 page-table format is subtly (and annoyingly) different
when HCR_EL2.E2H is set.
Take the ARM64_KVM_HVHE configuration into account when setting
the AP bits.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/pgtable.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
As our M1 friend doesn't have a GIC, it relies on a special hack
to deal with masking the guest timers, in the form of an IMPDEF
system register.
Unfortunately, this sysreg is EL2-only, which means that the kernel
cannot mask the interrupts itself, but has to kindly ask EL2 to do
it. Yes, this is
Also make sure HCR_EL2.E2H is set when switching HCR_EL2 in guest
context.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_emulate.h | 2 +-
arch/arm64/kvm/hyp/nvhe/pkvm.c | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git
Disabling KASLR from the command line is implemented as a feature
override. Repaint it slightly so that it can further be used as
more generic infrastructure for SW override purposes.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/cpufeature.h | 4
arch/arm64/kernel/cpufeature.c
KVM (on ARMv8.0) and pKVM (on all revisions of the architecture) uses
the split hypervisor model that makes the EL2 code more or less
standalone. For this, we totally ignore the VHE mode and stick with
the good old v8.0 EL2 setup.
This is all good, but means that the EL2 code is limited in what
Expose a capability keying the hVHE feature as well as a new
predicate testing it. Nothing is so far using it, and nothing
is enabling it yet.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/cpufeature.h | 1 +
arch/arm64/include/asm/virt.h | 8
We can now start with the fun stuff: if we enable VHE *only* for
the hypervisor, we need to generate the VHE instructions when
accessing the system registers.
For this, reporpose the alternative sequence to be keyed off
ARM64_KVM_HVHE in the nVHE hypervisor code, and only there.
Signed-off-by:
When HCR_EL2.E2H is set, the CPTR_EL2 register takes the CPACR_EL1
format. Yes, this is good fun.
Hack the bits of startup code that assume E2H=0 while setting up
CPTR_EL2 to make them grok the CPTR_EL1 format.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/el2_setup.h | 11 +--
In the VHE hypervisor code, we should be using the remapped VHE
accessors, no ifs, no buts. No need to generate any alternative.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_hyp.h | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git
Using is_kernel_in_hyp_mode() in hypervisor code is a pretty bad
mistake. This helper only checks for CurrentEL being EL2, which
is always true.
Make the link fail if using the helper in hypervisor context
by referencing a non-existent function. Whilst we're at it,
flag the helper as
To initialise the timer access from EL2 when HCR_EL2.E2H is set,
we must make use the CNTHCTL_EL2 formap used is appropriate.
This amounts to shifting the timer/counter enable bits by 10
to the left.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/el2_setup.h | 5 +
1 file changed,
If the OVERRIDE_HVHE SW override is set (as a precursor of
the KVM_HVHE capability), do not enable VHE for the kernel
and drop to EL1 as if VHE was either disabled or unavailable.
Further changes will enable VHE at EL2 only, with the kernel
still running at EL1.
Signed-off-by: Marc Zyngier
---
For VHE-specific hypervisor code, kern_hyp_va() is a NOP.
Actually, it is a whole range of NOPs. It'd be much better if
this code simply didn't exist. Let's just do that.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_mmu.h | 4
1 file changed, 4 insertions(+)
diff --git
On Wed, Oct 19, 2022 at 11:32:36PM +, Sean Christopherson wrote:
> On Fri, Oct 07, 2022, Oliver Upton wrote:
> > @@ -1534,7 +1517,7 @@ bool kvm_set_spte_gfn(struct kvm *kvm, struct
> > kvm_gfn_range *range)
> > */
> > kvm_pgtable_stage2_map(kvm->arch.mmu.pgt, range->start <<
On Wed, Oct 19, 2022 at 11:29:56PM +, Sean Christopherson wrote:
> On Fri, Oct 07, 2022, Oliver Upton wrote:
> > The use of RCU is necessary to safely change the stage-2 page tables in
> > parallel. Acquire and release the RCU read lock when traversing the page
> > tables.
> >
> > Use the
On Wed, Oct 19, 2022 at 11:17:43PM +, Sean Christopherson wrote:
> On Fri, Oct 07, 2022, Oliver Upton wrote:
> > Use an opaque type for pteps and require visitors explicitly dereference
> > the pointer before using. Protecting page table memory with RCU requires
> > that KVM dereferences
On 10/20/22 4:18 AM, Maciej S. Szmigiero wrote:
On 19.10.2022 02:26, Gavin Shan wrote:
On 10/18/22 11:56 PM, Maciej S. Szmigiero wrote:
On 18.10.2022 02:51, Gavin Shan wrote:
On 10/18/22 8:46 AM, Gavin Shan wrote:
On 10/18/22 5:31 AM, Maciej S. Szmigiero wrote:
On 14.10.2022 09:19, Gavin
The memory area in each slot should be aligned to host page size.
Otherwise, the test will fail. For example, the following command
fails with the following messages with 64KB-page-size-host and
4KB-pae-size-guest. It's not user friendly to abort the test.
Lets do something to report the optimal
The addresses and sizes passed to vm_userspace_mem_region_add() and
madvise() should be aligned to host page size, which can be 64KB on
aarch64. So it's wrong by passing additional fixed 4KB memory area
to various tests.
Fix it by passing additional fixed 64KB memory area to various tests.
We
The test case is obviously broken on aarch64 because non-4KB guest
page size is supported. The guest page size on aarch64 could be 4KB,
16KB or 64KB.
This supports variable guest page size, mostly for aarch64.
- The host determines the guest page size when virtual machine is
created. The
prepare_vm() is called in every iteration and run. The allowed memory
slots (KVM_CAP_NR_MEMSLOTS) are probed for multiple times. It's not
free and unnecessary.
Move the probing logic for the allowed memory slots to parse_args()
for once, which is upper layer of prepare_vm().
No functional change
There are two loops in prepare_vm(), which have different conditions.
'slot' is treated as meory slot index in the first loop, but index of
the host virtual address array in the second loop. It makes it a bit
hard to understand the code.
Change the usage of 'slot' in the second loop, to treat it
In prepare_vm(), 'data->nslots' is assigned with 'max_mem_slots - 1'
at the beginning, meaning they are interchangeable.
Use 'data->nslots' isntead of 'max_mem_slots - 1'. With this, it
becomes easier to move the logic of probing number of slots into
upper layer in subsequent patches.
No
kvm/selftests/memslots_perf_test doesn't work with 64KB-page-size-host
and 4KB-page-size-guest on aarch64. In the implementation, the host and
guest page size have been hardcoded to 4KB. It's ovbiously not working
on aarch64 which supports 4KB, 16KB, 64KB individually on host and guest.
This
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