Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On 02/01/2017 01:38 PM, Catalin Marinas wrote: > On Wed, Feb 01, 2017 at 06:34:01PM +, Will Deacon wrote: >> On Wed, Feb 01, 2017 at 06:22:44PM +, Catalin Marinas wrote: >>> On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote: On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On 01/31/2017 12:56 PM, Marc Zyngier wrote: > On 31/01/17 17:48, Christopher Covington wrote: >> On 01/31/2017 07:37 AM, Mark Rutland wrote: >>> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: >>>> The Qualcomm Datacenter Technologies Falkor v

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On 01/31/2017 07:37 AM, Mark Rutland wrote: > On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: >> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries >> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum >&g

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

Hi Mark, On 01/30/2017 05:56 AM, Mark Rutland wrote: > Hi, > > On Fri, Jan 27, 2017 at 04:52:23PM -0500, Christopher Covington wrote: >> On 01/27/2017 09:38 AM, Mark Rutland wrote: >>> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: > >&g

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

Hi Mark, On 01/27/2017 09:38 AM, Mark Rutland wrote: > On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: >> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries >> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum

[PATCH v4 3/4] arm64: Use __tlbi() macros in KVM code

-by: Christopher Covington <c...@codeaurora.org> --- arch/arm64/kvm/hyp/tlb.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index 88e2f2b938f0..e8e7ba2bc11f 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++ b/arch/arm64/k

[PATCH v4 1/4] arm64: Define Falkor v1 CPU

From: Shanker Donthineni <shank...@codeaurora.org> Define the MIDR implementer and part number field values for the Qualcomm Datacenter Technologies Falkor processor version 1 in the usual manner. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> Signed-off-by: Christopher

[PATCH v4 2/4] arm64: Work around Falkor erratum 1003

ora.org> Signed-off-by: Christopher Covington <c...@codeaurora.org> --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 11 +++ arch/arm64/include/asm/assembler.h | 23 +++ arch/arm64/include/asm/cpucaps.h | 3

Re: [PATCH v3 3/5] arm64: Create and use __tlbi_dsb() macros

Hi Will, On 01/13/2017 11:12 AM, Will Deacon wrote: > On Fri, Jan 13, 2017 at 10:12:36AM -0500, Christopher Covington wrote: >> On 01/12/2017 11:58 AM, Will Deacon wrote: >>> On Wed, Jan 11, 2017 at 09:41:16AM -0500, Christopher Covington wrote: >>>> +#define __tlbi

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

Hi Catalin, On 01/11/2017 01:06 PM, Catalin Marinas wrote: > Some minor comments below, nothing fundamental (as long as you say the > new sequence doesn't have the speculative TLB load problem I mentioned > on a previous version). This workaround is documented as providing functional correctness

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On 01/12/2017 11:12 AM, Mark Rutland wrote: > On Thu, Jan 12, 2017 at 03:45:48PM +, Catalin Marinas wrote: >> On Wed, Jan 11, 2017 at 06:40:52PM +, Mark Rutland wrote: > >>> Likewise, I beleive we may need to modify cpu_set_reserved_ttbr0(). >> >> This may be fine if my assumptions about

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

Hi Mark, On 01/11/2017 01:45 PM, Mark Rutland wrote: > On Wed, Jan 11, 2017 at 12:40:42PM -0600, Timur Tabi wrote: >> On 01/11/2017 12:37 PM, Mark Rutland wrote: >>> The name, as it is, is perfectly descriptive. >>> >>> Let's not sacrifice legibility over a non-issue. >> >> I don't want to kick a

Re: [PATCH v3 3/5] arm64: Create and use __tlbi_dsb() macros

Hi Will, On 01/12/2017 11:58 AM, Will Deacon wrote: > Hi Christopher, > > On Wed, Jan 11, 2017 at 09:41:16AM -0500, Christopher Covington wrote: >> This refactoring will allow an errata workaround that repeats tlbi dsb >> sequences to only change one location. This is n

[PATCH v3 2/5] arm64: Work around Falkor erratum 1003

amp;0 ASID is not subject to this erratum because hardware is prohibited from performing translations from an out-of-context translation regime. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> Signed-off-by: Christopher Covington <c...@codeaurora.org> --- Documentation/arm64/s

[PATCH v3 5/5] arm64: Work around Falkor erratum 1009

During a TLB invalidate sequence targeting the inner shareable domain, Falkor may prematurely complete the DSB before all loads and stores using the old translation are observed; instruction fetches are not subject to the conditions of this erratum. Signed-off-by: Christopher Covington &l

[PATCH v3 4/5] arm64: Use __tlbi_dsb() macros in KVM code

. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arch/arm64/kvm/hyp/tlb.c | 29 +++-- 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index 88e2f2b..9669e4b 100644 --- a/arch/arm64/k

[PATCH v3 1/5] arm64: Define Falkor v1 CPU

From: Shanker Donthineni <shank...@codeaurora.org> Define the MIDR implementer and part number field values for the Qualcomm Datacenter Technologies Falkor processor version 1 in the usual manner. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> Signed-off-by: Christopher

[PATCH v3 3/5] arm64: Create and use __tlbi_dsb() macros

-off-by: Christopher Covington <c...@codeaurora.org> --- arch/arm64/include/asm/tlbflush.h | 104 +- 1 file changed, 69 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index deab523..f

Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

Hi Christoffer, On 01/04/2017 05:33 AM, Christoffer Dall wrote: > On Thu, Dec 29, 2016 at 05:43:32PM -0500, Christopher Covington wrote: >> From: Shanker Donthineni <shank...@codeaurora.org> >> >> On the Qualcomm Datacenter Technologies Falkor v1 CPU, memory accesses

Re: [PATCH v2 4/5] arm64: Use __tlbi_dsb() macros in KVM code

On 01/03/2017 10:57 AM, Mark Rutland wrote: > On Thu, Dec 29, 2016 at 05:43:34PM -0500, Christopher Covington wrote: >> Refactor the KVM code to use the newly introduced __tlbi_dsb macros, which >> will allow an errata workaround that repeats tlbi dsb sequences to only >>

Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

On 01/03/2017 10:55 AM, Mark Rutland wrote: > Hi, > > On Thu, Dec 29, 2016 at 05:43:32PM -0500, Christopher Covington wrote: >> +config QCOM_FALKOR_E1003_RESERVED_ASID >> +int >> +default 1 >> +depends on QCOM_FALKOR_ERRATUM_1003 >> + > >

Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

On 12/29/2016 06:08 PM, Timur Tabi wrote: > On 12/29/2016 04:43 PM, Christopher Covington wrote: >> +config QCOM_FALKOR_E1003_RESERVED_ASID >> +int >> +default 1 >> +depends on QCOM_FALKOR_ERRATUM_1003 > > Also, since this can't be changed via the m

Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003

On 12/29/2016 06:02 PM, Timur Tabi wrote: > On 12/29/2016 04:43 PM, Christopher Covington wrote: >> -| Implementor| Component | Erratum ID | Kconfig >>| >> -++-+-+---

[PATCH v2 1/5] arm64: Define Falkor v1 CPU

From: Shanker Donthineni <shank...@codeaurora.org> Define the MIDR implementer and part number field values for the Qualcomm Datacenter Technologies Falkor processor version 1 in the usual manner. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> Signed-off-by: Christopher

[PATCH v2 4/5] arm64: Use __tlbi_dsb() macros in KVM code

. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arch/arm64/kvm/hyp/tlb.c | 17 ++--- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index 88e2f2b..66e3f72 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++

[PATCH v2 2/5] arm64: Work around Falkor erratum 1003

<shank...@codeaurora.org> Signed-off-by: Christopher Covington <c...@codeaurora.org> --- Documentation/arm64/silicon-errata.txt | 43 +- arch/arm64/Kconfig | 16 + arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/k

[PATCH v2 5/5] arm64: Work around Falkor erratum 1009

During a TLB invalidate sequence targeting the inner shareable domain, Falkor may prematurely complete the DSB before all loads and stores using the old translation are observed; instruction fetches are not subject to the conditions of this erratum. Signed-off-by: Christopher Covington &l

[PATCH v2 3/5] arm64: Create and use __tlbi_dsb() macros

-by: Christopher Covington <c...@codeaurora.org> --- arch/arm64/include/asm/tlbflush.h | 104 +- 1 file changed, 69 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index deab523..f28813c

Re: [Qemu-devel] [PATCH kvm-unit-tests v8 03/10] arm/arm64: add some delay routines

On 12/09/2016 07:15 AM, Andrew Jones wrote: > On Fri, Dec 09, 2016 at 11:41:06AM +, Andre Przywara wrote: >> Hi, >> >> On 08/12/16 17:50, Andrew Jones wrote: >>> Allow a thread to wait some specified amount of time. Can >>> specify in cycles, usecs, and msecs. >>> +++ b/lib/arm/asm/delay.h

Re: [PATCH kvm-unit-tests v2 2/2] arm/pmu: don't run tcg tests

On 12/08/2016 12:05 PM, Andrew Jones wrote: > The TCG PMU is barely implemented for ARM and not at all implemented > for AArch64. Let's not bother running the TCG-only tests yet. We'll > likely move them to a new TCG-only unittests.cfg at some point before > re-enabling them too. ID_AA64DFR0_EL1

[PATCH] arm64: Work around Falkor erratum 1009

itions of this erratum. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arch/arm64/Kconfig| 10 + arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/a

Re: [kvm-unit-tests PATCH v13 4/4] arm: pmu: Add CPI checking

On 12/01/2016 03:27 PM, Andre Przywara wrote: > Hi, > > On 01/12/16 05:16, Wei Huang wrote: >> From: Christopher Covington <c...@codeaurora.org> >> >> Calculate the numbers of cycles per instruction (CPI) implied by ARM >> PMU cycle counter values. The c

Re: [kvm-unit-tests PATCH v10 3/3] arm: pmu: Add CPI checking

Hi Wei, On 11/21/2016 03:24 PM, Wei Huang wrote: > From: Christopher Covington <c...@codeaurora.org> I really appreciate your work on these patches. If for any or all of these you have more lines added/modified than me (or using any other better metric), please make sure to change t

Re: [kvm-unit-tests PATCH] arm/arm64: introduce is_aarch32

On 11/17/2016 11:59 AM, Andrew Jones wrote: > On Wed, Nov 16, 2016 at 05:02:59PM -0500, Christopher Covington wrote: >> On 11/16/2016 12:46 PM, Marc Zyngier wrote: >>> On 16/11/16 14:38, Andrew Jones wrote: >>>> ARMv7-A isn't exactly the same as ARMv8-A32 (AArch32).

Re: [kvm-unit-tests PATCH] arm/arm64: introduce is_aarch32

On 11/16/2016 12:46 PM, Marc Zyngier wrote: > On 16/11/16 14:38, Andrew Jones wrote: >> ARMv7-A isn't exactly the same as ARMv8-A32 (AArch32). This >> function allows unit tests to make the distinction. > > Hi Drew, > > Overall, having to find out about the architecture is a bad idea most of >

Re: [Qemu-devel] [kvm-unit-tests PATCH v8 2/3] arm: pmu: Check cycle count increases

On 11/16/2016 11:25 AM, Andrew Jones wrote: > On Wed, Nov 16, 2016 at 11:08:42AM -0500, Christopher Covington wrote: >> On 11/16/2016 08:01 AM, Andrew Jones wrote: >>> On Tue, Nov 15, 2016 at 04:50:53PM -0600, Wei Huang wrote: >>>> >>>> >>>&g

Re: [Qemu-devel] [kvm-unit-tests PATCH v8 2/3] arm: pmu: Check cycle count increases

On 11/16/2016 08:01 AM, Andrew Jones wrote: > On Tue, Nov 15, 2016 at 04:50:53PM -0600, Wei Huang wrote: >> >> >> On 11/14/2016 09:12 AM, Christopher Covington wrote: >>> Hi Drew, Wei, >>> >>> On 11/14/2016 05:05 AM, Andrew Jones wrote: >>

Re: [Qemu-devel] [kvm-unit-tests PATCH v8 2/3] arm: pmu: Check cycle count increases

Hi Drew, Wei, On 11/14/2016 05:05 AM, Andrew Jones wrote: > On Fri, Nov 11, 2016 at 01:55:49PM -0600, Wei Huang wrote: >> >> >> On 11/11/2016 01:43 AM, Andrew Jones wrote: >>> On Tue, Nov 08, 2016 at 12:17:14PM -0600, Wei Huang wrote: >>>> From:

Re: Intermittent guest kernel crashes with v4.5-rc6.

roblem. >> I suspected something like that. But it is such a massive hammer that it >> will hide any sort of subtle bug (HW *and* SW). >> >>>> Another thing worth looking at is what happened just before we decided >>>> to get back into the guest. Or to put

Re: [Qemu-devel] [kvm-unit-tests PATCHv5 3/3] arm: pmu: Add CPI checking

On 11/10/2015 09:05 PM, Andrew Jones wrote: > On Mon, Nov 02, 2015 at 09:58:14AM -0600, Andrew Jones wrote: >> On Fri, Oct 30, 2015 at 03:32:43PM -0400, Christopher Covington wrote: >>> Hi Drew, >>> >>> On 10/30/2015 09:00 AM, Andrew Jones wrote: >>&

Re: [PATCH] KVM/arm: kernel low level debug support for ARM32 virtual platforms

e, Nov 03, 2015 at 09:44:52AM -0800, Mario Smarduch wrote: >>>>> On 11/3/2015 8:33 AM, Christopher Covington wrote: >>>>>> On 11/02/2015 06:51 PM, Mario Smarduch wrote: >>>>>>>this is a re-post from couple weeks ago, please take time

Re: KVM/ARM: trap every load /store instruction

e-mem=yes` might be a starting point) than a bunch of hypervisor traps. Christopher Covington -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project _

Re: [PATCH v4 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register

On 10/30/2015 02:21 AM, Shannon Zhao wrote: > From: Shannon Zhao > > Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for > its reset handler. As it doesn't need to deal with the acsessing action Nit: accessing > specially, it uses default case to

Re: [PATCH v4 17/21] KVM: ARM64: Add helper to handle PMCR register bits

On 10/30/2015 02:21 AM, Shannon Zhao wrote: > From: Shannon Zhao > > According to ARMv8 spec, when writing 1 to PMCR.E, all counters are > enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are > disabled. When writing 1 to PMCR.P, reset all event counters,

[kvm-unit-tests PATCHv5 3/3] arm: pmu: Add CPI checking

allow for different tests to be run on TCG versus KVM. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c | 103 +- 1 file changed, 102 insertions(+), 1 deletion(-) diff --git a/arm/pmu.c b/arm/pmu.c index 4

[kvm-unit-tests PATCHv5 2/3] arm: pmu: Check cycle count increases

Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, even for the smallest delta of two subsequent reads. Signed-off-by: Christopher Covington <c...@codeaurora.org> Reviewed-by: Andrew Jones <drjo...@redhat.com> --- ar

[kvm-unit-tests PATCHv5 1/3] arm: Add PMU test

Beginning with a simple sanity check of the control register, add a unit test for the ARM Performance Monitors Unit (PMU). Signed-off-by: Christopher Covington <c...@codeaurora.org> Reviewed-by: Andrew Jones <drjo...@redhat.com> --- arm/pmu.c

[kvm-unit-tests PATCHv6] ARM PMU tests

inline assembly justification comments uniform. * Check argc properly. Thanks, Christopher Covington ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

[kvm-unit-tests PATCHv5 3/3] arm: pmu: Add CPI checking

allow for different tests to be run on TCG versus KVM. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c | 105 +- 1 file changed, 104 insertions(+), 1 deletion(-) diff --git a/arm/pmu.c b/arm/pmu.c index c

[kvm-unit-tests PATCHv5 1/3] arm: Add PMU test

Beginning with a simple sanity check of the control register, add a unit test for the ARM Performance Monitors Unit (PMU). Signed-off-by: Christopher Covington <c...@codeaurora.org> Reviewed-by: Andrew Jones <drjo...@redhat.com> --- arm/pmu.c

[kvm-unit-tests PATCHv5 2/3] arm: pmu: Check cycle count increases

Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, even for the smallest delta of two subsequent reads. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c | 60 1 file changed, 60 inse

Re: [Qemu-devel] [kvm-unit-tests PATCHv5 2/3] arm: pmu: Check cycle count increases

On 10/26/2015 11:58 AM, Andrew Jones wrote: > On Mon, Oct 26, 2015 at 11:38:49AM -0400, Christopher Covington wrote: >> Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, >> even for the smallest delta of two subsequent reads. >> >> Signed-off-b

Re: [Qemu-devel] [kvm-unit-tests PATCHv4 3/3] arm: pmu: Add CPI checking

supported by the in-line assembly code. >> The > > Not all odd counts, right? But rather all multiples of 3? IIUC this is because > the loop is two instructions (sub + branch), and then the clearing of the pmcr > register counts as the 3rd? Clearing the PMCR doesn't happen

Re: [PATCH v3 00/20] KVM: ARM64: Add guest PMU support

289068 seconds time elapsed >> ( +- 0.00% ) >> > > Thanks for V3. One suggestion is to run more perf stress tests, such as > "perf test". So we know the corner cases are covered as much as possible. I'd also recommend

[kvm-unit-tests PATCHv4 2/3] arm: pmu: Check cycle count increases

Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, even for the smallest delta of two subsequent reads. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c | 54 ++ 1 file changed, 54 insertions(+)

[kvm-unit-tests PATCHv4 1/3] arm: Add PMU test

Beginning with a simple sanity check of the control register, add a unit test for the ARM Performance Monitors Unit (PMU). Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c| 82 arm/unittes

[kvm-unit-tests PATCHv4] ARM PMU tests

Changes from v3 in response to Drew's suggestions: * Improved pmu_data / PMCR fields and usage * Straightened out awkward conditionals * Added 32-bit support * Styling enhancements * Deferred -icount testing to later patch ___ kvmarm mailing list

[kvm-unit-tests PATCHv3] ARM PMU tests

Changes from v2: * Explicit test for monotonically increasing cycle count * Tests now pass or fail * Tests broken into functions * Tests/functions broken into separate patches in series * Style improvements as suggested by Wei Huang and Linux checkpatch.pl * Spelling and comment improvements

[kvm-unit-tests PATCHv3 1/3] arm: Add PMU test

Beginning with a simple sanity check of the control register, add a unit test for the ARM Performance Monitors Unit (PMU). Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c | 66 + arm/unittests.cfg

[kvm-unit-tests PATCHv3 3/3] arm: pmu: Add CPI checking

Check the numbers of cycles per instruction (CPI) implied by ARM PMU cycle counter values. Check that in -icount mode these strictly match the specified rate. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c

[kvm-unit-tests PATCHv2] arm: Add PMU test

when using -icount. Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c | 89 + arm/unittests.cfg | 11 ++ config/config-arm64.mak | 4 ++- 3 files changed, 103 insertions(+), 1 deletion(-) creat

[PATCHv2] arm: Fail on unknown subtest

Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/selftest.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arm/selftest.c b/arm/selftest.c index fc9ec60..f4a5030 100644 --- a/arm/selftest.c +++ b/arm/selftest.c @@ -376,6 +376,9 @@ int main(int argc, char

[PATCH] arm: Add PMU test

Beginning with just a read of the control register, add plumbing for testing the ARM Performance Monitors Unit (PMU). Signed-off-by: Christopher Covington <c...@codeaurora.org> --- arm/pmu.c| 31 +++ arm/unittests.cfg| 5 +