On Thu, 18 Feb 2021 at 06:10, Marc Zyngier wrote:
>
> On Thu, 04 Feb 2021 07:51:37 +0000,
> Haibo Xu wrote:
> >
> > Kindly ping!
> >
> > On Thu, 21 Jan 2021 at 11:03, Haibo Xu wrote:
> > >
> > > Re-send in case the previous email was bloc
Kindly ping!
On Thu, 21 Jan 2021 at 11:03, Haibo Xu wrote:
>
> Re-send in case the previous email was blocked for the inlined hyper-link.
>
> Hi Marc,
>
> I have tried to enable the NV support in Qemu, and now I can
> successfully boot a L2 guest
> in Qemu KVM mode.
>
Re-send in case the previous email was blocked for the inlined hyper-link.
Hi Marc,
I have tried to enable the NV support in Qemu, and now I can
successfully boot a L2 guest
in Qemu KVM mode.
This patch series looks good from the Qemu side except for two minor
requirements:
(1) Qemu will check
On Fri, 11 Dec 2020 at 00:04, Marc Zyngier wrote:
>
> Add Stage-2 mmu data structures for virtual EL2 and for nested guests.
> We don't yet populate shadow Stage-2 page tables, but we now have a
> framework for getting to a shadow Stage-2 pgd.
>
> We allocate twice the number of vcpus as Stage-2
On Fri, 11 Dec 2020 at 00:04, Marc Zyngier wrote:
>
> If running a NV guest on an ARMv8.4-NV capable system, let's
> allocate an additional page that will be used by the hypervisor
> to fulfill system register accesses.
>
> Signed-off-by: Marc Zyngier
> ---
> arch/arm64/include/asm/kvm_host.h |
On Fri, 11 Dec 2020 at 00:00, Marc Zyngier wrote:
>
> This is a rework of the NV series that I posted 10 months ago[1], as a
> lot of the KVM code has changed since, and the series apply anymore
> (not that anybody really cares as the the HW is, as usual, made of
> unobtainium...).
>
> From the
On Mon, 11 Jan 2021 at 16:59, Marc Zyngier wrote:
>
> Hi Haibo,
>
> On 2021-01-11 07:20, Haibo Xu wrote:
> > On Fri, 11 Dec 2020 at 00:00, Marc Zyngier wrote:
> >>
> >> This is a rework of the NV series that I posted 10 months ago[1], as a
> &
On Wed, 16 Dec 2020 at 18:23, Steven Price wrote:
>
> On 16/12/2020 07:31, Haibo Xu wrote:
> [...]
> > Hi Steve,
>
> Hi Haibo
>
> > I have finished verifying the POC on a FVP setup, and the MTE test case can
> > be migrated from one VM to another succe
On Mon, 7 Dec 2020 at 22:48, Steven Price wrote:
>
> On 04/12/2020 08:25, Haibo Xu wrote:
> > On Fri, 20 Nov 2020 at 17:51, Steven Price wrote:
> >>
> >> On 19/11/2020 19:11, Marc Zyngier wrote:
> >>> On 2020-11-19 18:42, Andrew Jones wrote:
> >>
On Tue, 8 Dec 2020 at 18:01, Marc Zyngier wrote:
>
> On 2020-12-08 09:51, Haibo Xu wrote:
> > On Mon, 7 Dec 2020 at 22:48, Steven Price wrote:
> >>
>
> [...]
>
> >> Sounds like you are making good progress - thanks for the update. Have
> >> you th
On Tue, 8 Dec 2020 at 00:44, Dr. David Alan Gilbert wrote:
>
> * Steven Price (steven.pr...@arm.com) wrote:
> > On 07/12/2020 15:27, Peter Maydell wrote:
> > > On Mon, 7 Dec 2020 at 14:48, Steven Price wrote:
> > > > Sounds like you are making good progress - thanks for the update. Have
> > > >
On Mon, 7 Dec 2020 at 22:48, Steven Price wrote:
>
> On 04/12/2020 08:25, Haibo Xu wrote:
> > On Fri, 20 Nov 2020 at 17:51, Steven Price wrote:
> >>
> >> On 19/11/2020 19:11, Marc Zyngier wrote:
> >>> On 2020-11-19 18:42, Andrew Jones wrote:
> >>
On Fri, 20 Nov 2020 at 17:51, Steven Price wrote:
>
> On 19/11/2020 19:11, Marc Zyngier wrote:
> > On 2020-11-19 18:42, Andrew Jones wrote:
> >> On Thu, Nov 19, 2020 at 03:45:40PM +, Peter Maydell wrote:
> >>> On Thu, 19 Nov 2020 at 15:39, Steven Price wrote:
> >>> > This series adds support
On Wed, 28 Oct 2020 at 01:26, Alexandru Elisei wrote:
>
> Stage 2 faults triggered by the profiling buffer attempting to write to
> memory are reported by the SPE hardware by asserting a buffer management
> event interrupt. Interrupts are by their nature asynchronous, which means
> that the guest
On Wed, 28 Oct 2020 at 01:26, Alexandru Elisei wrote:
>
> user_mem_abort() is already a long and complex function, let's make it
> slightly easier to understand by abstracting the algorithm for choosing the
> stage 2 IPA entry size into its own function.
>
> This also makes it possible to reuse
On Wed, 28 Oct 2020 at 01:26, Alexandru Elisei wrote:
>
> From: Sudeep Holla
>
> To configure the virtual SPE buffer management interrupt number, we use a
> VCPU kvm_device ioctl, encapsulating the KVM_ARM_VCPU_SPE_IRQ attribute
> within the KVM_ARM_VCPU_SPE_CTRL group.
>
> After configuring the
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