Re: Migration with directly assigned devices is possible?

On Tue, Apr 24, 2018 at 1:13 PM, Paolo Bonzini <pbonz...@redhat.com> wrote: > On 24/04/2018 16:56, Jintack Lim wrote: >> Hi, >> >> I wonder if we can do migration with directly assigned devices (i.e. >> pass-through devices)? I looked at the KVM migration page[1],

Migration with directly assigned devices is possible?

Hi, I wonder if we can do migration with directly assigned devices (i.e. pass-through devices)? I looked at the KVM migration page[1], but couldn't find information. Can somebody let me now if it's possible or point me the related documents? Thanks, Jintack [1]

Re: [PATCH] KVM: arm/arm64: Don't enable/disable physical timer access on VHE

register format is > different when HCR_EL2.E2H is set. > > The CNTHCTL_EL2 is initialized when CPUs become online in > kvm_timer_init_vhe() and we don't have to call these functions on VHE > systems, which also allows us to inline the non-VHE functionality. > > Reported-by: Jintack Li

Re: [PATCH v4 14/20] KVM: arm/arm64: Avoid timer save/restore in vcpu entry/exit

On Mon, Nov 20, 2017 at 6:15 AM, Christoffer Dall <cd...@linaro.org> wrote: > On Thu, Nov 16, 2017 at 03:30:39PM -0500, Jintack Lim wrote: >> Hi Christoffer, >> >> On Fri, Oct 20, 2017 at 7:49 AM, Christoffer Dall >> <christoffer.d...@linaro.org>

Re: [PATCH v4 14/20] KVM: arm/arm64: Avoid timer save/restore in vcpu entry/exit

On Thu, Nov 16, 2017 at 3:30 PM, Jintack Lim <jint...@cs.columbia.edu> wrote: > Hi Christoffer, > > On Fri, Oct 20, 2017 at 7:49 AM, Christoffer Dall > <christoffer.d...@linaro.org> wrote: >> From: Christoffer Dall <cd...@linaro.org> >> >> We don't n

Re: [PATCH v4 14/20] KVM: arm/arm64: Avoid timer save/restore in vcpu entry/exit

Hi Christoffer, On Fri, Oct 20, 2017 at 7:49 AM, Christoffer Dall wrote: > From: Christoffer Dall > > We don't need to save and restore the hardware timer state and examine > if it generates interrupts on on every entry/exit to the guest. The >

[RFC PATCH v2 29/31] KVM: arm64: Respect the virtual HCR_EL2.AT and NV setting

Forward system instruction traps to the virtual EL2 if a corresponding bit in the virtual HCR_EL2 is set. Signed-off-by: Jintack Lim <jintack@linaro.org> --- Notes: v1-->v2: This is a new commit. We can rework existing forward_nv_traps() and forward_nv1_traps() defined

[RFC PATCH v2 31/31] KVM: arm64: Fixes to toggle_cache for nesting

re EL1 register). Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/include/asm/kvm_mmu.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/inc

[RFC PATCH v2 27/31] KVM: arm64: Emulate TLBI VMALLS12E1(IS) instruction

Based on the same principle as TLBI ALLE1(IS) emulation, we clear the mappings in the shadow stage-2 page tables and invalidate TLB entries. But this time we do it only for the current VMID from the guest hypervisor's perspective, not for all VMIDs. Signed-off-by: Jintack Lim <jint

[RFC PATCH v2 14/31] KVM: arm/arm64: Forward the guest hypervisor's stage 2 permission faults

about the fault. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm/include/asm/kvm_mmu.h | 7 +++ arch/arm64/include/asm/kvm_mmu.h | 2 ++ arch/arm64/kvm/mmu-nested.c | 22 ++

[RFC PATCH v2 21/31] KVM: arm64: Emulate AT S1E[01] instructions

Emulate AT S1E[01] instructions by issuing the same instructions in EL2. We set the physical EL1 registers, NV and NV1 bits as described in the AT instruction emulation overview. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/include/asm/kvm_emulate.h | 11 +++

[RFC PATCH v2 30/31] KVM: arm64: Emulate TLBI instructions accesible from EL1

, then execute the same instruction in EL2. We don't set HCR_EL2.TTLB bit yet. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/include/asm/kvm_asm.h | 1 + arch/arm64/include/asm/kvm_mmu.h | 1 + arch/arm64/include/asm/sysreg.h | 15 arch/arm64/kvm/hyp

[RFC PATCH v2 26/31] KVM: arm64: Emulate TLBI ALLE1(IS)

ings in the stage 2 page tables maintained by the guest hypervisor. We then need to invalidate all EL1&0 regime stage 1 and 2 TLB entries of all VMIDs, which are assigned by the host hypervisor, for this VM. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/kvm/s

[RFC PATCH v2 24/31] KVM: arm64: Emulate TLBI ALLE2(IS) instruction

tage 1 TLB entries via TLBI VMALL1IS instruction, but to make it simeple, we reuse the existing function, __kvm_tlb_flush_vmid(), which invalidates both of stage 1 and 2 TLB entries. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/kvm/sys_r

[RFC PATCH v2 16/31] KVM: arm64: Introduce sys_reg_desc.forward_trap

This introduces a function prototype to determine if we need to forward system instruction traps to the virtual EL2. The implementation of forward_trap functions for each system instruction will be added in later patches. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm

[RFC PATCH v2 28/31] KVM: arm64: Emulate TLBI IPAS2E1* instructions

Based on the same principle as TLBI ALLE1(IS) and TLBI VMALLS12E1(IS) emulation, we clear the mappings in the shadow stage-2 page tables and invalidate TLB entries. We do it only for one mapping for the current VMID from the guest hypervisor's view. Signed-off-by: Jintack Lim <jint

[RFC PATCH v2 15/31] KVM: arm64: Move system register helper functions around

From: Jintack Lim <jint...@cs.columbia.edu> We are about to add a framework to handle system instruction traps. To reuse existing helper functions, let's move them around. No functional change. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/kvm/sys

[RFC PATCH v2 22/31] KVM: arm64: Emulate AT S1E2 instructions

Emulate AT S1E2 instructions by issuing the corresponding S1E1 instructions in EL2. We set the physical EL1 registers and the HCR_EL2 register as described in the AT instruction emulation overview. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/kvm/sys_regs.

[RFC PATCH v2 18/31] KVM: arm64: Enumerate AT and TLBI instructions to emulate

List all system instructions to emulate. This patch only introduces the definitions, emulation handlers will be added in subsequent patches. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/include/asm/sysreg.h | 38 ++ arch/arm

[RFC PATCH v2 20/31] KVM: arm64: Implement AT instruction handling

registers and executing AT instructions. Note that ctxt->hw_sys_regs is expected to have the proper processor context before calling the handling function(__kvm_at_insn) implemented in this patch. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/include/asm/kvm_asm.h |

[RFC PATCH v2 25/31] KVM: arm64: Emulate TLBI VAE2* instrutions

Emulate TLBI VAE2* instruction executed in the virtual EL2. Based on the same principle as TLBI ALLE2 instruction, we can simply emulate those instructions by executing corresponding VAE1* instructions with the virtual EL2's VMID assigned by the host hypervisor. Signed-off-by: Jintack Lim

[RFC PATCH v2 17/31] KVM: arm64: Rework the system instruction emulation framework

Rework the system instruction emulation framework to handle potentially all system instruction traps other than MSR/MRS instructions. Those system instructions would be AT and TLBI instructions controlled by HCR_EL2.NV, AT, and TTLB bits. Signed-off-by: Jintack Lim <jintack@linaro.

[RFC PATCH v2 19/31] KVM: arm64: Describe AT instruction emulation design

This design overview will help to digest the subsequent patches that implement AT instruction emulation. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/kvm/sys_regs.c | 66 +++ 1 file changed, 66 insertions(+) diff --git

[RFC PATCH v2 05/31] KVM: arm/arm64: Support mmu for the virtual EL2 execution

ucture does not have vttbr any more. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jintack@linaro.org> --- Notes: v1-->v2: Fixed a bug that hw_vttbr was not initialized correctly in kvm_arch_vcpu_init() where vmid

[RFC PATCH v2 12/31] KVM: arm/arm64: Handle shadow stage 2 page faults

riable names so that fault_ipa is used for the former and ipa is used for the latter. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jintack@linaro.org> --- Notes: v1-->v2: - Added a common function to inject s2 faults. -

[RFC PATCH v2 11/31] KVM: arm64: Implement nested Stage-2 page table walk logic

From: Christoffer Dall <christoffer.d...@linaro.org> Based on the pseudo-code in the ARM ARM, implement a stage 2 software page table walker. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jintack@linaro.org> --- Notes: v1--

[RFC PATCH v2 09/31] KVM: arm/arm64: Manage mmus for nested VMs

a set of shadow stage-2 page tables for each shadow VMID. All this information is stored in kvm_nested_s2_mmu struct. A host hypervisor manages a list of kvm_nested_s2_mmu objects per VM. On a VM entry it searches an object in the list using a virtual VMID as a key. Signed-off-by: Jintack Lim

[RFC PATCH v2 08/31] KVM: arm/arm64: Make mmu functions non-static

From: Christoffer Dall <christoffer.d...@linaro.org> Make mmu functions non-static so that we can reuse those functions to support mmu for the nested VMs. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch

[RFC PATCH v2 10/31] KVM: arm/arm64: Unmap/flush shadow stage 2 page tables

xample by clearing out an entire shadow stage-2 table. This will be handled in a more efficient way using the reverse mapping feature in a later version of the patch series. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jintack@linaro.org>

[RFC PATCH v2 03/31] KVM: arm/arm64: Remove unused params in mmu functions

inaro.org> Signed-off-by: Jintack Lim <jintack@linaro.org> --- virt/kvm/arm/mmu.c | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c index f2d5b6c..0a5f5ca 100644 --- a/virt/kvm/arm/mmu.c +++ b/virt/kvm/arm/mmu.

[RFC PATCH v2 07/31] KVM: arm64: Setup vttbr_el2 on each VM entry

ed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/kvm/context.c | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c index a7811e1..afd1702 100644 --

[RFC PATCH v2 06/31] KVM: arm64: Invalidate virtual EL2 TLB entries when needed

; Signed-off-by: Jintack Lim <jintack@linaro.org> --- virt/kvm/arm/arm.c | 5 + virt/kvm/arm/mmu.c | 23 ++- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index 41e0654..63dd897 100644 --- a/virt/kvm/arm/arm.c

[RFC PATCH v2 00/31] Nested Virtualization on KVM/ARM - memory virtualization

ing Dave Martin (1): arm64: KVM: Hide unsupported AArch64 CPU features from guests Jintack Lim (18): KVM: arm64: Expose limited memory management support to the virtual EL2 KVM: arm/arm64: Manage mmus for nested VMs KVM: arm64: Move system register helper functions around KVM: ar

[RFC PATCH v2 02/31] KVM: arm64: Expose limited memory management support to the virtual EL2

. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/kvm/sys_regs.c | 47 ++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 65f4c20..395b964 100644 --- a/arch/arm

[RFC PATCH v2 01/31] arm64: KVM: Hide unsupported AArch64 CPU features from guests

From: Dave Martin Currently, a guest kernel sees the true CPU feature registers (ID_*_EL1) when it reads them using MRS instructions. This means that the guest will observe features that are present in the hardware but the host doesn't understand or doesn't provide support

Re: [RFC PATCH v2 20/38] KVM: arm64: Handle eret instruction traps

On Sun, Jul 30, 2017 at 4:00 PM, Christoffer Dall <cd...@linaro.org> wrote: > On Tue, Jul 18, 2017 at 11:58:46AM -0500, Jintack Lim wrote: >> When HCR.NV bit is set, eret instructions trap to EL2 with EC code 0x1A. >> Emulate eret instructions by setting pc and pstate. >

Re: [RFC PATCH v2 08/38] KVM: arm64: Add EL2 special registers to vcpu context

On Sun, Jul 30, 2017 at 3:59 PM, Christoffer Dall <cd...@linaro.org> wrote: > On Tue, Jul 18, 2017 at 11:58:34AM -0500, Jintack Lim wrote: >> To support the virtual EL2 execution, we need to maintain the EL2 >> special registers such as SPSR_EL2, ELR_EL2 and SP_EL2 in vcp

Re: [RFC PATCH v2 04/38] KVM: arm/arm64: Check if nested virtualization is in use

On Sun, Jul 30, 2017 at 3:59 PM, Christoffer Dall <cd...@linaro.org> wrote: > On Tue, Jul 18, 2017 at 11:58:30AM -0500, Jintack Lim wrote: >> Nested virtualizaion is in use only if all three conditions are met: >> - The architecture supports nested virtualization. >> -

Re: [RFC PATCH v2 02/38] KVM: arm/arm64: Enable nested virtualization via command-line

On Sun, Jul 30, 2017 at 3:59 PM, Christoffer Dall <cd...@linaro.org> wrote: > On Tue, Jul 18, 2017 at 11:58:28AM -0500, Jintack Lim wrote: >> Add a new kernel parameter(kvm-arm.nested) to enable KVM/ARM nested >> virtualization support. This kernel parameter on arm architectur

Re: [RFC PATCH v2 04/38] KVM: arm/arm64: Check if nested virtualization is in use

On Sun, Jul 30, 2017 at 3:59 PM, Christoffer Dall <cd...@linaro.org> wrote: > On Tue, Jul 18, 2017 at 11:58:30AM -0500, Jintack Lim wrote: >> Nested virtualizaion is in use only if all three conditions are met: >> - The architecture supports nested virtualization. >> -

Re: [RFC PATCH v2 00/38] Nested Virtualization on KVM/ARM

On Fri, Jul 28, 2017 at 4:13 PM, Bandan Das <b...@redhat.com> wrote: > Jintack Lim <jintack@linaro.org> writes: > ... >>> >>> I'll share my experiment setup shortly. >> >> I summarized my experiment setup here. >> >> https://githu

Re: [RFC PATCH v2 00/38] Nested Virtualization on KVM/ARM

On Wed, Jul 19, 2017 at 4:49 AM, Christoffer Dall <cd...@linaro.org> wrote: > Hi Jintack, > > On Tue, Jul 18, 2017 at 10:23:05PM -0400, Jintack Lim wrote: >> On Tue, Jul 18, 2017 at 12:58 PM, Jintack Lim <jintack@linaro.org> wrote: >> > Nested virtualiza

Re: [RFC PATCH v2 37/38] KVM: arm64: Respect the virtual HCR_EL2.NV1 bit setting

On Tue, Jul 18, 2017 at 12:59 PM, Jintack Lim <jintack@linaro.org> wrote: > Forward ELR_EL1, SPSR_EL1 and VBAR_EL1 traps to the virtual EL2 if the > virtual HCR_EL2.NV bit is set. > > This is for recursive nested virtualization. > > Signed-off-by: Jintack Lim

Re: [RFC PATCH v2 00/38] Nested Virtualization on KVM/ARM

On Tue, Jul 18, 2017 at 12:58 PM, Jintack Lim <jintack@linaro.org> wrote: > Nested virtualization is the ability to run a virtual machine inside another > virtual machine. In other words, it’s about running a hypervisor (the guest > hypervisor) on top of another hypervisor (the

[RFC PATCH v2 37/38] KVM: arm64: Respect the virtual HCR_EL2.NV1 bit setting

Forward ELR_EL1, SPSR_EL1 and VBAR_EL1 traps to the virtual EL2 if the virtual HCR_EL2.NV bit is set. This is for recursive nested virtualization. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/include/asm/kvm_arm.h | 1 + arch/arm64/kvm/sys_regs.c

[RFC PATCH v2 23/38] KVM: arm64: Inject HVC exceptions to the virtual EL2

Now that the psci call is done by the smc instruction when nested virtualization is enabled, it is clear that all hvc instruction from the VM (including from the virtual EL2) are supposed to handled in the virtual EL2. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm

[RFC PATCH v2 38/38] KVM: arm64: Respect the virtual CPTR_EL2.TCPAC setting

Forward CPACR_EL1 traps to the virtual EL2 if virtual CPTR_EL2 is configured to trap CPACR_EL1 accesses from EL1. This is for recursive nested virtualization. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/kvm/sys_regs.c | 5 + 1 file changed, 5 insertions(+) diff

[RFC PATCH v2 34/38] KVM: arm64: Respect the virtual HCR_EL2.NV bit setting

Forward traps due to HCR_EL2.NV bit to the virtual EL2 if they are not coming from the virtual EL2 and the virtual HCR_EL2.NV bit is set. This is for recursive nested virtualization. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/include/asm/kvm_arm.h| 1 + arch

[RFC PATCH v2 35/38] KVM: arm64: Respect the virtual HCR_EL2.NV bit setting for EL12 register traps

-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/kvm/sys_regs.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 4fd7090..3559cf7 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_

[RFC PATCH v2 33/38] KVM: arm64: Emulate appropriate VM control system registers

Now that the virtual EL2 can access EL2 register states via EL1 registers, we need to consider it when selecting the register to emulate. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/kvm/sys_regs.c | 46 -- 1 file chang

[RFC PATCH v2 30/38] KVM: arm64: Allow the virtual EL2 to access EL2 states without trap

since those registers already have EL2 register states. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/kvm/hyp/switch.c | 23 +-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c

[RFC PATCH v2 24/38] KVM: arm64: Respect virtual HCR_EL2.TWX setting

Forward exceptions due to WFI or WFE instructions to the virtual EL2 if they are not coming from the virtual EL2 and virtual HCR_EL2.TWX is set. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/handle_exit.c

[RFC PATCH v2 31/38] KVM: arm64: Manage the shadow states when virtual E2H bit enabled

to EL2. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/kvm/context.c | 67 +++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c index 39bd92d..9947bc8 100644 ---

[RFC PATCH v2 32/38] KVM: arm64: Trap and emulate CPTR_EL2 accesses via CPACR_EL1 from the virtual EL2 with VHE

virtual CPTR_EL2. The downside of using v8.0 format is to convert the format when copying states between CPTR_EL2 and CPACR_EL1 to support the virtual EL2 with VHE. The decision is subject to change depending on the future discussion. Signed-off-by: Jintack Lim <jintack@linaro.org> ---

[RFC PATCH v2 29/38] KVM: arm64: Support a VM with VHE considering EL0 of the VHE host

without trapping to the host hypervisor. So, when returning from the VHE host mode, set the vcpu mode depending on the physical exception level. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/kvm/context.c | 36 ++-- 1 file changed, 22 inse

[RFC PATCH v2 27/38] KVM: arm64: Add EL2 registers defined in ARMv8.1 to vcpu context

ARMv8.1 added more EL2 registers: TTBR1_EL2, CONTEXTIDR_EL2, and three EL2 virtual timer registers. Add the first two registers to vcpu context and set their handlers. The timer registers and their handlers will be added in a separate patch. Signed-off-by: Jintack Lim <jintack@linaro.

[RFC PATCH v2 22/38] KVM: arm64: Handle PSCI call via smc from the guest

-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/kvm/handle_exit.c | 24 ++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index d19e253..6cf6b93 100644 --- a/arch/arm64/kvm/handle_

[RFC PATCH v2 26/38] KVM: arm64: Add macros to support the virtual EL2 with VHE

These macros will be used to support the virtual EL2 with VHE. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/include/asm/kvm_emulate.h | 24 1 file changed, 24 insertions(+) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/inclu

[RFC PATCH v2 25/38] KVM: arm64: Respect virtual CPTR_EL2.TFP setting

Forward traps due to FP/ASIMD register accesses to the virtual EL2 if virtual CPTR_EL2.TFP is set. Note that if TFP bit is set, then even accesses to FP/ASIMD register from EL2 as well as NS EL0/1 will trap to EL2. So, we don't check the VM's exception level. Signed-off-by: Jintack Lim <jint

[RFC PATCH v2 28/38] KVM: arm64: Emulate EL12 register accesses from the virtual EL2

it's one of the EL12 registers controlled by HCR_EL2.NV bit. Therefore, add a handler for it and don't treat it as a non-trap-registers when preparing a shadow context. Move EL12 system register macros to a common place to reuse them. Signed-off-by: Jintack Lim <jintack@linaro.org> ---

[RFC PATCH v2 20/38] KVM: arm64: Handle eret instruction traps

the virtual _EL2 registers. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/include/asm/esr.h | 1 + arch/arm64/kvm/handle_exit.c | 16 arch/arm64/kvm/trace.h | 21 + 3 files changed, 38 insertions(+) diff --git a/arch/arm64/inclu

[RFC PATCH v2 17/38] KVM: arm64: Trap EL1 VM register accesses in virtual EL2

From: Christoffer Dall When running in virtual EL2 mode, we actually run the hardware in EL1 and therefore have to use the EL1 registers to ensure correct operation. By setting the HCR.TVM and HCR.TVRM we ensure that the virtual EL2 mode doesn't shoot itself in the

[RFC PATCH v2 12/38] arm64: Add missing TCR hw defines

From: Christoffer Dall Some bits of the TCR weren't defined and since we're about to use these in KVM, add these defines. Signed-off-by: Christoffer Dall --- arch/arm64/include/asm/pgtable-hwdef.h | 6 ++ 1 file changed, 6

[RFC PATCH v2 21/38] KVM: arm64: Set a handler for the system instruction traps

EL2 and above are trapped to EL2. In these cases, ESR_EL2.EC will be set to 0x18. Change the existing handler to handle those system instructions as well as MRS/MSR instructions. Emulation of each system instructions will be done in separate patches. Signed-off-by: Jintack Lim <jint

[RFC PATCH v2 18/38] KVM: arm64: Trap SPSR_EL1, ELR_EL1 and VBAR_EL1 from virtual EL2

. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/include/asm/sysreg.h | 2 ++ arch/arm64/kvm/sys_regs.c | 29 - 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h

[RFC PATCH v2 16/38] KVM: arm64: Support to inject exceptions to the virtual EL2

Support inject synchronous exceptions to the virtual EL2 as described in ARM ARM AArch64.TakeException(). This can be easily extended to support to inject asynchronous exceptions to the virtual EL2, but it will be added in a later patch when appropriate. Signed-off-by: Jintack Lim <jint

[RFC PATCH v2 11/38] KVM: arm64: Set vcpu context depending on the guest exception level

If the guest exception level is EL2, then set up the shadow context of the virtual EL2 to hardware. Otherwise, set the regular EL0/EL1 context. Note that the shadow context content will be prepared in subsequent patches. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm

[RFC PATCH v2 13/38] KVM: arm64: Create shadow EL1 registers

state. When entering EL1/EL0, we need a special care for MPIDR_EL1. Read of this register returns the value of VMPIDR_EL2, so when a VM has the virtual EL2, the value of MPIDR_EL1 should come from the virtual VMPIDR_EL2. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off

[RFC PATCH v2 19/38] KVM: arm64: Trap CPACR_EL1 access in virtual EL2

For the same reason we trap virtual memory register accesses in virtual EL2, we trap CPACR_EL1 access too; We allow the virtual EL2 mode to access EL1 system register state instead of the virtual EL2 one. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/kvm/hyp/switch.

[RFC PATCH v2 15/38] KVM: arm64: Move exception macros and enums to a common file

These macros and enums can be reused to inject exceptions for nested virtualization. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/include/asm/kvm_emulate.h | 12 arch/arm64/kvm/inject_fault.c| 12 2 files changed, 12 insertions(

[RFC PATCH v2 10/38] KVM: arm/arm64: Add a framework to prepare virtual EL2 execution

ed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm/include/asm/kvm_emulate.h | 4 ++ arch/arm64/include/asm/kvm_emulate.h | 4 ++ arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/context.c

[RFC PATCH v2 14/38] KVM: arm64: Synchronize EL1 system registers on virtual EL2 entry and exit

ed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/kvm/context.c | 58 ++-- 1 file changed, 56 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c index e965049..e1bc753 100644 --- a/arch/arm64/kvm/con

[RFC PATCH v2 09/38] KVM: arm64: Add the shadow context for virtual EL2 execution

With the nested virtualization support, a hypervisor running inside a VM (i.e. a guest hypervisor) is now deprivilaged and runs in EL1 instead of EL2. So, the host hypervisor manages the shadow context for the virtual EL2 execution. Signed-off-by: Jintack Lim <jintack@linaro.org> ---

[RFC PATCH v2 08/38] KVM: arm64: Add EL2 special registers to vcpu context

To support the virtual EL2 execution, we need to maintain the EL2 special registers such as SPSR_EL2, ELR_EL2 and SP_EL2 in vcpu context. Note that SP_EL2 is not accessible in EL2, so we don't need a trap handler for this register. Signed-off-by: Jintack Lim <jintack@linaro.org> ---

[RFC PATCH v2 05/38] KVM: arm64: Allow userspace to set PSR_MODE_EL2x

From: Christoffer Dall We were not allowing userspace to set a more privileged mode for the VCPU than EL1, but now that we support nesting with a virtual EL2 mode, do allow this! Signed-off-by: Christoffer Dall ---

[RFC PATCH v2 07/38] KVM: arm64: Add EL2 system registers to vcpu context

. This patch doesn't set the NV bit yet. It will be set in a later patch once nested virtualization support is completed. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm64/include/asm/kvm_host.h | 30 +++- arch/arm64/include/asm/sysreg.h

[RFC PATCH v2 06/38] KVM: arm64: Add vcpu_mode_el2 primitive to support nesting

From: Christoffer Dall When running a nested hypervisor we occasionally have to figure out if the mode we are switching into is the virtual EL2 mode or a regular EL0/1 mode. Signed-off-by: Christoffer Dall ---

[RFC PATCH v2 03/38] KVM: arm64: Add KVM nesting feature

From: Christoffer Dall <christoffer.d...@linaro.org> Set the initial exception level of the guest to EL2 if nested virtualization feature is enabled. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch

[RFC PATCH v2 04/38] KVM: arm/arm64: Check if nested virtualization is in use

Nested virtualizaion is in use only if all three conditions are met: - The architecture supports nested virtualization. - The kernel parameter is set. - The userspace uses nested virtualiztion feature. Signed-off-by: Jintack Lim <jintack@linaro.org> --- arch/arm/include/asm/kvm_host.h

[RFC PATCH v2 00/38] Nested Virtualization on KVM/ARM

EL2 Jintack Lim (31): arm64: Add ARM64_HAS_NESTED_VIRT feature KVM: arm/arm64: Enable nested virtualization via command-line KVM: arm/arm64: Check if nested virtualization is in use KVM: arm64: Add EL2 system registers to vcpu context KVM: arm64: Add EL2 special registers to vcpu cont

Re: [RFC 06/55] KVM: arm64: Add EL2 execution context for nesting

Thanks Christoffer and Marc, On Mon, Jul 3, 2017 at 5:54 AM, Christoffer Dall <cd...@linaro.org> wrote: > On Mon, Jul 03, 2017 at 10:32:45AM +0100, Marc Zyngier wrote: >> On 03/07/17 10:03, Christoffer Dall wrote: >> > On Mon, Jun 26, 2017 at 10:33:23AM -0400, Jin

Re: [RFC 21/55] KVM: arm64: Forward HVC instruction to the guest hypervisor

On Wed, Feb 22, 2017 at 6:47 AM, Christoffer Dall <cd...@linaro.org> wrote: > On Mon, Jan 09, 2017 at 01:24:17AM -0500, Jintack Lim wrote: >> Forward exceptions due to hvc instruction to the guest hypervisor. >> >> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu&

Re: [RFC 06/55] KVM: arm64: Add EL2 execution context for nesting

Hi Christoffer, On Wed, Feb 22, 2017 at 6:10 AM, Christoffer Dall <cd...@linaro.org> wrote: > On Mon, Jan 09, 2017 at 01:24:02AM -0500, Jintack Lim wrote: >> With the nested virtualization support, the context of the guest >> includes EL2 register states. The host manages

Re: [RFC 10/55] KVM: arm64: Synchronize EL1 system registers on virtual EL2 entry and exit

Hi Bandan, On Tue, Jun 6, 2017 at 4:16 PM, Bandan Das <b...@redhat.com> wrote: > Jintack Lim <jint...@cs.columbia.edu> writes: > >> From: Christoffer Dall <christoffer.d...@linaro.org> >> >> When running in virtual EL2 we use the shadow EL1 systerm regi

Re: [RFC 11/55] KVM: arm64: Emulate taking an exception to the guest hypervisor

On Tue, Jun 6, 2017 at 6:07 PM, Bandan Das <b...@redhat.com> wrote: > Hi Jintack, > > Jintack Lim <jintack@linaro.org> writes: > >> Hi Bandan, >> >> On Tue, Jun 6, 2017 at 4:21 PM, Bandan Das <b...@redhat.com> wrote: >>> Jintack Lim

Re: [RFC 11/55] KVM: arm64: Emulate taking an exception to the guest hypervisor

Hi Bandan, On Tue, Jun 6, 2017 at 4:21 PM, Bandan Das <b...@redhat.com> wrote: > Jintack Lim <jint...@cs.columbia.edu> writes: > >> Emulate taking an exception to the guest hypervisor running in the >> virtual EL2 as described in ARM ARM AArch64.TakeException(

Re: [PATCH v2] KVM: arm/arm64: Let vcpu thread modify its own active state

Hi Christoffer, thanks for submitting this patch. On Mon, Mar 6, 2017 at 8:42 AM, Christoffer Dall <christoffer.d...@linaro.org> wrote: > From: Jintack Lim <jint...@cs.columbia.edu> > > Currently, if a vcpu thread tries to change the active state of an > interrupt whic

Re: [RFC 00/55] Nested Virtualization on KVM/ARM

gt; On Mon, Jan 09, 2017 at 01:23:56AM -0500, Jintack Lim wrote: >> Nested virtualization is the ability to run a virtual machine inside another >> virtual machine. In other words, it’s about running a hypervisor (the guest >> hypervisor) on top of another hypervisor (the host hyp

Re: [RFC 00/55] Nested Virtualization on KVM/ARM

Hi Christoffer, On Wed, Feb 22, 2017 at 1:23 PM, Christoffer Dall <cd...@linaro.org> wrote: > Hi Jintack, > > > On Mon, Jan 09, 2017 at 01:23:56AM -0500, Jintack Lim wrote: > > Nested virtualization is the ability to run a virtual machine inside > another > >

Re: [RFC v4 00/10] Provide the EL1 physical timer to the VM

On Fri, Feb 3, 2017 at 11:14 AM, Marc Zyngier <marc.zyng...@arm.com> wrote: > On 03/02/17 15:19, Jintack Lim wrote: >> The ARM architecture defines the EL1 physical timer and the virtual timer, >> and it is reasonable for an OS to expect to be able to access both. >&g

[RFC v4 09/10] KVM: arm64: Add the EL1 physical timer access handler

KVM traps on the EL1 phys timer accesses from VMs, but it doesn't handle those traps. This results in terminating VMs. Instead, set a handler for the EL1 phys timer access, and inject an undefined exception as an intermediate step. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Re

[RFC v4 06/10] KVM: arm/arm64: Update the physical timer interrupt level

Now that we maintain the EL1 physical timer register states of VMs, update the physical timer interrupt level along with the virtual one. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Acked-by: Christoffer Dall <christoffer.d...@linaro.org> --- virt/kvm/arm/arch_timer.c | 4

[RFC v4 03/10] KVM: arm/arm64: Decouple kvm timer functions from virtual timer

Now that we have a separate structure for timer context, make functions generic so that they can work with any timer context, not just the virtual timer context. This does not change the virtual timer functionality. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Acked-by: Marc Z

[RFC v4 08/10] KVM: arm/arm64: Set up a background timer for the physical timer emulation

use the virtual timer since the physical timer is always not enabled. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> --- virt/kvm/arm/arch_timer.c | 25 - 1 file changed, 24 insertions(+), 1 delet

[RFC v4 05/10] KVM: arm/arm64: Initialize the emulated EL1 physical timer

Initialize the emulated EL1 physical timer with the default irq number. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm/kvm/reset.c | 9 - arch/arm64/kvm/reset.c | 9 -

[RFC v4 07/10] KVM: arm/arm64: Set a background timer to the earliest timer expiration

When scheduling a background timer, consider both of the virtual and physical timer and pick the earliest expiration time. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm/kvm/arm.c| 3 ++-

[RFC v4 01/10] KVM: arm/arm64: Abstract virtual timer context into separate structure

Abstract virtual timer context into a separate structure and change all callers referring to timer registers, irq state and so on. No change in functionality. This is about to become very handy when adding the EL1 physical timer. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu>

[RFC v4 04/10] KVM: arm/arm64: Add the EL1 physical timer context

Add the EL1 physical timer context. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Acked-by: Christoffer Dall <christoffer.d...@linaro.org> --- include/kvm/arm_arch_timer.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_

[RFC v4 00/10] Provide the EL1 physical timer to the VM

and restore enable field back to arch_timer_cpu structure Jintack Lim (10): KVM: arm/arm64: Abstract virtual timer context into separate structure KVM: arm/arm64: Move cntvoff to each timer context KVM: arm/arm64: Decouple kvm timer functions from virtual timer KVM: arm/arm64: Add the

Re: [RFC v3 00/10] Provide the EL1 physical timer to the VM

On Fri, Feb 3, 2017 at 7:33 AM, Christoffer Dall <cd...@linaro.org> wrote: > On Thu, Feb 02, 2017 at 09:51:13AM -0500, Jintack Lim wrote: >> On Thu, Feb 2, 2017 at 7:31 AM, Christoffer Dall <cd...@linaro.org> wrote: >> > Hi Jintack, >> > >> > On We

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