Hi folks,
After many years of awesome service, the kvmarm mailing list hosted by
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lore.kernel.org, and I am placing the old list under emergency
moderation *NOW*.
If you haven't yet subscribed to the new kvmarm list and still want
Alexandru Elisei (1):
MAINTAINERS: Remove myself as a KVM/arm64 reviewer
James Clark (1):
KVM: arm64: PMU: Fix PMCR_EL0 reset value
Marc Zyngier (8):
KVM: arm64: Fix S1PTW handling on RO memslots
KVM: arm64: Document the behaviour of S1PTW faults
On Thu, 05 Jan 2023 00:37:48 +,
"Paul E. McKenney" wrote:
>
> Now that the SRCU Kconfig option is unconditionally selected, there is
> no longer any point in selecting it. Therefore, remove the "select SRCU"
> Kconfig statements.
>
> Signed-off-by
pts so I apologize if the following review
> is rather shallow but...
No need to apologise. Any extra pair of eye is welcome, specially when
the idiot behind the keyboard writes stuff like the patch below...
>
> On Tue, Jan 03, 2023 at 09:50:20AM +, Marc Zyngier wrote:
> > I
On Fri, 9 Dec 2022 16:44:45 +, James Clark wrote:
> We noticed qemu failing to run because of an assert on our CI. I don't see
> the issue anymore with
> this fix.
>
> Applies to kvmarm/next (753d734f3f34)
>
> Thanks
>
> [...]
Applied to fixes, thanks!
[1/1] KVM: arm64: PMU: Fix PMCR_EL0
On Tue, 3 Jan 2023 09:50:19 +, Marc Zyngier wrote:
> I've spent the holiday break reviving the Nested Virt KVM/arm64
> implementation[1] and allowing it to work on the Apple M2 SoC. The
> amusing part is that it actually works!
>
> However, the way the vgic is implemented on t
On Tue, 3 Jan 2023 12:39:33 +, Marc Zyngier wrote:
> Zenghui has been around for quite some time, and has been instrumental
> in reviewing the GICv4/4.1 KVM support. I'm delighted that he's agreed
> to help with the patch review in a more official capacity!
Applied to fixes, than
ned-off-by: Alexandru Elisei
> ---
> MAINTAINERS | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7f86d02cb427..813673637500 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11356,7 +11356,6 @@ F:virt/kvm/*
> KERNEL
On Tue, 03 Jan 2023 12:40:34 +,
Jonathan Cameron wrote:
>
> On Thu, 29 Dec 2022 19:59:21 -0800
> Reiji Watanabe wrote:
>
> > The goal of this series is to allow userspace to limit the number
> > of PMU event counters on the vCPU.
>
> Hi Rieji,
>
> Why do you want to do this?
>
> I can
Zenghui has been around for quite some time, and has been instrumental
in reviewing the GICv4/4.1 KVM support. I'm delighted that he's agreed
to help with the patch review in a more official capacity!
Cc: Zenghui Yu
Signed-off-by: Marc Zyngier
---
MAINTAINERS | 1 +
1 file changed, 1 insertion
The former is an AArch32 legacy, so let's move over to the
verbose (and strictly identical) version.
This involves moving some of the #defines that were private
to KVM into the more generic esr.h.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/esr.h| 9 +
arch
d-by: Ard Biesheuvel
Regression-tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
Cc: sta...@vger.kernel.org
---
arch/arm64/include/asm/kvm_emulate.h | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_emulate.h
b/arch/arm64/inclu
, document the fact that such an access results in a guest
exception, not an exit. This is consistent with the guest being
terminally broken anyway.
Reviewed-by: Oliver Upton
Signed-off-by: Marc Zyngier
---
Documentation/virt/kvm/api.rst | 8
1 file changed, 8 insertions(+)
diff --git
.
* From v1:
- Added the documentation patch
- Dropped the AF micro-optimisation, as it was creating more
confusion, was hard to test, and was of dubious value
- Collected RBs, with thanks
Marc Zyngier (3):
KVM: arm64: Fix S1PTW handling on RO memslots
KVM: arm64: Document the behaviour
In order to deliver vgic maintenance interrupts that Nested Virt
requires, hook it into the FIQ space, even if it is delivered
as an IRQ (we don't distinguish between the two anyway).
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-apple-aic.c | 55 +
1 file
-WIP
Marc Zyngier (3):
KVM: arm64: vgic: Add Apple M2 cpus to the list of broken SEIS
implementations
KVM: arm64: vgic: Allow registration of a non-maskable maintenance
interrupt
irqchip/apple-aic: Register vgic maintenance interrupt with KVM
arch/arm64/include/asm/cputype.h | 4
useful once we enable NV on M2 HW.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/vgic/vgic-init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c
index f6d4f4052555..e61d9ca01768 100644
--- a/arch/arm64/kvm/vgic
, this is all a bit crap.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/cputype.h | 4
arch/arm64/kvm/vgic/vgic-v3.c| 3 ++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 4e8b66c74ea2..683ca3af4084
-WIP
Marc Zyngier (3):
KVM: arm64: vgic: Add Apple M2 cpus to the list of broken SEIS
implementations
KVM: arm64: vgic: Allow registration of a non-maskable maintenance
interrupt
irqchip/apple-aic: Register vgic maintenance interrupt with KVM
arch/arm64/include/asm/cputype.h | 4
On Thu, 29 Dec 2022 13:53:15 +,
Marc Zyngier wrote:
>
> On Wed, 24 Aug 2022 07:03:03 +0100,
> Ganapatrao Kulkarni wrote:
> >
> > Guest-Hypervisor forwards the timer interrupt to Guest-Guest, if it is
> > enabled, unmasked and ISTATUS bit of register CNTV_CTL_
On Wed, 24 Aug 2022 07:03:04 +0100,
Ganapatrao Kulkarni wrote:
>
> In NV case, Shadow stage 2 page table is created using host hypervisor
> page table configuration like page size, block size etc. Also, the shadow
> stage 2 table uses block level mapping if the Guest Hypervisor IPA is
> backed
On Wed, 24 Aug 2022 07:03:03 +0100,
Ganapatrao Kulkarni wrote:
>
> Guest-Hypervisor forwards the timer interrupt to Guest-Guest, if it is
> enabled, unmasked and ISTATUS bit of register CNTV_CTL_EL0 is set for a
> loaded timer.
>
> For NV2 implementation, the Host-Hypervisor is not emulating
On Wed, 24 Aug 2022 07:03:02 +0100,
Ganapatrao Kulkarni wrote:
>
> From: D Scott Phillips
>
> The timer emulation logic goes into an infinite loop when the NestedVM(L2)
> timer is being emulated.
>
> While the CPU is executing in L1 context, the L2 timers are emulated using
> host hrtimer.
On 2022-12-27 13:02, Paolo Bonzini wrote:
Queued, thanks. I will leave this in kvm/queue after testing
everything
else and moving it to kvm/next; this way, we can wait for test results
on other architectures.
Can you please make this a topic branch, and if possible based
on a released -rc?
On Fri, 23 Dec 2022 11:33:35 +,
Sandeep Gupta wrote:
>
> I am trying to run openbsd as guest OS.
> I am using this command to create the vm
> ```
>
> virt-install --name openbsd1 --ram 2048 --vcpus 2 --disk
> path=/var/lib/libvirt/images/openbsd1.qcow2,format=qcow2,bus=virtio,size=20
>
the values saved with the old kernel.
>
> Suggested-by: Marc Zyngier
> Signed-off-by: Akihiko Odaki
> ---
> arch/arm64/include/asm/cache.h| 3 +
> arch/arm64/include/asm/kvm_host.h | 4 +
> arch/arm64/kvm/reset.c| 1 +
> arch/arm64/kvm/sys_regs.c
On Thu, 22 Dec 2022 13:01:55 +,
Ard Biesheuvel wrote:
>
> On Tue, 20 Dec 2022 at 21:09, Marc Zyngier wrote:
> >
> > A recent development on the EFI front has resulted in guests having
> > their page tables baked in the firmware binary, and mapped into
> > t
On Thu, 22 Dec 2022 20:58:40 +,
Oliver Upton wrote:
>
> On Thu, Dec 22, 2022 at 09:01:15AM +, Marc Zyngier wrote:
> > On Wed, 21 Dec 2022 17:46:24 +, Oliver Upton
> > wrote:
> > > - When UFFD is in use, translation faults are reported to userspace as
>
On Wed, 21 Dec 2022 18:06:10 +,
Mark Brown wrote:
>
> The KVM code makes extensive use of ARM64_FEATURE_MASK() to generate a
> mask for fields in the ID registers. This macro has the assumption that
> all feature fields are 4 bits wide but the architecture has evolved to
> add fields with
On Wed, 21 Dec 2022 17:46:24 +,
Oliver Upton wrote:
>
> On Wed, Dec 21, 2022 at 08:46:06AM -0800, Ricardo Koller wrote:
>
> [...]
>
> > > - return false;
> > > + /* Can't introspect TCR_EL1 with pKVM */
> > > + if
On Wed, 21 Dec 2022 16:50:30 +,
Oliver Upton wrote:
>
> On Wed, Dec 21, 2022 at 09:35:06AM +, Marc Zyngier wrote:
>
> [...]
>
> > > > + if (kvm_vcpu_abt_iss1tw(vcpu)) {
> > > > + /*
> > > > +
Hi Ricardo,
On Wed, 21 Dec 2022 16:46:06 +,
Ricardo Koller wrote:
>
> Hello,
>
> On Tue, Dec 20, 2022 at 08:09:22PM +, Marc Zyngier wrote:
> > As a minor optimisation, we can retrofit the "S1PTW is a write
> > even on translation fault" concept *if* th
On Tue, 20 Dec 2022 21:47:36 +,
Oliver Upton wrote:
>
> Hi Marc,
>
> On Tue, Dec 20, 2022 at 08:09:21PM +, Marc Zyngier wrote:
> > A recent development on the EFI front has resulted in guests having
> > their page tables baked in the firmware binary, and mappe
The former is an AArch32 legacy, so let's move over to the
verbose (and strictly identical) version.
This involves moving some of the #defines that were private
to KVM into the more generic esr.h.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/esr.h| 9 +
arch
s to parse the PTs to find out if the DBM bit is set there.
This is not going to happen.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_emulate.h | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/kvm_emulate.h
b/arch/arm
* page sizes!
M.
Marc Zyngier (3):
KVM: arm64: Fix S1PTW handling on RO memslots
KVM: arm64: Handle S1PTW translation with TCR_HA set as a write
KVM: arm64: Convert FSC_* over to ESR_ELx_FSC_*
arch/arm64/include/asm/esr.h| 9
arch/arm64/include/asm/kvm_arm.h
ume write fault on S1PTW permission fault
on instruction fetch")
Signed-off-by: Marc Zyngier
Cc: sta...@vger.kernel.org
---
arch/arm64/include/asm/kvm_emulate.h | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_emulate.h
b/ar
hronization is needed before reading SVCR later in
> fpsimd_save, or it may cause sync exception which can not be
> handled by host.
>
> Cc: Marc Zyngier
> Cc: James Morse
> Cc: Alexandru Elisei
> Cc: Suzuki K Poulose
> Cc: Oliver Upton
> Cc: Catalin Marinas
On Mon, 19 Dec 2022 15:00:15 +,
Mark Brown wrote:
>
> [1 ]
> On Sun, Dec 18, 2022 at 01:11:01PM +0000, Marc Zyngier wrote:
> > Akihiko Odaki wrote:
>
> > > arch/arm64/tools/gen-sysreg.awk does not allow a hole and requires all
> > > bits are described h
On 2022-12-19 14:50, Mark Brown wrote:
On Mon, Dec 19, 2022 at 02:47:25PM +, Marc Zyngier wrote:
Since you're reviewing some of this, please have a look at v3[1],
which outlined a limitation of the sysreg generation tool as well
as a potential fix.
Hrm, would've been nice to be CCed
On 2022-12-19 13:12, Mark Brown wrote:
On Sun, Dec 11, 2022 at 02:16:58PM +0900, Akihiko Odaki wrote:
CCSIDR2_EL1 was added with FEAT_CCIDX.
This corresponds to the definition in DDI0487I.a.
Reviewed-by: Mark Brown
Since you're reviewing some of this, please have a look at v3[1],
which
On Sun, 18 Dec 2022 05:14:10 +,
Akihiko Odaki wrote:
>
> Allow the userspace to set CCSIDR_EL1 so that if the kernel changes the
> default values of CCSIDR_EL1, the userspace can restore the old values
> from an old saved VM context.
>
> Suggested-by: Marc Zyngier
> S
On Sun, 18 Dec 2022 11:35:12 +,
Akihiko Odaki wrote:
>
> On 2022/12/18 20:23, Marc Zyngier wrote:
> > On Sun, 18 Dec 2022 05:14:06 +,
> > Akihiko Odaki wrote:
> >>
> >> Convert CCSIDR_EL1 to automatic generation as per DDI0487I.a. The field
> &g
On Sun, 18 Dec 2022 05:14:06 +,
Akihiko Odaki wrote:
>
> Convert CCSIDR_EL1 to automatic generation as per DDI0487I.a. The field
> definition is for case when FEAT_CCIDX is not implemented. Fields WT,
> WB, RA and WA are defined as per A.j since they are now reserved and
> may have UNKNOWN
On Thu, 15 Dec 2022 00:52:28 +,
Oliver Upton wrote:
>
> On Tue, Dec 06, 2022 at 01:59:18PM +, Ryan Roberts wrote:
> > (appologies, I'm resending this series as I managed to send the cover
> > letter to
> > all but the following patches only to myself on first attempt).
> >
> > This is
that
> the VMM can restore the values saved with the old kernel.
>
> Suggested-by: Marc Zyngier
> Signed-off-by: Akihiko Odaki
> ---
> arch/arm64/include/asm/kvm_arm.h | 3 +-
> arch/arm64/include/asm/kvm_emulate.h | 4 -
> arch/arm64/include/asm
On 2022-12-13 20:03, Sean Christopherson wrote:
One last thought/question, what do y'all think about renaming
directories to
follow the kernel proper? I.e. aarch64=>arm64, s390x=>s390, and
x86_64=>x86.
Then $(ARCH_DIR) would go away. The churn would be unfortunate, but it
would be
nice to
On Fri, 9 Dec 2022 16:44:45 +, James Clark wrote:
> We noticed qemu failing to run because of an assert on our CI. I don't see
> the issue anymore with
> this fix.
>
> Applies to kvmarm/next (753d734f3f34)
>
> Thanks
>
> [...]
Applied to fixes, thanks!
[1/1] KVM: arm64: PMU: Fix PMCR_EL0
Alex,
On Sun, 11 Dec 2022 11:40:39 +,
Alexandru Elisei wrote:
>
> A simple "hey, you're wrong here, the PMU extensions do not follow the
> principles of the ID scheme for fields in ID registers" would have
> sufficed.
This is what I did, and saved you the hassle of looking it up.
> Guess
On Sun, 11 Dec 2022 05:25:31 +,
Akihiko Odaki wrote:
>
> On 2022/12/04 23:57, Marc Zyngier wrote:
> > On Fri, 02 Dec 2022 09:55:24 +,
> > Akihiko Odaki wrote:
> >>
> >> On 2022/12/02 18:40, Marc Zyngier wrote:
> >>> On Fri, 02 Dec
On Fri, 09 Dec 2022 17:58:31 +,
Oliver Upton wrote:
>
> On Fri, Dec 09, 2022 at 04:44:46PM +, James Clark wrote:
> > ARMV8_PMU_PMCR_N_MASK is an unshifted value which results in the wrong
> > reset value for PMCR_EL0, so shift it to fix it.
>
> That's just mean. *_MASK tends to be a
On Fri, 09 Dec 2022 17:47:14 +,
Alexandru Elisei wrote:
>
> Hi,
>
> On Fri, Dec 02, 2022 at 04:55:25AM +, Ricardo Koller wrote:
> > PMUv3p5 uses 64-bit counters irrespective of whether the PMU is configured
> > for overflowing at 32 or 64-bits. The consequence is that tests that check
>
On Tue, 06 Dec 2022 21:43:43 +,
Paolo Bonzini wrote:
>
> On 12/6/22 19:20, Mark Brown wrote:
> >> I almost suggested doing that on multiple occasions this cycle, but
> >> ultimately
> >> decided not to because it would effectively mean splitting series that
> >> touch KVM
> >> and
On Tue, 06 Dec 2022 17:41:21 +,
Paolo Bonzini wrote:
>
> On 12/5/22 16:58, Marc Zyngier wrote:
> > - There is a lot of selftest conflicts with your own branch, see:
> >
> >https://lore.kernel.org/r/20221201112432.4cb9a...@canb.auug.org.au
> >
On Tue, 06 Dec 2022 12:06:00 +,
Ryan Roberts wrote:
>
> This is my first upstream feature submission so please go easy ;-)
Sure! Where are the patches? ;-)
M.
--
Without deviation from the norm, progress is not possible.
___
kvmarm
tic generation
arm64/sysreg: Convert ID_DFR1_EL1 to automatic generation
Marc Zyngier (32):
Merge tag 'kvmarm-fixes-6.1-3' into kvm-arm64/dirty-ring
arm64: Add ID_DFR0_EL1.PerfMon values for PMUv3p7 and IMP_DEF
KVM: arm64: PMU: Align chained counter implementation with architect
On Mon, 5 Dec 2022 11:40:31 +, Ryan Roberts wrote:
> get_user_mapping_size() uses kvm's pgtable library to walk a user space
> page table created by the kernel, and in doing so, fakes up the metadata
> that the library needs, including ia_bits, which defines the size of the
> input address.
>
Hi Ryan,
Thanks for that.
On Mon, 05 Dec 2022 11:40:31 +,
Ryan Roberts wrote:
>
> get_user_mapping_size() uses kvm's pgtable library to walk a user space
> page table created by the kernel, and in doing so, fakes up the metadata
> that the library needs, including ia_bits, which defines
On Thu, 01 Dec 2022 16:51:46 +,
Ricardo Koller wrote:
>
> On Thu, Dec 01, 2022 at 08:47:47AM -0800, Ricardo Koller wrote:
> > On Sun, Nov 13, 2022 at 04:38:20PM +, Marc Zyngier wrote:
> > > The PMU architecture makes a subtle difference between a 64bit
> &
ove, this paragraph doesn't make much sense.
>
> Also, allow the userspace to overwrite the bits with arbitrary values so
> that it can restore a vCPU state saved with an older kernel.
>
> Signed-off-by: Akihiko Odaki
> Suggested-by: Marc Zyngier
> ---
> arch/arm64/inclu
On Fri, 02 Dec 2022 09:55:24 +,
Akihiko Odaki wrote:
>
> On 2022/12/02 18:40, Marc Zyngier wrote:
> > On Fri, 02 Dec 2022 05:17:12 +,
> > Akihiko Odaki wrote:
> >>
> >>>> On M2 MacBook Air, I have seen no other difference in standard ID
&
On Fri, 02 Dec 2022 05:17:12 +,
Akihiko Odaki wrote:
>
> >> On M2 MacBook Air, I have seen no other difference in standard ID
> >> registers and CCSIDRs are exceptions. Perhaps Apple designed this way
> >> so that macOS's Hypervisor can freely migrate vCPU, but I can't assure
> >> that
On Thu, 01 Dec 2022 18:29:51 +,
Oliver Upton wrote:
>
> On Thu, Dec 01, 2022 at 11:06:50AM +, Marc Zyngier wrote:
>
> [...]
>
> > It would be a lot better to expose a virtual topology
> > (one set, one way, one level). It would also save us fro
On Thu, 01 Dec 2022 17:26:08 +,
Akihiko Odaki wrote:
>
> On 2022/12/01 20:06, Marc Zyngier wrote:
> > On Thu, 01 Dec 2022 10:49:11 +,
> > Akihiko Odaki wrote:
> >
> > Thanks for looking into this.
> >
> >> M2 MacBook Air has mism
On Thu, 01 Dec 2022 10:49:11 +,
Akihiko Odaki wrote:
Thanks for looking into this.
> M2 MacBook Air has mismatched CCSIDR associativity bits, which makes the
> bits a KVM vCPU sees inconsistent when migrating.
Can you describe the actual discrepancy? Is that an issue between the
two core
On Tue, 29 Nov 2022 19:19:42 +,
Oliver Upton wrote:
>
> When I implemented the parallel faults series I was mostly focused on
> improving the performance of 8.1+ implementations which bring us
> FEAT_HAFDBS. In so doing, I failed to put access faults on the read side
> of the MMU lock.
>
>
On Wed, 30 Nov 2022 01:23:20 +,
Ricardo Koller wrote:
>
> On Tue, Nov 29, 2022 at 09:15:21PM +, Oliver Upton wrote:
> > Hi Ricardo,
> >
> > Thanks for having a look.
> >
> > On Tue, Nov 29, 2022 at 12:52:12PM -0800, Ricardo Koller wrote:
> > > On Tue, Nov 29, 2022 at 07:19:44PM +,
On Fri, 18 Nov 2022 21:15:01 +, Oliver Upton wrote:
> Small series to add support for arm64 to access_tracking_perf_test and
> correct a couple bugs along the way.
>
> Tested on Ampere Altra w/ all supported guest modes.
>
> v1 -> v2:
> - Have perf_test_util indicate when to stop vCPU
On Thu, 3 Nov 2022 18:10:33 -0700, Peter Collingbourne wrote:
> This patch series allows VMMs to use shared mappings in MTE enabled
> guests. The first five patches were taken from Catalin's tree [1] which
> addressed some review feedback from when they were previously sent out
> as v3 of this
On Fri, 04 Nov 2022 17:42:27 +,
Peter Collingbourne wrote:
>
> On Fri, Nov 4, 2022 at 9:23 AM Marc Zyngier wrote:
> >
> > On Fri, 04 Nov 2022 01:10:33 +,
> > Peter Collingbourne wrote:
> > >
> > > Hi,
> > >
> > > This pa
On Wed, 23 Nov 2022 17:11:41 +,
Reiji Watanabe wrote:
>
> Hi Marc,
>
> On Wed, Nov 23, 2022 at 3:11 AM Marc Zyngier wrote:
> >
> > On Wed, 23 Nov 2022 05:58:17 +,
> > Reiji Watanabe wrote:
> > >
> > > Hi Marc,
> > >
On Wed, 23 Nov 2022 05:58:17 +,
Reiji Watanabe wrote:
>
> Hi Marc,
>
> On Sun, Nov 13, 2022 at 8:46 AM Marc Zyngier wrote:
> >
> > PMUv3p5 (which is mandatory with ARMv8.5) comes with some extra
> > features:
> >
> > - All counters are 64bit
On 2022-11-19 05:52, Reiji Watanabe wrote:
Hi Marc,
On Sun, Nov 13, 2022 at 8:46 AM Marc Zyngier wrote:
Allow userspace to write ID_DFR0_EL1, on the condition that only
the PerfMon field can be altered and be something that is compatible
with what was computed for the AArch64 view
On 2022-11-18 07:45, Reiji Watanabe wrote:
Hi Marc,
On Sun, Nov 13, 2022 at 8:38 AM Marc Zyngier wrote:
Even when using PMUv3p5 (which implies 64bit counters), there is
no way for AArch32 to write to the top 32 bits of the counters.
The only way to influence these bits (other than
On Mon, 07 Nov 2022 12:00:44 +,
Usama Arif wrote:
>
>
>
> On 06/11/2022 16:35, Marc Zyngier wrote:
> > On Fri, 04 Nov 2022 06:20:59 +,
> > Usama Arif wrote:
> >>
> >> This patchset adds support for vcpu_is_preempted in arm64, whic
correct KVM define
> KVM: arm64: selftests: Disable single-step without relying on ucall()
I'm obviously late to the party, but hey... For the record:
Acked-by: Marc Zyngier
M.
--
Without deviation from the norm, progress is not possible.
___
On Tue, 15 Nov 2022 22:55:02 +,
Oliver Upton wrote:
>
> Marek reported a BUG resulting from the recent parallel faults changes,
> as the hyp stage-1 map walker attempted to allocate table memory while
> holding the RCU read lock:
>
> BUG: sleeping function called from invalid context at
>
On Fri, 11 Nov 2022 23:39:09 +,
Oliver Upton wrote:
>
> On Fri, Nov 11, 2022 at 08:26:02AM +, Marc Zyngier wrote:
> > On Thu, 10 Nov 2022 21:13:54 +, Oliver Upton
> > wrote:
> > > The goal of what I was trying to get at is that either the kernel or
>
The PMU code has historically been torn between referencing a counter
as a pair vcpu+index or as the PMC pointer.
Given that it is pretty easy to go from one representation to
the other, standardise on the latter which, IMHO, makes the
code slightly more readable. YMMV.
Signed-off-by: Marc
Allow userspace to write ID_DFR0_EL1, on the condition that only
the PerfMon field can be altered and be something that is compatible
with what was computed for the AArch64 view of the guest.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/sys_regs.c | 57
Allow userspace to write ID_AA64DFR0_EL1, on the condition that only
the PMUver field can be altered and be at most the one that was
initially computed for the guest.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/sys_regs.c | 42 ++-
1 file changed, 41
Now that the infrastructure is in place, bump the PMU support up
to PMUv3p5.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/pmu-emul.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index c37cc67ff1d7..b7a5f75d008d
-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_host.h | 4
arch/arm64/kvm/arm.c | 6 ++
arch/arm64/kvm/pmu-emul.c | 11 ++
arch/arm64/kvm/sys_regs.c | 36 ---
include/kvm/arm_pmu.h | 6 ++
5 files
kvm_pmu_is_3p5() helper makes it easy to spot the
PMUv3p5 specific handling.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/pmu-emul.c | 8 +---
arch/arm64/kvm/sys_regs.c | 4
include/kvm/arm_pmu.h | 7 +++
3 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kvm
The way we compute the target vcpu on getting an overflow is
a bit odd, as we use the PMC array as an anchor for kvm_pmc_to_vcpu,
while we could directly compute the correct address.
Get rid of the intermediate step and directly compute the target
vcpu.
Signed-off-by: Marc Zyngier
---
arch
by something that is pending. The counter should be updated
with the value set by SW, and start counting from there if
required.
Remove the odd computation and just assign the provided value
after having released the perf event (which is then restarted).
Signed-off-by: Marc Zyngier
---
arch/arm64
this distinction in the few cases where it matters in the code,
as we will reuse this with PMUv3p5 long counters.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/pmu-emul.c | 43 ---
1 file changed, 31 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/kvm/pmu-emul.c b
The current PMU emulation sometimes narrows counters to 32bit
if the counter isn't the cycle counter. As this is going to
change with PMUv3p5 where the counters are all 64bit, fix
the couple of cases where this happens unconditionally.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/pmu-emul.c
In order to reduce the boilerplate code, add two helpers returning
the counter register index (resp. the event register) in the vcpu
register file from the counter index.
Reviewed-by: Oliver Upton
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/pmu-emul.c | 33
/20221028105402.2030192-1-...@kernel.org
[3] https://lore.kernel.org/r/20221107085435.2581641-1-...@kernel.org
Marc Zyngier (16):
arm64: Add ID_DFR0_EL1.PerfMon values for PMUv3p7 and IMP_DEF
KVM: arm64: PMU: Align chained counter implementation with
architecture pseudocode
KVM: arm64: PMU
Align the ID_DFR0_EL1.PerfMon values with ID_AA64DFR0_EL1.PMUver.
Reviewed-by: Oliver Upton
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/sysreg.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 7d301700d1a9
in code deletion, removing the notions of
"counter pair", "chained counters", and "canonical counter".
The code is further restructured to make the CHAIN handling similar
to SWINC, as the two are now extremely similar in behaviour.
Reported-by: Ricardo Koller
Signed-o
For 64bit counters that overflow on a 32bit boundary, make
sure we only check the bottom 32bit to generate a CHAIN event.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/pmu-emul.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm
Even when the underlying HW doesn't offer the CHAIN event
(which happens with QEMU), we can always support it as we're
in control of the counter overflow.
Always advertise the event via PMCEID0_EL0.
Reviewed-by: Reiji Watanabe
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/pmu-emul.c | 2
on a counter update.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/pmu-emul.c | 35 +++
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index ea0c8411641f..419e5e0a13d0 100644
--- a/arch/arm64/kvm/pmu
On 2022-11-08 05:36, Reiji Watanabe wrote:
Hi Marc,
> BTW, if we have no intention of supporting a mix of vCPUs with and
> without PMU, I think it would be nice if we have a clear comment on
> that in the code. Or I'm hoping to disallow it if possible though.
I'm not sure we're in a position
On 2022-11-08 05:38, Reiji Watanabe wrote:
Hi Marc,
On Mon, Nov 7, 2022 at 1:16 AM Marc Zyngier wrote:
Allow userspace to write ID_AA64DFR0_EL1, on the condition that only
the PMUver field can be altered and be at most the one that was
initially computed for the guest.
Signed-off-by: Marc
Hi Reiji,
On Sat, 12 Nov 2022 07:55:38 +,
Reiji Watanabe wrote:
>
> Hi Marc,
>
> On Mon, Nov 7, 2022 at 12:54 AM Marc Zyngier wrote:
> >
> > Ricardo recently pointed out that the PMU chained counter emulation
> > in KVM wasn't quite behaving l
On 2022-11-11 22:19, Gavin Shan wrote:
Hi Marc,
On 11/11/22 11:19 PM, Marc Zyngier wrote:
On Thu, 10 Nov 2022 23:47:41 +,
Gavin Shan wrote:
commit b05377ecbe003f12c8b79846fa3a300401dcab68 (HEAD ->
kvm/arm64_dirtyring)
Author: Gavin Shan
Date: Fri Nov 11 07:13:12 2022 +0
On Thu, 03 Nov 2022 05:32:28 +,
Wei-Lin Chang wrote:
>
> HYP_PAGE_OFFSET is removed since 4.8, and the method for generating Hyp
> VAs has evolved. Update the functional description of
> create_hyp_mappings accordingly.
>
> Signed-off-by: Wei-Lin Chang
> ---
> arch/arm64/kvm/mmu.c | 7
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