attributes.
This patch updates vma->vm_page_prot and maps with write-combine
attribute if the associated BAR is prefetchable. For ARM64
pgprot_writecombine() is mapped to memory-type MT_NORMAL_NC which
has no side effects on reads and multiple writes can be combined.
Signed-off-by: Shanker Donthin
ends on the flag VM_PFNMAP in VMA. VFIO-PCI will keep the prefetchable
(write-combine) information in vma->vm_page_prot similar to other fields, and
KVM will prepare stage-2 entries based on the memory-type attribute that was
set in VMA.
Shanker Donthineni (2):
vfio/pci: keep the prefetchable at
type DEVICE_nGnRE for non-WC regions.
Change-Id: Ibaea69c7a301df3c86609e871f6d066728391080
Signed-off-by: Shanker Donthineni
---
arch/arm64/include/asm/kvm_mmu.h | 3 ++-
arch/arm64/include/asm/kvm_pgtable.h | 2 ++
arch/arm64/include/asm/memory.h | 4 +++-
arch/arm64/kvm/hyp
Hi Will,
On 03/09/2018 07:48 AM, Will Deacon wrote:
> Hi SHanker,
>
> On Mon, Mar 05, 2018 at 11:06:43AM -0600, Shanker Donthineni wrote:
>> The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC
>> V1.1 Calling Convention to mitigate CVE-2017-5715. This patch
Hi Will,
On 03/06/2018 09:25 AM, Will Deacon wrote:
> On Mon, Mar 05, 2018 at 12:03:33PM -0600, Shanker Donthineni wrote:
>> On 03/05/2018 11:15 AM, Will Deacon wrote:
>>> On Mon, Mar 05, 2018 at 10:57:58AM -0600, Shanker Donthineni wrote:
>>>> On 03/05/20
org>
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
Changes since v6:
-Both I-Cache and D-Cache changes are symmetric as Will suggested.
-Remove Kconfig option.
-Patch __flush_icache_all().
Changes since v5:
-Addressed Mark's review comments.
Changes since v4:
-Moved patc
Hi Will,
On 03/06/2018 12:48 PM, Shanker Donthineni wrote:
> Hi Will,
>
> On 03/06/2018 09:23 AM, Will Deacon wrote:
>> Hi Shanker,
>>
>> On Tue, Mar 06, 2018 at 08:47:27AM -0600, Shanker Donthineni wrote:
>>> On 03/06/2018 07:44 AM, Will Deacon wrote:
>
Hi Will,
On 03/06/2018 09:23 AM, Will Deacon wrote:
> Hi Shanker,
>
> On Tue, Mar 06, 2018 at 08:47:27AM -0600, Shanker Donthineni wrote:
>> On 03/06/2018 07:44 AM, Will Deacon wrote:
>>> I think this is a slight asymmetry with the code for the I-side. On
Hi Will
On 03/06/2018 07:44 AM, Will Deacon wrote:
> Hi Shanker,
>
> On Wed, Feb 28, 2018 at 10:14:00PM -0600, Shanker Donthineni wrote:
>> The DCache clean & ICache invalidation requirements for instructions
>> to be data coherence are discoverable thro
Hi Will,
On 03/05/2018 11:15 AM, Will Deacon wrote:
> On Mon, Mar 05, 2018 at 10:57:58AM -0600, Shanker Donthineni wrote:
>> Hi Will,
>>
>> On 03/05/2018 09:56 AM, Will Deacon wrote:
>>> Hi Shanker,
>>>
>>> On Fri, Mar 02, 2018 at 03:50:18PM -0
The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC
V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses
the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead
of Silicon provider service ID 0xC2001700.
Signed-off-by: Shanker Donthineni <sh
Hi Will,
On 03/05/2018 09:56 AM, Will Deacon wrote:
> Hi Shanker,
>
> On Fri, Mar 02, 2018 at 03:50:18PM -0600, Shanker Donthineni wrote:
>> The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC
>> V1.1 Calling Convention to mitigate CVE-2017-5715. This patch
The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC
V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses
the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead
of Silicon provider service ID 0xC2001700.
Signed-off-by: Shanker Donthineni <sh
org>
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
Changes since v5:
-Addressed Mark's review comments.
Changes since v4:
-Moved patching ARM64_HAS_CACHE_DIC inside invalidate_icache_by_line
-Removed 'dsb ishst' for ARM64_HAS_CACHE_DIC as Mark suggested.
Changes since v
org>
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
Changes since v4:
-Moved patching ARM64_HAS_CACHE_DIC inside invalidate_icache_by_line
-Removed 'dsb ishst' for ARM64_HAS_CACHE_DIC as Mark suggested.
Changes since v3:
-Added preprocessor guard CONFIG_xxx to code snippe
org>
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
Changes since v3:
-Added preprocessor guard CONFIG_xxx to code snippets in cache.S
-Changed barrier attributes from ISH to ISHST.
Changes since v2:
-Included barriers, DSB/ISB with DIC set, and DSB with IDC set.
-Single
Hi Mark,
On 02/21/2018 09:09 AM, Mark Rutland wrote:
> On Wed, Feb 21, 2018 at 07:49:06AM -0600, Shanker Donthineni wrote:
>> The DCache clean & ICache invalidation requirements for instructions
>> to be data coherence are discoverable through new fields in CTR_EL0.
>>
org>
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
Changes since v2:
-Included barriers, DSB/ISB with DIC set, and DSB with IDC set.
-Single Kconfig option.
Changes since v1:
-Reworded commit text.
-Used the alternatives framework as Catalin suggested.
Hi Catalin,
On 02/21/2018 05:12 AM, Catalin Marinas wrote:
> On Mon, Feb 19, 2018 at 08:59:06PM -0600, Shanker Donthineni wrote:
>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
>> index f55fe5b..4061210 100644
>> --- a/arch/arm64/Kconfig
>> +++ b/arch/arm64/Kco
org>
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
Changes since v1:
-Reworded commit text.
-Used the alternatives framework as Catalin suggested.
-Rebased on top of https://patchwork.kernel.org/patch/10227927/
arch/arm64/Kconfig | 21 +++
arch/a
Thanks Catalin for your comments.
On 02/19/2018 11:18 AM, Catalin Marinas wrote:
> On Mon, Feb 19, 2018 at 10:35:30AM -0600, Shanker Donthineni wrote:
>> On 02/19/2018 08:38 AM, Catalin Marinas wrote:
>>> On the patch, I'd rather have an alternative framework entry for no V
Hi Will,
On 02/19/2018 08:43 AM, Will Deacon wrote:
> Hi Shanker,
>
> On Fri, Feb 16, 2018 at 06:57:46PM -0600, Shanker Donthineni wrote:
>> Two point of unification cache maintenance operations 'DC CVAU' and
>> 'IC IVAU' are optional for implementors as per ARMv8 specifi
Hi Catalin,
On 02/19/2018 08:38 AM, Catalin Marinas wrote:
> On Fri, Feb 16, 2018 at 06:57:46PM -0600, Shanker Donthineni wrote:
>> Two point of unification cache maintenance operations 'DC CVAU' and
>> 'IC IVAU' are optional for implementors as per ARMv8 specification.
>&
.
— CNTVCT is read from Non-secure EL0.
So, no need to zero CNTVOFF_EL2/CNTVOFF for VHE case.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
virt/kvm/arm/arch_timer.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/virt/kvm/arm/arch_timer.c b/virt/k
== 0b000
or (CLIDR_EL1.LoUIS == 0b000 && CLIDR_EL1.LoUU == 0b000).
1: Data cache clean to the point of unification is not required
for instruction to data coherence.
Signed-off-by: Philip Elcan <pel...@codeaurora.org>
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org
References to CPU part number MIDR_QCOM_FALKOR were dropped from the
mailing list patch due to mainline/arm64 branch dependency. So this
patch adds the missing part number.
Fixes: ec82b567a74f ("arm64: Implement branch predictor hardening for Falkor")
Signed-off-by: Shanker Donthin
Hi Will, Thanks for your quick reply.
On 02/01/2018 04:33 AM, Will Deacon wrote:
> Hi Shanker,
>
> On Wed, Jan 31, 2018 at 06:03:42PM -0600, Shanker Donthineni wrote:
>> A DMB instruction can be used to ensure the relative order of only
>> memory accesses before and aft
ensures that no instructions that appear in program
order after the DSB instruction, can execute until the DSB instruction
has completed.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
drivers/irqchip/irq-gic-v3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
able in upstream v4.15-rc7
branch. Please merge v2 patch.
On 01/08/2018 01:10 PM, Shanker Donthineni wrote:
> Hi Will,
>
> On 01/08/2018 12:44 PM, Will Deacon wrote:
>> On Mon, Jan 08, 2018 at 05:09:33PM +, Will Deacon wrote:
>>> On Fri, Jan 05, 2018 at 02:28:59PM -06
-by: Shanker Donthineni <shank...@codeaurora.org>
Signed-off-by: Will Deacon <will.dea...@arm.com>
---
This patch is availble at
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch/arm64?h=v4.15-rc7=c622cc013cece073722592cff1ac6643a33b1622
arch/arm64/include/a
Falkor is susceptible to branch predictor aliasing and can
theoretically be attacked by malicious code. This patch
implements a mitigation for these attacks, preventing any
malicious entries from affecting other victim contexts.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.
Hi Will,
On 01/08/2018 12:44 PM, Will Deacon wrote:
> On Mon, Jan 08, 2018 at 05:09:33PM +, Will Deacon wrote:
>> On Fri, Jan 05, 2018 at 02:28:59PM -0600, Shanker Donthineni wrote:
>>> Falkor is susceptible to branch predictor aliasing and can
>>> theoretically be
Falkor is susceptible to branch predictor aliasing and can
theoretically be attacked by malicious code. This patch
implements a mitigation for these attacks, preventing any
malicious entries from affecting other victim contexts.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.
to 0 when HCR_EL2[VM] has a value of 1).
To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
Changes since v3:
Rebased to kernel v4.
-by: Shanker Donthineni <shank...@codeaurora.org>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d..cbf08d7 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch
Thanks Mark, I'll post v5 patch without alternatives.
On 12/11/2017 04:45 AM, Mark Rutland wrote:
> Hi,
>
> On Sun, Dec 10, 2017 at 08:03:43PM -0600, Shanker Donthineni wrote:
>> +/**
>> + * Errata workaround prior to disable MMU. Insert an ISB immediately prior
>&g
to 0 when HCR_EL2[VM] has a value of 1).
To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
Changes since v3:
Rebased to kernel v4.
-by: Shanker Donthineni <shank...@codeaurora.org>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d..cbf08d7 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch
Hi Will,
On 12/03/2017 07:35 AM, Shanker Donthineni wrote:
> Hi Will, thanks for your review comments.
>
> On 12/01/2017 05:24 AM, Will Deacon wrote:
>> On Mon, Nov 27, 2017 at 05:18:00PM -0600, Shanker Donthineni wrote:
>>> The ARM architecture defines the memory loca
Hi Will, thanks for your review comments.
On 12/01/2017 05:24 AM, Will Deacon wrote:
> On Mon, Nov 27, 2017 at 05:18:00PM -0600, Shanker Donthineni wrote:
>> The ARM architecture defines the memory locations that are permitted
>> to be accessed as the result of a speculative in
series got dropped to accommodate review comments. Apply
the workaround where it's required.
Posted wrong the patches in v2.
Shanker Donthineni (2):
arm64: Define cputype macros for Falkor CPU
arm64: Add software workaround for Falkor erratum 1041
Documentation/arm64/silicon-errata.txt | 1
-by: Shanker Donthineni <shank...@codeaurora.org>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d..cbf08d7 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch
to 0 when HCR_EL2[VM] has a value of 1).
To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
Changes since v3:
Rebased to kernel v4.
Hi,
Sorry, I've posted a wrong patch which causes the compilation errors.
Please disregard this patch, I posted v3 patch to fix the build
issue.
https://patchwork.kernel.org/patch/10055077/
On 11/12/2017 07:16 PM, Shanker Donthineni wrote:
> The ARM architecture defines the memory locati
-by: Shanker Donthineni <shank...@codeaurora.org>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d..cbf08d7 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch
to 0 when HCR_EL2[VM] has a value of 1).
To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
Changes since v1:
Apply the workaround wher
E1041.
Shanker Donthineni (2):
arm64: Define cputype macros for Falkor CPU
arm64: Add software workaround for Falkor erratum 1041
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 10 ++
arch/arm64/include/asm/assembler.h | 18
SCTLR_ELn[M] is changed to 0 to fix the
Falkor erratum 1041.
Patch2 from V1 series got dropped to accommodate review comments. Apply
the workaround where it's required.
Patch1:
- CPUTYPE definitions for Falkor CPU.
Patch2:
- Actual workaround changes for erratum E1041.
Shanker Donthineni (2
to 0 when HCR_EL2[VM] has a value of 1).
To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
Documentation/arm64/silicon-errata.txt | 1 +
-by: Shanker Donthineni <shank...@codeaurora.org>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d..cbf08d7 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch
Hi James,
On 11/10/2017 04:24 AM, James Morse wrote:
> Hi Shanker,
>
> On 09/11/17 15:22, Shanker Donthineni wrote:
>> On 11/09/2017 05:08 AM, James Morse wrote:
>>> On 04/11/17 21:43, Shanker Donthineni wrote:
>>>> On 11/03/2017 10:11 AM, Robin Murphy wro
Hi James,
On 11/09/2017 05:08 AM, James Morse wrote:
> Hi Shanker, Robin,
>
> On 04/11/17 21:43, Shanker Donthineni wrote:
>> On 11/03/2017 10:11 AM, Robin Murphy wrote:
>>> On 03/11/17 03:27, Shanker Donthineni wrote:
>>>> The ARM architecture defines the
Hi Robin, Thanks for your review comments.
On 11/03/2017 10:11 AM, Robin Murphy wrote:
> On 03/11/17 03:27, Shanker Donthineni wrote:
>> The ARM architecture defines the memory locations that are permitted
>> to be accessed as the result of a speculative instruction fetch from
to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 10 ++
arch/arm64/include/asm/assembler.h | 17 +
arch
SCTLR_ELn[M] is changed to 0 to fix the
Falkor erratum 1041.
Patch1:
- CPUTYPE definitions for Falkor CPU.
Patch2:
- Define two ASM helper macros to read/write SCTLR_ELn register.
Patch3:
- Actual workaround changes for erratum E1041.
Shanker Donthineni (3):
arm64: Define cputype macros
-by: Shanker Donthineni <shank...@codeaurora.org>
Signed-off-by: Neil Leeder <nlee...@codeaurora.org>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d..cbf08d7 10064
This patch introduces two helper macros read_sctlr and write_sctlr
to access system register SCTLR_ELn. Replace all MSR/MRS references
to sctlr_el1{el2} with macros.
This should cause no behavioral change.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
arch/arm64/inclu
Hi Marc,
I've tested this patch series on QDF2400 server platform using NVME card, the
basic
functionality works fine and the below log messages shows around 70 interrupts
are delivered to vCPU directly.
Tested-by: Shanker Donthineni <shank...@codeaurora.org>
>From guest kernel:
/
/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
arch/arm64/include/asm/esr.h | 4
arch/arm64/kvm/handle_exit.c | 12 +++-
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/arch
then we don't advertise KVM_CAP_MSI_DEVID capability.
Update the field msis_require_devid to true inside vgic_its_create()
to fix the issue.
Fixes: 0e4e82f154e3 ("vgic-its: Enable ITS emulation as a virtual MSI
controller")
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
s_gicv4 && vgic_has_its(kvm))
> + vgic_v4_teardown(kvm);
> }
>
> void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu)
>
--
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm Technologies, Inc. is
after reviewing giant v2 series.
Tested-by: Shanker Donthineni <shank...@codeaurora.org>
-Original Message-
From: linux-arm-kernel [mailto:linux-arm-kernel-boun...@lists.infradead.org]
On Behalf Of Marc Zyngier
Sent: Wednesday, June 28, 2017 10:03 AM
To: linux-ker...@vger.kernel.org;
anyway I
> understand this will force the HW to read the LPI pending table.
It's not a good idea to set PendLast bit always. There is no correctness issue
but causes a huge impact on the system performance. No need to read pending
table contents from memory if
Hi Marc,
On 03/06/2017 02:34 AM, Marc Zyngier wrote:
Hi Shanker,
On Mon, Mar 06 2017 at 2:33:18 am GMT, Shanker Donthineni
<shank...@codeaurora.org> wrote:
Now all the cpu_hwcaps features have their own static keys. We don't
need a separate function hyp_alternate_select() to patch t
the better code with a fewer instructions.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
v2: removed 'Change-Id: Ia8084189833f2081ff13c392deb5070c46a64038' from commit
arch/arm64/kvm/hyp/debug-sr.c | 12 ++
arch/arm64/kvm/hyp/switch.c
the better code with a fewer instructions.
Change-Id: Ia8084189833f2081ff13c392deb5070c46a64038
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
arch/arm64/kvm/hyp/debug-sr.c | 12 ++
arch/arm64/kvm/hyp/switch.c| 50 +++---
+
+/*
* ITS registers, offsets from ITS_base
*/
#define GITS_CTLR 0x
--
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux
Foundati
ce_ids - 1, 0);
How do we know this 'devid' is not being used by real hardware devices?
I think we need some kind check in its_msi_prepare() to skip this device
or WARN.
Unfortunately Qualcomm doesn't support Direct LPI feature.
--
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an af
lt;< 62)
+#define GICR_PENDBASER_Valid (1ULL << 63)
+
+/*
* ITS registers, offsets from ITS_base
*/
#define GITS_CTLR 0x
--
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.
Qua
_CTLR.RWP == 0.
--
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux
Foundation Collaborative Project.
___
kvmarm maili
(GFP_KERNEL);
+ if (vpt_page) {
Change to 'if (!vpt_page)'.
--
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux
return 0;
+ }
+
+ case PROP_UPDATE_VLPI:
+ {
+ return 0;
+ }
+
+ default:
+ return -EINVAL;
+ }
Missing a return statement.
--
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm Te
would easier to enable 24bit LPI later.
Actually Qualcomm server chips support 24bit IDBITS.
--
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux
Foundation Collabo
);
err = its_setup_baser(its, baser, cache, shr, psz, order,
indirect);
if (err < 0) {
--
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Au
goto out_free_its;
+ }
+
+ pr_info("ITS@%pa: Using ITS number %d\n", >start,
its_number);
+ } else {
+ pr_info("ITS@%pa: Single VMOVP capable\n", >start);
+ }
Can we move to a separate function for code readability purp
pi &= !!(typer &
GICR_TYPER_DirectLPIS);
+
+ return 1;
+}
+
+static void gic_update_vlpi_properties(void)
+{
+ gic_scan_rdist_properties(__gic_update_vlpi_properties);
+ pr_info("%sVLPI support, %sdirect LPI support\n",
Would be better if we keep one space after 'no'?
return 0;
+
/* We couldn't even deal with ourselves... */
WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
-smp_processor_id(), mpidr);
+smp_processor_id(),
+ (unsigned long)cpu_logical_map(smp_processor_id()));
validation checks. No need
to call the function vgic_its_inject_msi() second time to avoid
an unnecessary overhead in IRQ queue logic. It also avoids the
possibility of VM seeing the MSI twice.
Simple fix, return -1 if the argument 'level' value is zero.
Signed-off-by: Shanker Donthineni <sh
in tpidr_el2. The function __guest_exit()
calling convention is slightly modified, caller only pushes the regs
x0-x1 to stack instead of regs x0-x3.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org>
---
Tested this
Hi Marc,
On 08/30/2016 05:54 AM, Marc Zyngier wrote:
On 30/08/16 10:55, Christoffer Dall wrote:
On Mon, Aug 29, 2016 at 10:51:14PM -0500, Shanker Donthineni wrote:
We are doing an unnecessary stack push/pop operation when restoring
the guest registers x0-x18 in __guest_enter(). This patch
in tpidr_el2. The function __guest_exit()
prototype is simplified and caller pushes the regs x0-x1 to stack
instead of regs x0-x3.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
Changes since v1:
Incorporated Cristoffer suggestions.
__guest_exit prototype is changed to
, Shanker Donthineni wrote:
We are doing an unnecessary stack push/pop operation when restoring
the guest registers x0-x18 in __guest_enter(). This patch saves the
two instructions by using x18 as a base register. No need to store
the vcpu context pointer in stack because it is redundant
information is available in tpidr_el2.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
---
arch/arm64/kvm/hyp/entry.S | 66 ++
1 file changed, 32 insertions(+), 34 deletions(-)
diff --git a/arch/arm64/kvm/hyp/entry.S b/arch/arm64/k
your board.
>
> Regards,
>
--
Shanker Donthineni
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux
Foundation Collaborative Project
___
kvmarm mailing
020
> 8003ffe14010
>> 3fe0: 0a482550 8003c040 0800f000
> 8003c0403a30
>> 4000: 8003c0403b50 8003c0403a30
>
>> 4020:
>
On 04/11/2016 10:33 AM, Julien Grall wrote:
> The only call of arch_timer_get_timecounter (in KVM) has been removed.
>
> Signed-off-by: Julien Grall <julien.gr...@arm.com>
> Acked-by: Christoffer Dall <christoffer.d...@linaro.org>
Tested-by: Shanker Donthineni <shan
newly function
> arch_timer_get_kvm_info()
> which return all the information required by the virtual timer code.
>
> Signed-off-by: Julien Grall <julien.gr...@arm.com>
> Acked-by: Christoffer Dall <christoffer.d...@linaro.org>
>
Tested-by: Shanker Donthineni <shank...@codeaurora.org&
er <ja...@lakedaemon.net>
> Cc: Marc Zyngier <marc.zyng...@arm.com>
>
Tested-by: Shanker Donthineni <shank...@codeaurora.org>
Using the Qualcomm Technologies QDF2XXX server platform.
--
Shanker Donthineni
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc
Dall <christoffer.d...@linaro.org>
> Reviewed-by: Hanjun Guo <hanjun@linaro.org>
>
Tested-by: Shanker Donthineni <shank...@codeaurora.org>
Using the Qualcomm Technologies QDF2XXX server platform.
--
Shanker Donthineni
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovat
t; Introduce a new structure and set of helpers to get/set the virtual GIC
> information. Also fill up the structure for GICv2.
>
> Signed-off-by: Julien Grall <julien.gr...@arm.com>
>
Tested-by: Shanker Donthineni <shank...@codeaurora.org>
Using the Qualcomm Technolo
fic, gather all the
> information in a single structure.
>
> Signed-off-by: Julien Grall <julien.gr...@arm.com>
> Acked-by: Christofer Dall <christoffer.d...@linaro.org>
> Acked-by: Hanjun Guo <hanjun....@linaro.org>
>
Tested-by: Shanker Donthineni <shank...@codeauror
kvm_info to get the virtual
> IRQ.
>
> Note that the KVM code will be modified in a subsequent patch.
>
> Signed-off-by: Julien Grall <julien.gr...@arm.com>
> Acked-by: Christoffer Dall <christoffer.d...@linaro.org>
>
Tested-by: Shanker Donthineni <shank...@codeaurora.o
y: Christoffer Dall <christoffer.d...@linaro.org>
>
Tested-by: Shanker Donthineni <shank...@codeaurora.org>
Using the Qualcomm Technologies QDF2XXX server platform.
> ---
> Cc: Daniel Lezcano <daniel.lezc...@linaro.org>
> Cc: Thomas Gleixner <t...@linutronix.de&
q = irq;
>>> +
>>> +if (acpi_data.vcpu_base) {
>>
>> Sorry, I'm not familiar with KVM, but I got a question here, will
>> KVM works without valid vcpu_base in GICv3 mode?
>
Yes, KVM works without vcpu_base in GICv3 mode. The vcpu_base will be used
for emu
_info);
> +}
>
> static int __init
> gic_acpi_init(struct acpi_subtable_header *header, const unsigned long
> end)
> @@ -1159,6 +1265,8 @@ gic_acpi_init(struct acpi_subtable_header *header,
> const unsigned long end)
>
On 03/03/2016 08:03 AM, Marc Zyngier wrote:
> On 03/03/16 13:25, Shanker Donthineni wrote:
>>
>> On 03/02/2016 11:35 AM, Marc Zyngier wrote:
>>> On 02/03/16 15:48, Shanker Donthineni wrote:
>>>
>>>> We haven't started running heavy workloads in VMs. S
On 03/02/2016 09:09 AM, Marc Zyngier wrote:
> On 02/03/16 14:59, Shanker Donthineni wrote:
>> Hi Marc,
>>
>> Thanks for your quick reply.
>>
>> On 03/02/2016 08:16 AM, Marc Zyngier wrote:
>>> On 02/03/16 13:56, Shanker Donthineni wrote:
>>
Hi Marc,
Thanks for your quick reply.
On 03/02/2016 08:16 AM, Marc Zyngier wrote:
On 02/03/16 13:56, Shanker Donthineni wrote:
For some reason v4.5-rc6 kernel is not stable for guest machines on
Qualcomm server platforms.
We are getting IABT translation faults while booting the guest kernel
an_flat_dt+0x9c/0xd0
[0.00] pc : [] lr : []
pstate: 83c5
[0.00] sp : ffc000d47e80
[0.00] x29: ffc000d47e80 x28: 00000000
--
Shanker Donthineni
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc.
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