Zyngier
+R: James Morse
+R: Julien Thierry
+R: Suzuki Pouloze
Please note that it is: "Suzuki K Poulose"
With that:
Acked-by: Suzuki K Poulose
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On 04/02/2019 16:53, Andrew Murray wrote:
The kvm_pmu_{enable/disable}_counter functions can enabled/disable
multiple counters at once as they operate on a bitmask. Let's
make this clearer by renaming the function.
Signed-off-by: Andrew Murray
Suggested-by: Suzuki K Poulose
Review
On 02/02/2019 10:50, kbuild test robot wrote:
tree: https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git master
head: a7d7d3ebc7d441ee48e1fd87d9a8abbf7d528127
commit: 4cc936fd184a2641801c906ea320326317895397 [7/8] KVM: arm64: Relax the
restriction on using stage2 PUD huge map
Marc,
On 30/01/2019 10:21, Marc Zyngier wrote:
On 29/01/2019 19:12, Suzuki K Poulose wrote:
We restrict mapping the PUD huge pages in stage2 to only when the
stage2 has 4 level page table, leaving the feature unused with
the default IPA size. But we could use it even with a 3
level page table
using the
PUD huge page mappings at stage2 when it is possible.
Cc: Christoffer Dall
Cc: Marc Zyngier
Signed-off-by: Suzuki K Poulose
---
virt/kvm/arm/mmu.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
index fbdf3ac
On 28/01/2019 14:28, Andrew Murray wrote:
On Tue, Jan 22, 2019 at 10:12:22PM +, Suzuki K Poulose wrote:
Hi Andrew,
On 01/22/2019 10:49 AM, Andrew Murray wrote:
To prevent re-creating perf events everytime the counter registers
are changed, let's instead lazily create the event whe
Hi Andrew,
On 28/01/2019 11:47, Andrew Murray wrote:
On Tue, Jan 22, 2019 at 02:18:17PM +, Suzuki K Poulose wrote:
Hi Andrew
On 01/22/2019 10:49 AM, Andrew Murray wrote:
The perf event sample_period is currently set based upon the current
counter value, when PMXEVTYPER is written to and
Hi Andrew,
On 01/22/2019 10:49 AM, Andrew Murray wrote:
To prevent re-creating perf events everytime the counter registers
are changed, let's instead lazily create the event when the event
is first enabled and destroy it when it changes.
Signed-off-by: Andrew Murray
---
virt/kvm/arm/pmu.
On 01/22/2019 10:49 AM, Andrew Murray wrote:
Let's reduce code duplication by extracting common code to its own
function.
Signed-off-by: Andrew Murray
---
Reviewed-by: Suzuki K Poulose
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Hi Andrew
On 01/22/2019 10:49 AM, Andrew Murray wrote:
The perf event sample_period is currently set based upon the current
counter value, when PMXEVTYPER is written to and the perf event is created.
However the user may choose to write the type before the counter value in
which case sample_peri
On 10/01/2019 15:16, Andrew Murray wrote:
On Thu, Jan 10, 2019 at 11:36:01AM +, Suzuki K Poulose wrote:
Hi Andrew,
On 07/01/2019 14:41, Andrew Murray wrote:
The virt/arm core allocates a kvm_cpu_context_t percpu, at present this is
a typedef to kvm_cpu_context and is used to store host
make this explicitly load
the address of the host_ctxt member to make sure this doesn't break
with future changes to the structure ?
i.e,
add \reg, \reg, #HOST_DATA_CONTEXT
Otherwise,
Reviewed-by: Suzuki K Poulose
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On 12/12/2018 10:29, Andrew Murray wrote:
In order to effeciently enable/disable guest/host only perf counters
at guest entry/exit we add bitfields to kvm_cpu_context for guest and
host events as well as accessors for updating them.
Signed-off-by: Andrew Murray
Reviewed-by: Suzuki K
}
It may be helpful to add in a comment why we do this only for !exclude_host.
Either way,
Reviewed-by: Suzuki K Poulose
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set:
events_guest & ~events_host
Either way:
Reviewed-by: Suzuki K Poulose
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On 12/12/2018 10:47, Julien Thierry wrote:
On 12/12/2018 10:42, Suzuki K Poulose wrote:
On 12/12/2018 10:29, Andrew Murray wrote:
Add support for the :G and :H attributes in perf by handling the
exclude_host/exclude_guest event attributes.
We notify KVM of counters that we wish to be
On 12/12/2018 10:29, Andrew Murray wrote:
Add support for the :G and :H attributes in perf by handling the
exclude_host/exclude_guest event attributes.
We notify KVM of counters that we wish to be enabled or disabled on
guest entry/exit and thus defer from starting or stopping :G events
as pe
Hi Andrew,
On 12/12/2018 10:29, Andrew Murray wrote:
The virt/arm core allocates a kvm_cpu_context_t percpu, at present this is
a typedef to kvm_cpu_context and is used to store host cpu context. The
kvm_cpu_context structure is also used elsewhere to hold vcpu context.
In order to use the percp
From: Punit Agrawal
KVM only supports PMD hugepages at stage 2. Now that the various page
handling routines are updated, extend the stage 2 fault handling to
map in PUD hugepages.
Addition of PUD hugepage support enables additional page sizes (e.g.,
1G with 4K granule) which can be useful on cor
King
Cc: Catalin Marinas
Cc: Will Deacon
[ Replaced BUG() => WARN_ON(1) for arm32 PUD helpers ]
Signed-off-by: Suzuki K Poulose
---
arch/arm/include/asm/kvm_mmu.h | 6 ++
arch/arm64/include/asm/kvm_mmu.h | 5 +
arch/arm64/include/asm/pgtable.h | 1 +
virt/kvm/arm/mm
This series is an update to the PUD hugepage support previously posted
at [0]. This patchset adds support for PUD hugepages at stage 2 a
feature that is useful on cores that have support for large sized TLB
mappings (e.g., 1GB for 4K granule).
The patches are based on v4.20-rc4
The patches have b
* helpers
to allow sharing of code with arm32.
Signed-off-by: Punit Agrawal
Reviewed-by: Christoffer Dall
Cc: Marc Zyngier
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
[ Replaced BUG() => WARN_ON() in arm32 pud helpers ]
Signed-off-by: Suzuki K Poulose
---
arch/arm/include/asm/kvm_mm
implementations of arm32 helpers to allow sharing of
code.
Signed-off-by: Punit Agrawal
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
[ Replaced BUG() => WARN_ON(1) in arm32 PUD helpers ]
Signed-off-by: Suzuki K Poulose
---
arch/arm/include/asm/kvm_mm
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
[ Replaced BUG() => WARN_ON(1) in PUD helpers ]
Signed-off-by: Suzuki K Poulose
---
arch/arm/include/asm/kvm_mmu.h | 9 +
arch/arm64/include/asm/kvm_mmu.h | 7 +++
arch/arm64/include/asm/pgtable.h | 6 ++
virt/kvm/
them across the different pagesizes.
Signed-off-by: Punit Agrawal
Reviewed-by: Suzuki K Poulose
Cc: Christoffer Dall
Cc: Marc Zyngier
Signed-off-by: Suzuki K Poulose
---
virt/kvm/arm/mmu.c | 49 ++---
1 file changed, 30 insertions(+), 19 deletions(-)
avoid creating another copy
when support for PUD hugepages is introduced refactor the code to
share the checks needed to mark a page table entry as executable.
Signed-off-by: Punit Agrawal
Reviewed-by: Suzuki K Poulose
Cc: Christoffer Dall
Cc: Marc Zyngier
Signed-off-by: Suzuki K Poulose
not exist on arm.
Signed-off-by: Punit Agrawal
Reviewed-by: Suzuki K Poulose
Acked-by: Christoffer Dall
Cc: Marc Zyngier
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Suzuki K Poulose
---
arch/arm/include/asm/kvm_mmu.h | 5 +
arch/arm64/include/asm/kvm_mmu.h | 5
On 11/12/2018 12:13, Andrew Murray wrote:
The virt/arm core allocates a percpu structure as per the kvm_cpu_context_t
type, at present this is typedef'd to kvm_cpu_context and used to store
host cpu context. The kvm_cpu_context structure is also used elsewhere to
hold vcpu context. In order to
On 10/12/2018 08:56, Christoffer Dall wrote:
On Mon, Dec 03, 2018 at 01:37:37PM +, Suzuki K Poulose wrote:
Hi Anshuman,
On 03/12/2018 12:11, Anshuman Khandual wrote:
On 10/31/2018 11:27 PM, Punit Agrawal wrote:
The code for operations such as marking the pfn as dirty, and
dcache
On 10/12/2018 08:56, Christoffer Dall wrote:
On Mon, Dec 03, 2018 at 01:37:37PM +, Suzuki K Poulose wrote:
Hi Anshuman,
On 03/12/2018 12:11, Anshuman Khandual wrote:
On 10/31/2018 11:27 PM, Punit Agrawal wrote:
The code for operations such as marking the pfn as dirty, and
dcache
---
arch/arm64/kvm/hyp/switch.c | 38 ++
1 file changed, 38 insertions(+)
Reviewed-by: Suzuki K Poulose
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On 06/12/2018 19:21, Andrew Murray wrote:
On Thu, Dec 06, 2018 at 06:51:37PM +, Suzuki K Poulose wrote:
On 06/12/2018 17:21, Suzuki K Poulose wrote:
Hi Andrew,
On 05/12/2018 15:30, Andrew Murray wrote:
In order to effeciently enable/disable guest/host only perf counters
at guest
On 06/12/2018 17:21, Suzuki K Poulose wrote:
Hi Andrew,
On 05/12/2018 15:30, Andrew Murray wrote:
In order to effeciently enable/disable guest/host only perf counters
at guest entry/exit we add bitfields to kvm_cpu_context for guest and
host events as well as accessors for updating them
is set
on non-VHE then there is a small blackout window at the guest
entry/exit where host events are not captured.
Signed-off-by: Andrew Murray
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Reviewed-by: Suzuki K Poulose
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Hi Andrew,
On 05/12/2018 15:30, Andrew Murray wrote:
In order to effeciently enable/disable guest/host only perf counters
at guest entry/exit we add bitfields to kvm_cpu_context for guest and
host events as well as accessors for updating them.
Signed-off-by: Andrew Murray
---
arch/arm64/incl
entries is used to perform
i-cache invalidation on first execute.
Provide trivial implementations of arm32 helpers to allow sharing of
code.
Signed-off-by: Punit Agrawal
Reviewed-by: Suzuki K Poulose
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
the page should be marked executable is
duplicated for PMD and PTE entries. To avoid creating another copy
when support for PUD hugepages is introduced refactor the code to
share the checks needed to mark a page table entry as executable.
Signed-off-by: Punit Agrawal
Reviewed-by: Suzuki K Poulose
migrating
VMs.
Also, provide trivial implementations of required kvm_s2pud_* helpers
to allow sharing of code with arm32.
Signed-off-by: Punit Agrawal
Reviewed-by: Christoffer Dall
Reviewed-by: Suzuki K Poulose
Cc: Marc Zyngier
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm
Hi Anshuman,
On 03/12/2018 13:50, Anshuman Khandual wrote:
On 10/31/2018 11:27 PM, Punit Agrawal wrote:
Introduce helpers to abstract architectural handling of the conversion
of pfn to page table entries and marking a PMD page table entry as a
block entry.
Why is this necessary ? we would s
creating another copy of the operations when we introduce
PUD hugepages, let's share them across the different pagesizes.
Signed-off-by: Punit Agrawal
Reviewed-by: Suzuki K Poulose
Cc: Christoffer Dall
Cc: Marc Zyngier
---
virt/kvm/arm/mmu.c | 49 -
On 21/11/2018 13:23, Andrew Murray wrote:
On Wed, Nov 21, 2018 at 10:56:02AM +, Andrew Murray wrote:
On Tue, Nov 20, 2018 at 02:49:05PM +, Suzuki K Poulose wrote:
On 11/20/2018 02:15 PM, Andrew Murray wrote:
Add support for the :G and :H attributes in perf by handling the
On 11/20/2018 02:15 PM, Andrew Murray wrote:
Add support for the :G and :H attributes in perf by handling the
exclude_host/exclude_guest event attributes.
We notify KVM of counters that we wish to be enabled or disabled on
guest entry/exit and thus defer from starting or stopping :G events
as pe
if (armv8pmu_event_is_chained(event))
armv8pmu_enable_counter(idx - 1);
- isb();
}
static inline int armv8pmu_disable_counter(int idx)
Reviewed-by: Suzuki K Poulose
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On 16/11/2018 12:12, Andrew Murray wrote:
On Thu, Nov 15, 2018 at 05:40:24PM +, Suzuki K Poulose wrote:
On 15/11/2018 15:57, Andrew Murray wrote:
On Thu, Nov 15, 2018 at 02:00:39PM +, Julien Thierry wrote:
Hi Andrew,
On 15/11/18 12:55, Andrew Murray wrote:
Enable/disable event
On 15/11/2018 15:57, Andrew Murray wrote:
On Thu, Nov 15, 2018 at 02:00:39PM +, Julien Thierry wrote:
Hi Andrew,
On 15/11/18 12:55, Andrew Murray wrote:
Enable/disable event counters as appropriate when entering and exiting
the guest to enable support for guest or host only event counti
Hi Andrew,
On 15/11/2018 12:55, Andrew Murray wrote:
When using VHE, EL1 is unused by the host and EL2 is unused by the
guest - therefore we can filter out these events with the PMU as per
the 'exclude_host' and 'exclude_guest' attributes.
With both VHE and non-VHE we switch the counters betwee
ber of page table levels required for
+ * IPA_SHIFT at stage2 expected by the hardware can be calculated using
+ * the same logic used for the (non-collapsable) stage1 page tables but for
+ * (IPA_SHIFT - 4).
Thanks for cleaning up the mess. With the above changes :
Reviewed-by: Suzuk
On 06/11/2018 11:45, Christoffer Dall wrote:
On Tue, Nov 06, 2018 at 09:52:59AM +, Suzuki K Poulose wrote:
On 06/11/2018 08:42, Christoffer Dall wrote:
On Mon, Nov 05, 2018 at 03:00:34PM +, Suzuki K Poulose wrote:
On 02/11/18 14:25, Christoffer Dall wrote:
On Fri, Nov 02, 2018
On 06/11/2018 08:42, Christoffer Dall wrote:
On Mon, Nov 05, 2018 at 03:00:34PM +, Suzuki K Poulose wrote:
On 02/11/18 14:25, Christoffer Dall wrote:
On Fri, Nov 02, 2018 at 11:02:38AM +, Suzuki K Poulose wrote:
Hi
On 02/11/18 07:53, Christoffer Dall wrote:
In attempting to re
On 02/11/18 14:25, Christoffer Dall wrote:
On Fri, Nov 02, 2018 at 11:02:38AM +, Suzuki K Poulose wrote:
Hi
On 02/11/18 07:53, Christoffer Dall wrote:
In attempting to re-construct the logic for our stage 2 page table
layout I found the reaoning in the comment explaining how we
Hi Christoffer,
On 02/11/18 13:43, Christoffer Dall wrote:
On Fri, Nov 02, 2018 at 10:26:37AM +, Suzuki K Poulose wrote:
Hi Christoffer,
On 02/11/18 07:53, Christoffer Dall wrote:
There are two things we need to take care of when we create block
mappings in the stage 2 page tables
Hi
On 02/11/18 07:53, Christoffer Dall wrote:
In attempting to re-construct the logic for our stage 2 page table
layout I found the reaoning in the comment explaining how we calculate
the number of levels used for stage 2 page tables a bit backwards.
This commit attempts to clarify the comment,
Hi Christoffer,
On 02/11/18 07:53, Christoffer Dall wrote:
There are two things we need to take care of when we create block
mappings in the stage 2 page tables:
(1) The alignment within a PMD between the host address range and the
guest IPA range must be the same, since otherwise we end
On 01/11/18 08:36, Christoffer Dall wrote:
On Wed, Oct 31, 2018 at 05:55:13PM +, Suzuki K Poulose wrote:
Hi Christoffer,
On 31/10/18 14:22, Christoffer Dall wrote:
On Wed, Sep 26, 2018 at 05:32:54PM +0100, Suzuki K Poulose wrote:
Allow specifying the physical address size limit for a
Hi Christoffer,
On 31/10/18 14:22, Christoffer Dall wrote:
On Wed, Sep 26, 2018 at 05:32:54PM +0100, Suzuki K Poulose wrote:
Allow specifying the physical address size limit for a new
VM via the kvm_type argument for the KVM_CREATE_VM ioctl. This
allows us to finalise the stage2 page table as
; add AA64ISAR1.API HWCAP_CAP; use
sysreg_clear_set]
Signed-off-by: Kristina Martsenko
Tested-by: Adam Wallis
Cc: Catalin Marinas
Cc: Ramana Radhakrishnan
Cc: Suzuki K Poulose
Cc: Will Deacon
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 0dd171c7d71e
ort.
User space will check whether KVM supports vcpu events through
KVM_CAP_VCPU_EVENTS IOCTL.
nit: User space will check whether KVM supports vcpu events by checking
the KVM_CAP_VCPU_EVENTS extension.
Cc: James Morse
Signed-off-by: Dongjiu Geng
Reviewed-by : Suzuki K Poulose
---
For t
Morse
Signed-off-by: Dongjiu Geng
Reviewed-by: Suzuki K Poulose
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D_SIZE) {
pmd_t new_pmd = kvm_pfn_pmd(pfn, mem_type);
new_pmd = kvm_pmd_mkhuge(new_pmd);
Reviewed-by: Suzuki K Poulose
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hugepages, let's share them across the different pagesizes.
Signed-off-by: Punit Agrawal
Cc: Suzuki K Poulose
Cc: Christoffer Dall
Cc: Marc Zyngier
---
Reviewed-by: Suzuki K Poulose
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if we ever add something there in
the future, this caller site could be lost. Is it worth a comment ?
Besides,
Reviewed-by: Suzuki K Poulose
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serve as the backend check
for the vm_type argument. That said, I am fine with the changes, FWIW:
Reviewed-by : Suzuki K Poulose
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Hi Marc,
On 09/28/2018 06:27 PM, Marc Zyngier wrote:
Hi Suzuki,
On 26/09/18 17:32, Suzuki K Poulose wrote:
Allow the arch backends to perform VM specific initialisation.
This will be later used to handle IPA size configuration and per-VM
VTCR configuration on arm64.
Cc: Marc Zyngier
Cc
Specify the physical size for the VM encoded in the vm type.
Signed-off-by: Suzuki K Poulose
---
arm/include/arm-common/kvm-arch.h | 6 +-
arm/kvm.c | 32 +++
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/arm/include/arm
Allow architectures to perform initialisation based on the
KVM device fd ioctls, even before the VM is created.
Signed-off-by: Suzuki K Poulose
---
include/kvm/kvm.h | 4
kvm.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/include/kvm/kvm.h b/include/kvm/kvm.h
index
Add an option to specify the physical address size used by this
VM.
Signed-off-by: Suzuki K Poulose
---
arm/aarch64/include/kvm/kvm-config-arch.h | 5 -
arm/include/arm-common/kvm-config-arch.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arm/aarch64/include/kvm/kvm
check returns the
maximum limit for the physical address shift supported by the host.
Cc: Marc Zyngier
Cc: Christoffer Dall
Cc: Peter Maydell
Cc: Paolo Bonzini
Cc: Radim Krčmář
Signed-off-by: Suzuki K Poulose
---
Changes since v5:
- Rename the capability to KVM_CAP_ARM_VM_IPA_SIZE
- Update
Add support for handling 52bit addresses in PAR to HPFAR
conversion. Instead of hardcoding the address limits, we
now use PHYS_MASK_SHIFT.
Cc: Marc Zyngier
Cc: Christoffer Dall
Reviewed-by: Eric Auger
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/kvm_arm.h | 7 +++
arch
back from the vtcr
field wherever we need it.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/kvm_arm.h| 2 ++
arch/arm64/include/asm/kvm_mmu.h| 2 +-
arch/arm64/include/asm/stage2_pgtable.h | 2 +-
arch/arm64/kvm/reset.c
ff-by: Suzuki K Poulose
---
Changes since v5:
- Set the missing TCR_T0SZ initialisation (Eric Auger)
and limit the T0SZ to the real CPU limit or KVM_PHYS_SHIFT
whichever is lower.
---
arch/arm64/include/asm/kvm_arm.h | 3 +-
arch/arm64/include/asm/kvm_asm.h | 2 -
arch/arm64/includ
S2_PGD_SIZE. Also, moves
some of the definitions in arm32 to align with the arm64.
Also drop the _AC() specifier constants wherever possible.
Cc: Christoffer Dall
Acked-by: Marc Zyngier
Reviewed-by: Eric Auger
Signed-off-by: Suzuki K Poulose
---
Changes since V3:
- Improve the comment about
If the guest wants to use a larger physical address space place
the RAM at upper half of the address space. Otherwise, it uses the
default layout.
Signed-off-by: Suzuki K Poulose
---
arm/aarch32/include/kvm/kvm-arch.h | 6 --
arm/aarch64/include/kvm/kvm-arch.h | 15 ---
arm
Since we are about to remove the lower limit on the IPA size,
make sure that we do not go to 1 level page table (e.g, with
32bit IPA on 64K host with concatenation) to avoid splitting
the host PMD huge pages at stage2.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
ion independently and
switch the page table code once we have it ready.
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since v5:
- Don't raise the IPA limit to 40bits
- Print the KVM IPA limit, WARN if the limit is less than the
l on /dev/kvm
- Handle 52bit addresses in PAR & HPFAR
- Drop patch changing the life time of stage2 PGD
- Rename macros for 48-to-52 bit conversion for GIC ITS BASER.
(suggested by Christoffer)
- Split virtio PFN check patches and address comments.
Kristina Martsenko (1):
vgic: Add sup
On a 4-level page table pgd entry can be empty, unlike a 3-level
page table. Remove the spurious WARN_ON() in stage_get_pud().
Acked-by: Christoffer Dall
Acked-by: Marc Zyngier
Reviewed-by: Eric Auger
Signed-off-by: Suzuki K Poulose
---
virt/kvm/arm/mmu.c | 2 +-
1 file changed, 1 insertion
Reviewed-by: Eric Auger
Signed-off-by: Kristina Martsenko
[ Macro clean ups, fix PROPBASER and PENDBASER accesses ]
Signed-off-by: Suzuki K Poulose
---
Changes since v5:
- Fixe CBASER_ADDRESS macro (s/52/51) - Eric Auger
---
include/linux/irqchip/arm-gic-v3.h | 5 +
virt/kvm/arm/vgic/vgic
Zyngier
Reviewed-by: Eric Auger
Signed-off-by: Suzuki K Poulose
---
virt/kvm/arm/mmu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
index ed162a6c57c5..ee7ce8fa4a12 100644
--- a/virt/kvm/arm/mmu.c
+++ b/virt/kvm/arm/mmu.c
@@ -412,7
: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/kvm_mmu.h | 12 +-
arch/arm64/include/asm/stage2_pgtable-nopmd.h | 42 -
arch/arm64/include/asm/stage2_pgtable-nopud.h | 39
arch/arm64/include/asm/stage2_pgtable.h | 173 ++
4 files
about
to make it dynamic, we need to calculate the SL0 at runtime
per VM. This patch adds a helper to compute the value of SL0
for a VM based on the IPA size.
Cc: Marc Zyngier
Cc: Christoffer Dall
Reviewed-by: Eric Auger
Signed-off-by: Suzuki K Poulose
---
Changes since v5:
- Improve
about to move its place. Having this helper keeps the code
movement cleaner.
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: James Morse
Cc: Christoffer Dall
Reviewed-by: Eric Auger
Signed-off-by: Suzuki K Poulose
---
Changes since V4:
- Add a comment on the result for unknown values.
---
arch/arm64
do the right thing with the
future changes.
Cc: Christoffer Dall
Cc: Marc Zyngier
Reviewed-by: Eric Auger
Signed-off-by: Suzuki K Poulose
---
Changes since v2:
- New patch
---
arch/arm64/include/asm/kvm_hyp.h | 9 +
arch/arm64/kvm/hyp/switch.c | 2 +-
arch/arm64/kvm/hyp/tlb.c
r Dall
Cc: Marc Zyngier
Reviewed-by: Eric Auger
Signed-off-by: Suzuki K Poulose
---
Change since v5:
- Reword commit description
- Use "lvls" instead of "n" for pt_levels_pgdir_shift()
---
arch/arm64/include/asm/stage2_pgtable.h | 84 +++--
1 file
Allow the arch backends to perform VM specific initialisation.
This will be later used to handle IPA size configuration and per-VM
VTCR configuration on arm64.
Cc: Marc Zyngier
Cc: Christoffer Dall
Reviewed-by: Eric Auger
Signed-off-by: Suzuki K Poulose
---
arch/arm/include/asm/kvm_host.h
This patch is a reverse engineered
implementation to calculate the 'x' at runtime for a given ipa and
number of page table levels. See patch for more details.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since v5:
- Update comment about the
Use the new helper for converting the parange to the physical shift.
Also, add the missing definitions for the VTCR_EL2 register fields
and use them instead of hard coding numbers.
Cc: Marc Zyngier
Cc: Christoffer Dall
Reviewed-by: Eric Auger
Signed-off-by: Suzuki K Poulose
---
Changs sinec
On 09/25/2018 10:59 AM, Auger Eric wrote:
Hi Suzuki,
On 9/17/18 12:41 PM, Suzuki K Poulose wrote:
So far we have restricted the IPA size of the VM to the default
value (40bits). Now that we can manage the IPA size per VM and
support dynamic stage2 page tables, we can allow VMs to have
larger
Hi Eric
On 09/21/2018 03:57 PM, Auger Eric wrote:
Hi Suzuki,
On 9/17/18 12:41 PM, Suzuki K Poulose wrote:
From: Kristina Martsenko
Add support for handling 52bit guest physical address to the
VGIC layer. So far we have limited the guest physical address
to 48bits, by explicitly masking the
On 09/25/2018 11:00 AM, Auger Eric wrote:
Hi Suzuki,
On 9/17/18 12:41 PM, Suzuki K Poulose wrote:
Since we are about to remove the lower limit on the IPA size,
make sure that we do not go to 1 level page table (e.g, with
32bit IPA on 64K host with concatenation) to avoid splitting
the host PMD
On 09/25/2018 11:00 AM, Auger Eric wrote:
Hi Suzuki,
On 9/17/18 12:41 PM, Suzuki K Poulose wrote:
Allow specifying the physical address size limit for a new
VM via the kvm_type argument for the KVM_CREATE_VM ioctl. This
allows us to finalise the stage2 page table as early as possible
and hence
Hi Punit,
On 09/24/2018 06:45 PM, Punit Agrawal wrote:
KVM only supports PMD hugepages at stage 2. Now that the various page
handling routines are updated, extend the stage 2 fault handling to
map in PUD hugepages.
Addition of PUD hugepage support enables additional page sizes (e.g.,
1G with 4
or THP
+* pages.
+*/
+ if (!PageHuge(page) && PageTransCompoundMap(page)) {
Reviewed-by: Suzuki K Poulose
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Hi Eric,
On 20/09/18 15:25, Auger Eric wrote:
Hi Suzuki,
On 9/17/18 12:41 PM, Suzuki K Poulose wrote:
VTCR_EL2 holds the following key stage2 translation table
parameters:
SL0 - Entry level in the page table lookup.
T0SZ - Denotes the size of the memory addressed by the table.
We have
On 20/09/18 15:07, Auger Eric wrote:
Hi Suzuki,
On 9/17/18 12:41 PM, Suzuki K Poulose wrote:
On arm64 VTTBR_EL2:BADDR holds the base address for the stage2
translation table. The Arm ARM mandates that the bits BADDR[x-1:0]
should be 0, where 'x' is defined for a given IPA Size and
Hi Eric,
On 20/09/18 11:21, Auger Eric wrote:
Hi Suzuki,
On 9/17/18 12:41 PM, Suzuki K Poulose wrote:
Add support for setting the VTCR_EL2 per VM, rather than hard
coding a value at boot time per CPU. This would allow us to tune
the stage2 page table parameters per VM in the later changes
Hi Drew,
On 09/19/2018 01:37 PM, Andrew Jones wrote:
On Tue, Sep 18, 2018 at 07:54:23PM +0200, Andrew Jones wrote:
This series provides KVM selftests that test dirty log tracking on
AArch64 for both 4K and 64K guest page sizes. Additionally the
framework provides an easy way to test dirty log t
On 09/18/2018 06:15 PM, Peter Maydell wrote:
On 18 September 2018 at 17:27, Suzuki K Poulose wrote:
---
"On arm64, the physical address size for a VM (IPA Size limit) is limited
to 40bits by default. The limit can be configured if the host supports the
extension KVM_CAP_ARM_VM_IPA_SIZE.
Hi Peter,
On 18/09/18 16:36, Peter Maydell wrote:
On 18 September 2018 at 16:16, Suzuki K Poulose wrote:
Hi Peter,
On 18/09/2018 02:55, Peter Maydell wrote:
On 17 September 2018 at 11:41, Suzuki K Poulose
wrote:
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm
Hi Peter,
On 18/09/2018 02:55, Peter Maydell wrote:
On 17 September 2018 at 11:41, Suzuki K Poulose wrote:
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -122,6 +122,14 @@ the default trap & emulate implementation (which changes
the virtual
memory la
Hi Peter,
On 17/09/2018 15:20, Peter Maydell wrote:
On 17 September 2018 at 11:41, Suzuki K Poulose wrote:
Allow specifying the physical address size limit for a new
VM via the kvm_type argument for the KVM_CREATE_VM ioctl. This
allows us to finalise the stage2 page table as early as possible
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