o the guest.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Change since V2:
- Load VTCR for TLB operations
---
arch/arm64/include/asm/kvm_arm.h | 19 +--
arch/arm64/include/asm/kvm_asm.h | 2 +-
arch/arm64/include/asm/kvm_host.h | 9 ++---
arch/
do the right thing with the
future changes.
Cc: Christoffer Dall
Cc: Marc Zyngier
Signed-off-by: Suzuki K Poulose
---
Changes since v2:
- New patch
---
arch/arm64/include/asm/kvm_hyp.h | 6 ++
arch/arm64/kvm/hyp/switch.c | 2 +-
arch/arm64/kvm/hyp/tlb.c | 4 ++--
3 files
about
to make it dynamic, we need to calculate the SL0 at runtime
per VM. This patch adds a helper to comput the value of SL0 for
a given IPA.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since v2:
- Part 2 of split from VTCR & VTTBR dynamic configura
This patch is a reverse engineered
implementation to calculate the 'x' at runtime for a given ipa and
number of page table levels. See patch for more details.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since V2:
- Part 1 of spilt from
to the top, before including the asm/stage2_pgtable.h to avoid a forward
declaration.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since V2
- Restrict the stage2 page table to allow reusing the host page table
helpers for now, until we get stage1 independ
S2_PGD_SIZE. Also, moves
some of the definitions dependent on kvm instance to asm/kvm_mmu.h
for arm32. In that process drop the _AC() specifier constants
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since V2:
- Update commit description abuot the movement to asm
Abstract the allocation of stage2 entry level tables for
given VM, so that later we can choose to fall back to the
normal page table levels (i.e, avoid entry level table
concatenation) on arm64.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since V2:
- New
On a 4-level page table pgd entry can be empty, unlike a 3-level
page table. Remove the spurious WARN_ON() in stage_get_pud().
Cc: Marc Zyngier
Acked-by: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
virt/kvm/arm/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
Use the new helper for converting the parange to the physical shift.
Also, add the missing definitions for the VTCR_EL2 register fields
and use them instead of hard coding numbers.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since V2
- Part 2 of the split
So far we have only supported 3 level page table with fixed IPA of 40bits.
Fix stage2_flush_memslot() to accommodate for 4 level tables.
Cc: Marc Zyngier
Acked-by: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
virt/kvm/arm/mmu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
, rather than silently breaking
the devices.
Cc: "Michael S. Tsirkin"
Cc: Jason Wang
Cc: Marc Zyngier
Cc: Christoffer Dall
Cc: Peter Maydel
Cc: Jean-Philippe Brucker
Signed-off-by: Suzuki K Poulose
---
Changes since v2:
- Change errno to -E2BIG
---
drivers/virtio/virtio_pci_leg
it
is about to move its place. Having this helper keeps the code
movement cleaner.
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: James Morse
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since V2:
- Split the patch
- Limit the physical shift only for values unrecognized
o PFN check patches and address comments.
Kristina Martsenko (1):
vgic: Add support for 52bit guest physical address
Suzuki K Poulose (19):
virtio: mmio-v1: Validate queue PFN
virtio: pci-legacy: Validate queue pfn
arm64: Add a helper for PARange to physical shift conversion
kvm: arm64: Cle
, rather than silently breaking
the devices.
Cc: "Michael S. Tsirkin"
Cc: Jason Wang
Cc: Marc Zyngier
Cc: Christoffer Dall
Cc: Peter Maydel
Cc: Jean-Philippe Brucker
Signed-off-by: Suzuki K Poulose
---
Changes since v2:
- Change errno to -E2BIG
---
drivers/virtio/virtio_m
Marc,
On 27/06/18 13:20, Marc Zyngier wrote:
Up to ARMv8.3, the combinaison of Stage-1 and Stage-2 attributes
results in the strongest attribute of the two stages. This means
that the hypervisor has to perform quite a lot of cache maintenance
just in case the guest has some non-cacheable mappin
Marc,
On 27/06/18 13:20, Marc Zyngier wrote:
The arm and arm64 KVM page tables accessors are pointlessly different
between the two architectures, and likely both wrong one way or another:
arm64 lacks a dsb(), and arm doesn't use WRITE_ONCE.
Let's unify them.
nit: Feel free to ignore. The chan
Hi Marc,
On 27/06/18 13:20, Marc Zyngier wrote:
The {pmd,pud,pgd}_populate accessors usage in the kernel have always
been a bit weird in KVM. We don't have a struct mm to pass (and
neither does the kernel most of the time, but still...), and
the 32bit code has all kind of cache maintenance that
-by: Marc Zyngier
Reviewed-by: Suzuki K Poulose
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On 24/05/18 12:39, Will Deacon wrote:
On Thu, May 24, 2018 at 10:58:43AM +0100, Suzuki K Poulose wrote:
On 22/05/18 16:06, Marc Zyngier wrote:
As for Spectre variant-2, we rely on SMCCC 1.1 to provide the
discovery mechanism for detecting the SSBD mitigation.
A new capability is also
no easy way to solve it
other than
1) Allow late modifications to CPU hwcaps
OR
2) Penalise the fastpath to always check per-cpu setting.
Regardless,
Reviewed-by: Suzuki K Poulose
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uniform support for GPA and GPI.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Suzuki K Poulose
Cc: Will Deacon
---
arch/arm64/include/asm/cpucaps.h | 5 -
arch/arm64/kernel/cpufeature.c | 47
2 files changed, 51 insertions(+), 1 deletion
. These may be made use of in future patches.
No support is added for the generic key (APGAKey), though this cannot be
trapped or made to behave as a NOP. Its presence is not advertised with
a hwcap.
Signed-off-by: Mark Rutland
Cc: Catalin Marinas
Cc: Ramana Radhakrishnan
Cc: Suzuki K Poulose
Cc
On 17/05/18 13:46, Jia He wrote:
Hi Suzuki
On 5/17/2018 4:17 PM, Suzuki K Poulose Wrote:
Hi Jia,
On 17/05/18 07:11, Jia He wrote:
I ever met a panic under memory pressure tests(start 20 guests and run
memhog in the host).
Please avoid using "I" in the commit description and
h a "positive" size value. Anyways,
the unmap requests must be in units of pages. So this check might be useful.
Reviewed-by: Suzuki K Poulose
[1] https://lkml.org/lkml/2018/5/3/1042
Signed-off-by: jia...@hxt-semitech.com
---
virt/kvm/arm/mmu.c | 2 ++
1 file changed, 2 inser
On 05/14/2018 03:43 PM, Punit Agrawal wrote:
KVM only supports PMD hugepages at stage 2. Extend the stage 2 fault
handling to add support for PUD hugepages.
Addition of pud hugepage support enables additional hugepage
sizes (e.g., 1G with 4K granule) which can be useful on cores that
support map
Hi Jia,
On 15/05/18 14:15, Jia He wrote:
On 5/15/2018 8:38 PM, Jia He Wrote:
Hi Suzuki
On 5/15/2018 4:36 PM, Suzuki K Poulose Wrote:
Hi Jia
On 05/15/2018 03:03 AM, Jia He wrote:
Hi Suzuki
I will merge the other thread into this, and add the necessary CC list
That WARN_ON call trace is
Hi Jia
On 05/15/2018 03:03 AM, Jia He wrote:
Hi Suzuki
I will merge the other thread into this, and add the necessary CC list
That WARN_ON call trace is very easy to reproduce in my armv8a server
after I start 20 guests
and run memhog in the host. Of course, ksm should be enabled
For you
On 14/05/18 03:30, Jia He wrote:
On 5/11/2018 9:39 PM, Suzuki K Poulose Wrote:
Marc
Thanks for looping me in. Comments below.
On 03/05/18 03:02, Jia He wrote:
Hi Marc
Thanks for the review
On 5/2/2018 10:26 PM, Marc Zyngier Wrote:
[+ Suzuki]
On 02/05/18 08:08, Jia He wrote:
From
Marc
Thanks for looping me in. Comments below.
On 03/05/18 03:02, Jia He wrote:
Hi Marc
Thanks for the review
On 5/2/2018 10:26 PM, Marc Zyngier Wrote:
[+ Suzuki]
On 02/05/18 08:08, Jia He wrote:
From: Jia He
In our armv8a server (QDF2400), I noticed a WARN_ON as follows:
[ 800.20285
On 03/05/18 15:39, James Morse wrote:
Hi Suzuki,
Nit: KVM in the subject line?
Well, the helper is generic and its just that KVM makes use of it.
On 27/03/18 14:15, Suzuki K Poulose wrote:
Add a helper to convert ID_AA64MMFR0_EL1:PARange to they physical
size shift. Limit the size to the
On 03/05/18 15:39, James Morse wrote:
Hi Suzuki,
On 27/03/18 14:15, Suzuki K Poulose wrote:
We set VTCR_EL2 very early during the stage2 init and don't
touch it ever. This is fine as we had a fixed IPA size. This
patch changes the behavior to set the VTCR for a given VM,
depending o
On 01/05/18 11:26, Punit Agrawal wrote:
Introduce helpers to abstract architectural handling of the conversion
of pfn to page table entries and marking a PMD page table entry as a
block entry.
The helpers are introduced in preparation for supporting PUD hugepages
at stage 2 - which are supported
On 30/04/18 15:17, Julien Grall wrote:
Hi,
On 27/03/18 14:15, Suzuki K Poulose wrote:
diff --git a/arm/kvm.c b/arm/kvm.c
index 5701d41..a9a9140 100644
--- a/arm/kvm.c
+++ b/arm/kvm.c
@@ -11,6 +11,8 @@
#include
#include
+unsigned long kvm_arm_type;
+
struct kvm_ext kvm_req_ext
On 27/04/18 16:22, Suzuki K Poulose wrote:
On 26/04/18 14:35, Julien Grall wrote:
Hi Suzuki,
On 27/03/18 14:15, Suzuki K Poulose wrote:
Right now the stage2 page table for a VM is hard coded, assuming
an IPA of 40bits. As we are about to add support for per VM IPA,
prepare the stage2 page
On 26/04/18 14:35, Julien Grall wrote:
Hi Suzuki,
On 27/03/18 14:15, Suzuki K Poulose wrote:
Right now the stage2 page table for a VM is hard coded, assuming
an IPA of 40bits. As we are about to add support for per VM IPA,
prepare the stage2 page table helpers to accept the kvm instance
to
On 26/04/18 11:58, Julien Grall wrote:
Hi Suzuki,
On 27/03/18 14:15, Suzuki K Poulose wrote:
Add a helper to convert ID_AA64MMFR0_EL1:PARange to they physical
size shift. Limit the size to the maximum supported by the kernel.
We are about to move the user of this code and this helps to
keep
On 25/04/18 17:35, Julien Grall wrote:
Hi Suzuki,
On 27/03/18 14:15, Suzuki K Poulose wrote:
So far we had a static stage2 page table handling code, based on a
fixed IPA of 40bits. As we prepare for a configurable IPA size per
VM, make the our stage2 page table code dynamic to do the right
On 25/04/18 17:10, Julien Grall wrote:
Hi Suzuki,
On 27/03/18 14:15, Suzuki K Poulose wrote:
Allow specifying the physical address size for a new VM via
the kvm_type argument for KVM_CREATE_VM ioctl. This allows
us to finalise the stage2 page table format as early as possible
and hence perform
On 13/04/18 17:27, Punit Agrawal wrote:
Hi Suzuki,
I haven't had a chance to look at the code but noticed one issue below.
Suzuki K Poulose writes:
Now that we can manage the stage2 page table per VM, switch the
configuration details to per VM instance. We keep track of the
IPA bits, n
On 13/04/18 14:21, Peter Maydell wrote:
On 27 March 2018 at 14:15, Suzuki K Poulose wrote:
Expose the maximum physical address size supported by the host
for a VM. This could be later used by the userspace to choose the
appropriate size for a given VM. The limit is determined as the
minimum of
On 03/04/18 15:58, James Morse wrote:
Hi Suzuki,
On 27/03/18 14:15, Suzuki K Poulose wrote:
We set VTCR_EL2 very early during the stage2 init and don't
touch it ever. This is fine as we had a fixed IPA size. This
patch changes the behavior to set the VTCR for a given VM,
depending o
Specify the physical size for the VM encoded in the vm type.
Signed-off-by: Suzuki K Poulose
---
arm/include/arm-common/kvm-arch.h | 6 +-
arm/kvm.c | 21 +
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/arm/include/arm-common/kvm
If the guest wants to use a larger physical address space place
the RAM at upper half of the address space. Otherwise, it uses the
default layout.
Signed-off-by: Suzuki K Poulose
---
arm/aarch32/include/kvm/kvm-arch.h | 1 +
arm/aarch64/include/kvm/kvm-arch.h | 15 ---
arm/include
Add an option to specify the physical address size used by this
VM.
Signed-off-by: Suzuki K Poulose
---
arm/aarch64/include/kvm/kvm-config-arch.h | 5 -
arm/include/arm-common/kvm-config-arch.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arm/aarch64/include/kvm/kvm
Allow architectures to perform initialisation based on the
KVM device fd ioctls, even before the VM is created.
Signed-off-by: Suzuki K Poulose
---
include/kvm/kvm.h | 4
kvm.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/include/kvm/kvm.h b/include/kvm/kvm.h
index
Signed-off-by: Kristina Martsenko
[ Macro clean ups, fix PROPBASER and PENDBASER accesses ]
Signed-off-by: Suzuki K Poulose
---
include/linux/irqchip/arm-gic-v3.h | 5 +
virt/kvm/arm/vgic/vgic-its.c | 37 ++---
virt/kvm/arm/vgic/vgic-mmio-v3.c | 2 --
3
aults in stage1.
Cc: Marc Zyngier
Cc: Kristina Martsenko
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/kvm_arm.h | 7 +++
arch/arm64/kvm/hyp/switch.c | 2 +-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/kvm_arm
the check for
the default IPA size support to kvm_get_ipa_limit().
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/kvm_host.h | 5 -
arch/arm64/include/asm/kvm_mmu.h | 18 +-
2 files changed, 17 insertions(+), 6 deletions
arm64.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/kvm_host.h | 14 --
arch/arm64/include/asm/kvm_mmu.h| 11 +--
arch/arm64/include/asm/stage2_pgtable.h | 1 -
arch/arm64/kvm/hyp/switch.c | 3
the stage2 page table.
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: Peter Maydel
Signed-off-by: Suzuki K Poulose
---
Documentation/virtual/kvm/api.txt | 14 ++
arch/arm/include/asm/kvm_mmu.h| 5 +
arch/arm64/include/asm/kvm_mmu.h | 5 +
include/uapi/linux/kvm.h
) in the bits[7:0]
of the type field and can encode more information in the future if
required.
Cc: Marc Zyngier
Cc: Christoffer Dall
Cc: Peter Maydel
Cc: Paolo Bonzini
Cc: Radim Krčmář
Signed-off-by: Suzuki K Poulose
---
arch/arm/include/asm/kvm_mmu.h | 2 ++
arch/arm64/include/asm
o the guest.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/kvm_arm.h | 16 ++--
arch/arm64/include/asm/kvm_asm.h | 2 +-
arch/arm64/include/asm/kvm_host.h | 8 +---
arch/arm64/kvm/hyp/s2-setup.c | 16 +---
arch/
e able to get contiguous block of memory for the entry
level page table. (e.g, With 64KB page size and 46bit IPA
starting at level 2, finding 16 * 64KB contiguous block on a
loaded system could be tricky. So we could decide to rather
enter at level 1, with a single page).
Cc: Marc Zyngier
Cc: C
Signed-off-by: Suzuki K Poulose
---
arch/arm/include/asm/kvm_arm.h| 3 +-
arch/arm/include/asm/kvm_mmu.h| 15 +++-
arch/arm/include/asm/stage2_pgtable.h | 42 -
arch/arm64/include/asm/kvm_mmu.h | 7 +-
arch/arm64/include/asm
configure the EL2 registers (VTTBR and VTCR). So, the IPA is still
fixed to 40bits. The patch also moves the kvm_page_empty() in asm/kvm_mmu.h
to the top, before including the asm/stage2_pgtable.h to avoid a forward
declaration.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
On a 4-level page table pgd entry can be empty, unlike a 3-level
page table. Remove the spurious WARN_ON() in stage_get_pud().
Cc: Marc Zyngier
Acked-by: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
virt/kvm/arm/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/cpufeature.h | 16
arch/arm64/kvm/hyp/s2-setup.c | 28 +---
2 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/arch/arm64/include/asm/cpufeature.h
b/arch
So far we have only supported 3 level page table with fixed IPA of 40bits.
Fix stage2_flush_memslot() to accommodate for 4 level tables.
Cc: Marc Zyngier
Acked-by: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
virt/kvm/arm/mmu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
Make pud_huge reusable for stage2 tables, independent
of the stage1 levels.
Cc: Steve Capper
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/pgtable.h | 5 +
arch/arm64/mm/hugetlbpage.c | 2 +-
2
, for consistency, we name the raw
page table action helpers __raw_p.d_action.
Cc: Catalin Marinas
Cc: Mark Rutland
Cc: Will Deacon
Cc: Steve Capper
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/pgalloc.h | 34 +++
arch
, rather than silently breaking
the devices.
Cc: "Michael S. Tsirkin"
Cc: Jason Wang
Cc: Marc Zyngier
Cc: Christoffer Dall
Cc: Peter Maydel
Cc: Jean-Philippe Brucker
Signed-off-by: Suzuki K Poulose
---
drivers/virtio/virtio_pci_legacy.c | 12 ++--
1 file changed, 10 insert
, rather than silently breaking
the devices.
Cc: "Michael S. Tsirkin"
Cc: Jason Wang
Cc: Marc Zyngier
Cc: Christoffer Dall
Cc: Peter Maydel
Cc: Jean-Philippe Brucker
Signed-off-by: Suzuki K Poulose
---
drivers/virtio/virtio_mmio.c | 18 --
1 file changed, 16 insert
a Martsenko (1):
vgic: Add support for 52bit guest physical address
Suzuki K Poulose (16):
virtio: mmio-v1: Validate queue PFN
virtio: pci-legacy: Validate queue pfn
arm64: Make page table helpers reusable
arm64: Refactor pud_huge for reusability
arm64: Helper for parange to
oks good to me, FWIW:
Reviewed-by: Suzuki K Poulose
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Hi Christoffer,
On 08/02/18 18:04, Christoffer Dall wrote:
On Tue, Jan 09, 2018 at 07:04:08PM +, Suzuki K Poulose wrote:
We set VTCR_EL2 very early during the stage2 init and don't
touch it ever. This is fine as we had a fixed IPA size. This
patch changes the behavior to set the VTC
On 09/02/18 08:16, Christoffer Dall wrote:
On Thu, Feb 08, 2018 at 05:53:17PM +, Suzuki K Poulose wrote:
On 08/02/18 11:14, Christoffer Dall wrote:
On Tue, Jan 09, 2018 at 07:04:10PM +, Suzuki K Poulose wrote:
Allow the guests to choose a larger physical address space size.
The
On 01/03/18 15:55, Marc Zyngier wrote:
As we're about to change the way we map devices at HYP, we need
to move away from kern_hyp_va on an IO address.
One way of achieving this is to store the VAs in kvm_vgic_global_state,
and use that directly from the HYP code. This requires a small change
to
On 01/03/18 15:55, Marc Zyngier wrote:
Both HYP io mappings call ioremap, followed by create_hyp_io_mappings.
Let's move the ioremap call into create_hyp_io_mappings itself, which
simplifies the code a bit and allows for further refactoring.
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyn
arch/arm64/include/asm/cpucaps.h | 2 +-
arch/arm64/kernel/cpufeature.c | 19 ---
2 files changed, 1 insertion(+), 20 deletions(-)
Reviewed-by: Suzuki K Poulose
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On 08/02/18 11:14, Christoffer Dall wrote:
On Tue, Jan 09, 2018 at 07:04:10PM +, Suzuki K Poulose wrote:
Allow the guests to choose a larger physical address space size.
The default and minimum size is 40bits. A guest can change this
right after the VM creation, but before the stage2 entry
On 08/02/18 11:00, Christoffer Dall wrote:
On Tue, Jan 09, 2018 at 07:04:09PM +, Suzuki K Poulose wrote:
Now that we can manage the stage2 page table per VM, switch the
configuration details to per VM instance. We keep track of the
IPA bits, number of page table levels and the VTCR bits
On 08/02/18 11:01, Christoffer Dall wrote:
On Tue, Jan 09, 2018 at 07:04:04PM +, Suzuki K Poulose wrote:
We allocate the entry level page tables for stage2 when the
VM is created. This doesn't give us the flexibility of configuring
the physical address space size for a VM. In order to
On 08/02/18 11:00, Christoffer Dall wrote:
On Tue, Jan 09, 2018 at 07:04:03PM +, Suzuki K Poulose wrote:
On arm/arm64 we pre-allocate the entry level page tables when
a VM is created and is free'd when either all the mm users are
gone or the KVM is about to get destroyed
On 07/02/18 15:10, Christoffer Dall wrote:
Hi Suzuki,
On Tue, Jan 09, 2018 at 07:03:57PM +, Suzuki K Poulose wrote:
Add helpers for encoding/decoding 52bit address in GICv3 ITS BASER
register. When ITS uses 64K page size, the 52bits of physical address
are encoded in BASER[47:12] as
On 08/02/18 11:00, Christoffer Dall wrote:
On Tue, Jan 09, 2018 at 07:04:00PM +, Suzuki K Poulose wrote:
Add a helper to convert ID_AA64MMFR0_EL1:PARange to they physical
*the*
size shift. Limit the size to the maximum supported by
On 16/01/18 15:04, Catalin Marinas wrote:
On Mon, Jan 15, 2018 at 07:38:54PM +, James Morse wrote:
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9ef84d0def9a..d88cd0e88606 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@
space ^^^
With that fixed,
Reviewed-by: Suzuki K Poulose
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ature detection.
Platform level RAS support may require additional firmware support.
Signed-off-by: Xie XiuQi
[Rebased added config option, reworded commit message]
Signed-off-by: James Morse
Reviewed-by: Catalin Marinas
Reviewed-by: Suzuki K Po
On 10/01/18 11:06, Michael S. Tsirkin wrote:
On Wed, Jan 10, 2018 at 10:54:09AM +, Suzuki K Poulose wrote:
On 09/01/18 23:29, Michael S. Tsirkin wrote:
On Tue, Jan 09, 2018 at 07:03:56PM +, Suzuki K Poulose wrote:
virtio-mmio using virtio-v1 and virtio legacy pci use a 32bit PFN
for
On 09/01/18 23:29, Michael S. Tsirkin wrote:
On Tue, Jan 09, 2018 at 07:03:56PM +, Suzuki K Poulose wrote:
virtio-mmio using virtio-v1 and virtio legacy pci use a 32bit PFN
for the queue. If the queue pfn is too large to fit in 32bits, which
we could hit on arm64 systems with 52bit physical
for propbaser handling ]
Signed-off-by: Suzuki K Poulose
---
virt/kvm/arm/vgic/vgic-its.c | 36 ++--
virt/kvm/arm/vgic/vgic-mmio-v3.c | 1 -
2 files changed, 10 insertions(+), 27 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic
Add an option to specify the physical address size used by this
VM.
Signed-off-by: Suzuki K Poulose
---
arm/aarch64/include/kvm/kvm-config-arch.h | 5 -
arm/include/arm-common/kvm-config-arch.h | 1 +
arm/kvm.c | 30 ++
3 files
If the guest wants to use a larger physical address space place
the RAM at upper half of the address space. Otherwise, it uses the
default layout.
Signed-off-by: Suzuki K Poulose
---
arm/aarch32/include/kvm/kvm-arch.h | 1 +
arm/aarch64/include/kvm/kvm-arch.h | 15 ---
arm/include
When the host fails to complete the shake hand due to various
reasons. e.g, for PCI and MMIO, if 0 is written as the PFN,
it implies the host has given up and simply don't take any
action.
Signed-off-by: Suzuki K Poulose
---
virtio/mmio.c | 14 --
virtio/pci.c | 10 ++--
: Peter Maydell
Signed-off-by: Suzuki K Poulose
---
Documentation/virtual/kvm/api.txt | 27 ++
arch/arm/include/asm/kvm_host.h | 7 +++
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/include/asm/kvm_mmu.h | 41 ++-
arch/arm64
configure the EL2 registers (VTTBR and VTCR). So, the IPA is still
fixed to 40bits.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
arch/arm/include/asm/kvm_mmu.h| 1 +
arch/arm64/include/asm/kvm_mmu.h | 16 +-
arch/arm64/include/asm
K Poulose
---
arch/arm/include/asm/kvm_mmu.h | 1 +
arch/arm64/include/asm/kvm_host.h | 12
arch/arm64/include/asm/kvm_mmu.h| 22 --
arch/arm64/include/asm/stage2_pgtable.h | 1 -
arch/arm64/kvm/hyp/switch.c | 3 +--
virt/kvm
specific call back with the mutex held.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
virt/kvm/arm/arm.c | 18 ++--
virt/kvm/arm/mmu.c | 61 +-
2 files changed, 57 insertions(+), 22 deletions(-)
diff --gi
page tables until we really
need to do something with it.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
virt/kvm/arm/arm.c | 1 +
virt/kvm/arm/mmu.c | 56 --
2 files changed, 30 insertions(+), 27 deletions(-)
dif
e able to get contiguous block of memory for the entry
level page table. (e.g, With 64KB page size and 46bit IPA
starting at level 2, finding 16 * 64KB contiguous block on a
loaded system could be tricky. So we could decide to rather
enter at level 1, with a single page).
Cc: Marc Zyngier
Cc: C
e SL0
and T0SZ are programmed for each VM and is cleared once we
exit the VM.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/kvm_arm.h | 16 ++--
arch/arm64/include/asm/kvm_asm.h | 2 +-
arch/arm64/include/asm/kvm_host.h
-by: Suzuki K Poulose
---
arch/arm/include/asm/kvm_arm.h| 2 -
arch/arm/include/asm/kvm_mmu.h| 11 ++-
arch/arm/include/asm/stage2_pgtable.h | 46 ++-
arch/arm64/include/asm/kvm_mmu.h | 6 +-
arch/arm64/include/asm/pgtable.h
Add a helper to convert ID_AA64MMFR0_EL1:PARange to they physical
size shift. Limit the size to the maximum supported by the kernel.
Cc: Mark Rutland
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Marc Zyngier
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/cpufeature.h | 16
On a 4-level page table pgd entry can be empty, unlike a 3-level
page table. Remove the spurious WARN_ON() in stage_get_pud().
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
virt/kvm/arm/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/virt
So far we have only supported 3 level page table with fixed IPA of 40bits.
Fix stage2_flush_memslot() to accommodate for 4 level tables.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
virt/kvm/arm/mmu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
check to validate the PFN, rather than silently breaking
the devices.
Cc: "Michael S. Tsirkin"
Cc: Jason Wang
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
drivers/virtio/virtio_mmio.c | 19 ---
drivers/virtio/virtio_pci_leg
, for consistency, we name the raw
page table action helpers __raw_p.d_action.
Cc: Catalin Marinas
Cc: Mark Rutland
Cc: Will Deacon
Cc: Steve Capper
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/pgalloc.h | 32 +-
arch/arm64/include/asm/pgtable.h | 58
c.info/?l=linux-virtualization&m=151308636322117&w=2
Kristina Martsenko (1):
vgic: its: Add support for 52bit guest physical address
Suzuki K Poulose (15):
virtio: Validate queue pfn for 32bit transports
irqchip: gicv3-its: Add helpers for handling 52bit address
arm64: Make page table
yngier
Signed-off-by: Suzuki K Poulose
---
drivers/irqchip/irq-gic-v3-its.c | 2 +-
include/linux/irqchip/arm-gic-v3.h | 32 ++--
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
Make pud_huge reusable for stage2 tables, independent
of the stage1 levels.
Cc: Steve Capper
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/pgtable.h | 5 +
arch/arm64/mm/hugetlbpage.c | 2 +-
2 files changed, 6
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