On 06/08/2015 07:03 PM, Marc Zyngier wrote:
Now that struct vgic_lr supports the LR_HW bit and carries a hwirq
field, we can encode that information into the list registers.
This patch provides implementations for both GICv2 and GICv3.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
On 17/06/15 14:21, Peter Maydell wrote:
On 17 June 2015 at 12:53, Eric Auger eric.au...@linaro.org wrote:
shouldn't we test somewhere that the hwirq is between 16 and 1019.
Not directly related, but that reminds me that I noticed the
other day that we have VGIC_MAX_IRQS = 1024 (and use that
On 09/06/15 14:21, Alex Bennée wrote:
Marc Zyngier marc.zyng...@arm.com writes:
Now that struct vgic_lr supports the LR_HW bit and carries a hwirq
field, we can encode that information into the list registers.
This patch provides implementations for both GICv2 and GICv3.
Signed-off-by:
Marc Zyngier marc.zyng...@arm.com writes:
Now that struct vgic_lr supports the LR_HW bit and carries a hwirq
field, we can encode that information into the list registers.
This patch provides implementations for both GICv2 and GICv3.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Now that struct vgic_lr supports the LR_HW bit and carries a hwirq
field, we can encode that information into the list registers.
This patch provides implementations for both GICv2 and GICv3.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
include/linux/irqchip/arm-gic-v3.h | 3 +++
