Hi James,
On 2020-10-27 17:41, James Morse wrote:
Hi Marc,
On 26/10/2020 13:34, Marc Zyngier wrote:
Move the AArch64 exception injection code from EL1 to HYP, leaving
only the ESR_EL1 updates to EL1. In order to come with the differences
(cope with the differences?)
Yes, much better!
Hi Marc,
On 26/10/2020 13:34, Marc Zyngier wrote:
> Move the AArch64 exception injection code from EL1 to HYP, leaving
> only the ESR_EL1 updates to EL1. In order to come with the differences
(cope with the differences?)
> between VHE and nVHE, two set of system register accessors are
On 2020-10-26 14:22, Mark Rutland wrote:
On Mon, Oct 26, 2020 at 01:34:46PM +, Marc Zyngier wrote:
Move the AArch64 exception injection code from EL1 to HYP, leaving
only the ESR_EL1 updates to EL1. In order to come with the differences
between VHE and nVHE, two set of system register
On Mon, Oct 26, 2020 at 01:34:46PM +, Marc Zyngier wrote:
> Move the AArch64 exception injection code from EL1 to HYP, leaving
> only the ESR_EL1 updates to EL1. In order to come with the differences
> between VHE and nVHE, two set of system register accessors are provided.
>
> SPSR, ELR, PC
Move the AArch64 exception injection code from EL1 to HYP, leaving
only the ESR_EL1 updates to EL1. In order to come with the differences
between VHE and nVHE, two set of system register accessors are provided.
SPSR, ELR, PC and PSTATE are now completely handled in the hypervisor.
Signed-off-by:
