Hi Paolo,
On 07/02/2015 03:40 PM, Paolo Bonzini wrote:
On 02/07/2015 15:17, Eric Auger wrote:
- new fields are added on producer side: linux irq, vfio_device handle,
active which reflects whether the source is active (at interrupt
controller level or at VFIO level - automasked -) and
Hi!
OK so both of you say the same thing. Will respin accordingly
You may also want to add this:
Tested-by: Pavel Fedin p.fe...@samsung.com
Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia
___
kvmarm mailing
Will Deacon will.dea...@arm.com writes:
Hi Alex,
On Thu, Jul 02, 2015 at 02:50:33PM +0100, Alex Bennée wrote:
Are you happy with this?:
[...]
+/**
+ * kvm_arch_dev_ioctl_check_extension
+ *
+ * We currently assume that the number of HW registers is uniform
+ * across all CPUs (see
Hi Christoffer,
+
+static struct its_collection *vits_new_collection(struct kvm *kvm, u32
coll_id)
+{
+struct its_collection *collection;
+
+collection = kmalloc(sizeof(struct its_collection), GFP_KERNEL);
If I manage to understand the structure here, you're calling all
On 07/03/2015 07:20 PM, Paolo Bonzini wrote:
On 03/07/2015 15:12, Eric Auger wrote:
Linux IRQ and active should be okay. As to the vfio_device handle, you
should link it from the vfio_platform_device instead. And for the
vfio_platform_device, you can link it from the vfio_platform_irq
On 07/03/2015 04:53 AM, Christoffer Dall wrote:
On Thu, Jul 02, 2015 at 02:51:57PM -0700, Mario Smarduch wrote:
On 07/01/2015 06:46 AM, Christoffer Dall wrote:
On Wed, Jun 24, 2015 at 05:04:11PM -0700, Mario Smarduch wrote:
This patch only saves and restores FP/SIMD registers on Guest access.
Hi,
On 03/07/15 10:05, Andre Przywara wrote:
Hi Pavel,
On 02/07/15 08:26, Pavel Fedin wrote:
Hello!
-Original Message-
From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On
Behalf Of Eric Auger
Sent: Monday, June 29, 2015 6:37 PM
To: eric.au...@st.com;
On 03/07/2015 15:12, Eric Auger wrote:
Linux IRQ and active should be okay. As to the vfio_device handle, you
should link it from the vfio_platform_device instead. And for the
vfio_platform_device, you can link it from the vfio_platform_irq instead.
For this last one, I don't think this
On 25/06/2015 20:45, Andrew Jones wrote:
The mmu is enabled automatically for all cpus, they must disable it
themselves if they don't want it on. Switch from managing a cpumask
of enabled cpus to one of disabled cpus. This allows us to remove
the mmu_set_enabled call from secondary_cinit,
On 25/06/2015 18:12, Andrew Jones wrote:
It shouldn't be necessary to use a barrier on the way into
spin_lock. We'll be focused on a single address until we get
it (exclusively) set, and then we'll do a barrier on the way
out. Also, it does make sense to do a barrier on the way in
to
On Fri, Jul 03, 2015 at 04:57:04PM +0100, Andre Przywara wrote:
Hi Christoffer,
+
+static struct its_collection *vits_new_collection(struct kvm *kvm, u32
coll_id)
+{
+ struct its_collection *collection;
+
+ collection = kmalloc(sizeof(struct its_collection),
On Fri, Jul 03, 2015 at 06:06:48PM +0800, Zhichao Huang wrote:
On June 30, 2015 9:15:22 PM GMT+08:00, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Mon, Jun 22, 2015 at 06:41:32PM +0800, Zhichao Huang wrote:
Implement switching of the debug registers. While the number
of
On Wed, Jul 01, 2015 at 07:29:00PM +0100, Alex Bennée wrote:
This introduces a level of indirection for the debug registers. Instead
of using the sys_regs[] directly we store registers in a structure in
the vcpu. The new kvm_arm_reset_debug_ptr() sets the debug ptr to the
guest context.
On Fri, Jul 03, 2015 at 08:14:52AM +0100, Alex Bennée wrote:
Christoffer Dall christoffer.d...@linaro.org writes:
On Wed, Jul 01, 2015 at 07:29:00PM +0100, Alex Bennée wrote:
This introduces a level of indirection for the debug registers. Instead
of using the sys_regs[] directly we
On 02/07/15 21:29, Chalamarla, Tirumalesh wrote:
is there a chance that this get merged in to 4.2? if not is it possible
to accept the other patches like adding implementations explicitly(like
Thunder).
We first need to reach a conclusion on this. Until then, I don't plan to
get anything in.
On 02/07/2015 15:17, Eric Auger wrote:
+ void (*stop_producer)(struct irq_bypass_producer *);
+ void (*resume_producer)(struct irq_bypass_producer *);
Also, can you call these just stop/resume ...
+ void (*add_consumer)(struct irq_bypass_producer *,
+
On 03/07/2015 09:00, Wu, Feng wrote:
struct irq_bypass_consumer {
struct list_head node;
void *token;
+ unsigned irq;/*got from producer when registered*/
void (*add_producer)(struct irq_bypass_producer *,
struct
On 03/07/2015 04:43, Wu, Feng wrote:
struct irq_bypass_consumer {
struct list_head node;
void *token;
+ unsigned irq; /*got from producer when registered*/
void (*add_producer)(struct irq_bypass_producer *,
struct irq_bypass_consumer
On 3 July 2015 at 09:28, Marc Zyngier marc.zyng...@arm.com wrote:
On 03/07/15 09:12, Peter Maydell wrote:
I would still like to see the proponents of this patch say
what their model is for userspace support of cross-host migration,
if we're abandoning the model the current API envisages.
I
On 03/07/15 10:34, Peter Maydell wrote:
On 3 July 2015 at 09:28, Marc Zyngier marc.zyng...@arm.com wrote:
On 03/07/15 09:12, Peter Maydell wrote:
I would still like to see the proponents of this patch say
what their model is for userspace support of cross-host migration,
if we're abandoning
Hi Alex,
On Thu, Jul 02, 2015 at 02:50:33PM +0100, Alex Bennée wrote:
Are you happy with this?:
[...]
+/**
+ * kvm_arch_dev_ioctl_check_extension
+ *
+ * We currently assume that the number of HW registers is uniform
+ * across all CPUs (see cpuinfo_sanity_check).
+ */
int
On June 30, 2015 5:20:20 PM GMT+08:00, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Mon, Jun 22, 2015 at 06:41:31PM +0800, Zhichao Huang wrote:
The trapping code keeps track of the state of the debug registers,
allowing for the switch code to implement a lazy switching strategy.
On 3 July 2015 at 10:50, Marc Zyngier marc.zyng...@arm.com wrote:
On 02/07/15 17:23, Christoffer Dall wrote:
If we had a different *shared* device than the timer which is
edge-triggered, don't we then also need to capture the physical
distributor's pending state along with the state of the
From: Marc Zyngier marc.zyng...@arm.com
As of 3.14, KVM/arm supports the creation/configuration of the GIC through
a more generic device API, which is now the preferred way to do so.
Plumb the new API in, and allow the old code to be used as a fallback.
[Andre: Rename some functions on the way
Since Linux 3.19-rc1 there is a new API to explicitly initialise
the in-kernel GIC emulation by a userland KVM device call.
Use that to tell the kernel we are finished with the GIC
initialisation, since the automatic GIC init will only be provided
as a legacy functionality in the future.
From: Marc Zyngier marc.zyng...@arm.com
On AArch64 system with a GICv2, the GICC range can be aligned
to the last 4k block of a 64k page, ending up straddling two
64k pages. In order not to conflict with the distributor mapping,
allocate two 64k pages to the CPU interface.
Signed-off-by: Marc
From: Marc Zyngier marc.zyng...@arm.com
The ARM GIC emulation needs to be told the number of interrupts
it has to support. As commit 1c262fa1dc7bc (kvm tools: irq: make
irq__alloc_line generic) made the interrupt counter private,
add a new accessor returning the number of interrupt lines we've
Extend the vGIC handling code to potentially deal with different IRQ
chip devices instead of hard-coding the GICv2 in.
We extend most vGIC functions to take a type parameter, but still put
GICv2 in at the top for the time being.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
Reviewed-by:
Currently we unconditionally create a virtual GICv2 in the guest.
Add a --irqchip= parameter to let the user specify a different GIC
type for the guest, when omitting this parameter it still defaults to
--irqchip=gicv2.
For now the only other supported type is --irqchip=gicv3
Signed-off-by: Andre
Instead of the GIC virtual CPU interface an emulated GICv3 needs to
have accesses to its emulated redistributors trapped in the guest.
Add code to tell the kernel about the mapping if a GICv3 emulation was
requested by the user.
This contains some defines which are not (yet) in the (32 bit)
On June 30, 2015 9:15:22 PM GMT+08:00, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Mon, Jun 22, 2015 at 06:41:32PM +0800, Zhichao Huang wrote:
Implement switching of the debug registers. While the number
of registers is massive, CPUs usually don't implement them all
(A15 has 6
On Thu, Jul 02, 2015 at 02:51:57PM -0700, Mario Smarduch wrote:
On 07/01/2015 06:46 AM, Christoffer Dall wrote:
On Wed, Jun 24, 2015 at 05:04:11PM -0700, Mario Smarduch wrote:
This patch only saves and restores FP/SIMD registers on Guest access. To do
this cptr_el2 FP/SIMD trap is set on
Christoffer, Marc,
On 07/02/2015 03:17 PM, Eric Auger wrote:
On halt, the guest is forced to exit and prevented from being
re-entered. This is synchronous.
Those two operations will be needed for IRQ forwarding setting.
Signed-off-by: Eric Auger eric.au...@linaro.org
would you agree to
On Fri, Jul 03, 2015 at 05:54:47PM +0800, Zhichao Huang wrote:
On June 30, 2015 5:20:20 PM GMT+08:00, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Mon, Jun 22, 2015 at 06:41:31PM +0800, Zhichao Huang wrote:
The trapping code keeps track of the state of the debug registers,
On 03/07/15 12:55, Eric Auger wrote:
Christoffer, Marc,
On 07/02/2015 03:17 PM, Eric Auger wrote:
On halt, the guest is forced to exit and prevented from being
re-entered. This is synchronous.
Those two operations will be needed for IRQ forwarding setting.
Signed-off-by: Eric Auger
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