2016-07-21 23:10+0200, Auger Eric:
> On 21/07/2016 18:33, Radim Krčmář wrote:
>> 2016-07-18 13:25+, Eric Auger:
>>> If the ITS modality is not available, let's simply support MSI
>>> injection by transforming the MSI.data into an SPI ID.
>>>
>>> This becomes possible to use KVM_SIGNAL_MSI
On 22/07/2016 15:56, Radim Krčmář wrote:
> 2016-07-22 15:52+0200, Auger Eric:
>> On 22/07/2016 15:39, Radim Krčmář wrote:
>>> 2016-07-21 23:10+0200, Auger Eric:
On 21/07/2016 18:33, Radim Krčmář wrote:
> 2016-07-18 13:25+, Eric Auger:
>> If the ITS modality is not available,
On 22/07/16 15:38, Andrew Jones wrote:
> We need to set cpsr before determining the spsr bank, as the bank
> depends on the target exception level of the injection, not the
> current mode of the vcpu. Normally this is one in the same (EL1),
> but not when we manage to trap an EL0 fault. It still
2016-07-22 15:52+0200, Auger Eric:
> On 22/07/2016 15:39, Radim Krčmář wrote:
>> 2016-07-21 23:10+0200, Auger Eric:
>>> On 21/07/2016 18:33, Radim Krčmář wrote:
2016-07-18 13:25+, Eric Auger:
> If the ITS modality is not available, let's simply support MSI
> injection by
With the advent of GICv3 ITS in-kernel emulation, KVM MSI routing
becomes mandated for proper VIRTIO-PCI vhost integration.
In QEMU, when the VIRTIO-PCI device is programmed with the MSI message,
we previously used direct_mapping trick: this consists in extracting the
IRQ ID found in the MSI
On ARM, the MSI msg (address and data) comes along with
out-of-band device ID information. The device ID encodes the
device that writes the MSI msg. Let's convey the device id in
kvm_irq_routing_msi and use KVM_MSI_VALID_DEVID flag value in
kvm_irq_routing_entry to indicate the msi devid is
on ARM, a devid field is populated in kvm_msi struct in case the
flag is set to KVM_MSI_VALID_DEVID. Let's propagate both flags and
devid field in kvm_kernel_irq_routing_entry.
Signed-off-by: Eric Auger
Reviewed-by: Andre Przywara
Acked-by:
This patch adds compilation and link against irqchip.
Main motivation behind using irqchip code is to enable MSI
routing code. In the future irqchip routing may also be useful
when targeting multiple irqchips.
Routing standard callbacks now are implemented in vgic-irqfd:
- kvm_set_routing_entry
2016-07-22 13:46+, Eric Auger:
> This patch adds compilation and link against irqchip.
>
> Main motivation behind using irqchip code is to enable MSI
> routing code. In the future irqchip routing may also be useful
> when targeting multiple irqchips.
>
> Routing standard callbacks now are
On Fri, Jul 22, 2016 at 10:43:21AM -0400, Andrew Jones wrote:
> Get arm emulation tests kick started by adding a couple pabt injection
> tests.
>
> Andrew Jones (2):
> arm64: add start_usr32
> arm64: add pabt injection test
>
> arm/Makefile.arm64| 2 +-
> arm/emul-abort.c
Hi Radim,
On 22/07/2016 15:39, Radim Krčmář wrote:
> 2016-07-21 23:10+0200, Auger Eric:
>> On 21/07/2016 18:33, Radim Krčmář wrote:
>>> 2016-07-18 13:25+, Eric Auger:
If the ITS modality is not available, let's simply support MSI
injection by transforming the MSI.data into an SPI
On Fri, Jul 22, 2016 at 11:42:02AM +0100, Andre Przywara wrote:
> Hi Stefan,
>
> On 22/07/16 06:57, Stefan Agner wrote:
> > Hi,
> >
> > I tried KVM on a Cortex-A7 platform (i.MX 7Dual SoC) and encountered
> > this stack trace immediately after invoking qemu-system-arm:
> >
> > Unable to handle
Signed-off-by: Andrew Jones
---
lib/arm64/asm/processor.h | 1 +
lib/arm64/processor.c | 21 +
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/lib/arm64/asm/processor.h b/lib/arm64/asm/processor.h
index 84d5c7ce752b..22687851379a
Get arm emulation tests kick started by adding a couple pabt injection
tests.
Andrew Jones (2):
arm64: add start_usr32
arm64: add pabt injection test
arm/Makefile.arm64| 2 +-
arm/emul-abort.c | 95 +++
arm/unittests.cfg
Signed-off-by: Andrew Jones
---
arm/Makefile.arm64 | 2 +-
arm/emul-abort.c | 95 ++
arm/unittests.cfg | 25 ++
3 files changed, 121 insertions(+), 1 deletion(-)
create mode 100644 arm/emul-abort.c
diff
Enhance kvm_kernel_irq_routing_entry to transport the device id
field, devid. A new flags field makes possible to indicate the
devid is valid. Those additions are used for ARM GICv3 ITS MSI
injection. The original struct msi_msg msi field is replaced by
a new custom structure that embeds the new
Up to now, only irqchip routing entries could be set. This patch
adds the capability to insert MSI routing entries.
For ARM64, let's also increase KVM_MAX_IRQ_ROUTES to 4096: this
include SPI irqchip routes plus MSI routes. In the future this
might be extended.
Signed-off-by: Eric Auger
kvm_setup_default_irq_routing and kvm_setup_empty_irq_routing are
not used by generic code. So let's move the declarations in x86 irq.h
header instead of kvm_host.h.
Signed-off-by: Eric Auger
Suggested-by: Andre Przywara
---
- new patch in v7
---
If the ITS modality is not available, let's simply support MSI
injection by transforming the MSI.data into an SPI ID.
This becomes possible to use KVM_SIGNAL_MSI ioctl and MSI
routing for arm too.
Signed-off-by: Eric Auger
---
v6 -> v7:
- move vgic_v2m_inject_msi into
On 22/07/2016 16:14, Radim Krčmář wrote:
> 2016-07-22 13:46+, Eric Auger:
>> Up to now, only irqchip routing entries could be set. This patch
>> adds the capability to insert MSI routing entries.
>>
>> For ARM64, let's also increase KVM_MAX_IRQ_ROUTES to 4096: this
>> include SPI irqchip
Hi Radim
On 22/07/2016 16:24, Radim Krčmář wrote:
> 2016-07-22 13:46+, Eric Auger:
>> This patch adds compilation and link against irqchip.
>>
>> Main motivation behind using irqchip code is to enable MSI
>> routing code. In the future irqchip routing may also be useful
>> when targeting
On 22/07/16 15:35, Andrew Jones wrote:
> On Fri, Jul 22, 2016 at 11:42:02AM +0100, Andre Przywara wrote:
>> Hi Stefan,
>>
>> On 22/07/16 06:57, Stefan Agner wrote:
>>> Hi,
>>>
>>> I tried KVM on a Cortex-A7 platform (i.MX 7Dual SoC) and encountered
>>> this stack trace immediately after invoking
We need to set cpsr before determining the spsr bank, as the bank
depends on the target exception level of the injection, not the
current mode of the vcpu. Normally this is one in the same (EL1),
but not when we manage to trap an EL0 fault. It still doesn't really
matter for the 64-bit EL0 case
Hi,
On 22/07/2016 17:40, Marc Zyngier wrote:
> On 22/07/16 15:35, Andrew Jones wrote:
>> On Fri, Jul 22, 2016 at 11:42:02AM +0100, Andre Przywara wrote:
>>> Hi Stefan,
>>>
>>> On 22/07/16 06:57, Stefan Agner wrote:
Hi,
I tried KVM on a Cortex-A7 platform (i.MX 7Dual SoC) and
Enhance kvm_kernel_irq_routing_entry to transport the device id
field, devid. A new flags field makes possible to indicate the
devid is valid. Those additions are used for ARM GICv3 ITS MSI
injection. The original struct msi_msg msi field is replaced by
a new custom structure that embeds the new
This patch adds compilation and link against irqchip.
Main motivation behind using irqchip code is to enable MSI
routing code. In the future irqchip routing may also be useful
when targeting multiple irqchips.
Routing standard callbacks now are implemented in vgic-irqfd:
- kvm_set_routing_entry
Up to now, only irqchip routing entries could be set. This patch
adds the capability to insert MSI routing entries.
For ARM64, let's also increase KVM_MAX_IRQ_ROUTES to 4096: this
include SPI irqchip routes plus MSI routes. In the future this
might be extended.
Signed-off-by: Eric Auger
on ARM, a devid field is populated in kvm_msi struct in case the
flag is set to KVM_MSI_VALID_DEVID. Let's propagate both flags and
devid field in kvm_kernel_irq_routing_entry.
Signed-off-by: Eric Auger
Reviewed-by: Andre Przywara
Acked-by:
kvm_setup_default_irq_routing and kvm_setup_empty_irq_routing are
not used by generic code. So let's move the declarations in x86 irq.h
header instead of kvm_host.h.
Signed-off-by: Eric Auger
Suggested-by: Andre Przywara
---
- new patch in v7
---
From: Andre Przywara
Add emulation for some basic MMIO registers used in the ITS emulation.
This includes:
- GITS_{CTLR,TYPER,IIDR}
- ID registers
- GITS_{CBASER,CREADR,CWRITER}
(which implement the ITS command buffer handling)
- GITS_BASER
Most of the handlers are
From: Andre Przywara
The kvm_io_bus framework is a nice place of holding information about
various MMIO regions for kernel emulated devices.
Add a call to retrieve the kvm_io_device structure which is associated
with a certain MMIO address. This avoids to duplicate
Now that we only have the "merged page tables" case to deal with,
there is a bunch of things we can simplify in the HYP code (both
at init and teardown time).
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
HYP_PAGE_OFFSET is not massively useful. And the way we use it
in KERN_HYP_VA is inconsistent with the equivalent operation in
EL2, where we use a mask instead.
Let's replace the uses of HYP_PAGE_OFFSET with HYP_PAGE_OFFSET_MASK,
and get rid of the pointless macro.
Signed-off-by: Marc Zyngier
Add the code that enables the switch to the lower HYP VA range.
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
arch/arm64/kernel/cpufeature.c | 19 +++
1 file changed, 19 insertions(+)
diff --git
From: Andre Przywara
The connection between a device, an event ID, the LPI number and the
associated CPU is stored in in-memory tables in a GICv3, but their
format is not specified by the spec. Instead software uses a command
queue in a ring buffer to let an ITS
This is more of a safety measure than anything else: If we end-up
with an idmap page that intersect with the range picked for the
the HYP VA space, abort the KVM setup, as it is unsafe to go
further.
I cannot imagine it happening on 64bit (we have a mechanism to
work around it), but could
From: Andre Przywara
The ARM GICv3 ITS MSI controller requires a device ID to be able to
assign the proper interrupt vector. On real hardware, this ID is
sampled from the bus. To be able to emulate an ITS controller, extend
the KVM MSI interface to let userspace provide
From: Eric Auger
For VGICv2 save and restore the CPU interface registers
are accessed. Restore the modality which has been altered.
Also explicitly set the iodev_type for both the DIST and CPU
interface.
Signed-off-by: Eric Auger
Signed-off-by:
As we need to indicate to the rest of the kernel which region of
the HYP VA space is safe to use, add a capability that will
indicate that KVM should use the [VA_BITS-2:0] range.
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
Declare the __hyp_text_start/end symbols in asm/virt.h so that
they can be reused without having to declare them locally.
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
arch/arm/include/asm/virt.h | 4
There is no need to have separate functions to validate devices
and collections, as the architecture doesn't really distinguish the
two, and they are supposed to be managed the same way.
Let's turn the DevID checker into a generic one.
Signed-off-by: Marc Zyngier
---
Instead of sprinkling raw kref_get() calls everytime we cannot
do a normal vgic_get_irq(), use the existing vgic_get_irq_kref(),
which does the same thing and is paired with a vgic_put_irq().
vgic_get_irq_kref is moved to vgic.h in order to be easily shared.
Signed-off-by: Marc Zyngier
From: Andre Przywara
kvm_register_device_ops() can return an error, so lets check its return
value and propagate this up the call chain.
Signed-off-by: Andre Przywara
Reviewed-by: Marc Zyngier
Tested-by: Eric Auger
Just like for arm64, we can now make the HYP setup a lot simpler,
and we can now initialise it in one go (instead of the two
phases we currently have).
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
From: Andre Przywara
LPIs are dynamically created (mapped) at guest runtime and their
actual number can be quite high, but is mostly assigned using a very
sparse allocation scheme. So arrays are not an ideal data structure
to hold the information.
We use a spin-lock
If we care to move all the checks that do not involve any memory
allocation, we can simplify the MAPI error handling. Let's do that,
it cannot hurt.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 30 --
1 file changed, 12
The current code will fail on valid indirect tables, and happily
use the ones that are pointing out of the guest RAM. Funny what a
small "!" can do for you...
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 6 +++---
1 file changed, 3 insertions(+), 3
vgic_its_cmd_handle_mapi has an extra "subcmd" argument, which is
already contained in the command buffer that all command handlers
obtain from the command queue. Let's drop it, as it is not that
useful.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 11
When checking that the storage address of a device entry is valid,
it is critical to compute the actual address of the entry, rather
than relying on the beginning of the page to match a CPU page of
the same size: for example, if the guest places the table at the
last 64kB boundary of RAM, but RAM
Checking that the device_id fits if the table, and we must make
sure that the associated memory is also accessible.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git
The nr_entries variable in vgic_its_check_device_id actually
describe the size of the L1 table, and not the number of
entries in this table.
Rename it to l1_tbl_size, so that we can now change the code
with a better understanding of what is what.
Signed-off-by: Marc Zyngier
Define the two possible HYP VA regions in terms of VA_BITS,
and keep HYP_PAGE_OFFSET_MASK as a temporary compatibility
definition.
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
arch/arm64/include/asm/kvm_mmu.h | 8 ++--
1
Since we now only have one set of page tables, the concept of
boot_pgd is useless and can be removed. We still keep it as
an element of the "extended idmap" thing.
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
From: Andre Przywara
arm-gic-v3.h contains bit and register definitions for the GICv3 and ITS,
at least for the bits the we currently care about.
The ITS emulation needs more definitions, so add them and refactor
the memory attribute #defines to be more universally
From: Andre Przywara
In the moment our struct vgic_irq's are statically allocated at guest
creation time. So getting a pointer to an IRQ structure is trivial and
safe. LPIs are more dynamic, they can be mapped and unmapped at any time
during the guest's _runtime_.
In
In order to be able to use C code in HYP, we're now mapping the kernel's
rodata in HYP. It works absolutely fine, except that we're mapping it RWX,
which is not what it should be.
Add a new HYP_PAGE_RO protection, and pass it as the protection flags
when mapping the rodata section.
Structures that can be generally written to don't have any requirement
to be executable (quite the opposite). This includes the kvm and vcpu
structures, as well as the stacks.
Let's change the default to incorporate the XN flag.
Signed-off-by: Marc Zyngier
Signed-off-by:
We're in a position where we can now always have "merged" page
tables, where both the runtime mapping and the idmap coexist.
This results in some code being removed, but there is more to come.
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
There is no way to free the boot PGD, because it doesn't exist
anymore as a standalone entity.
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
arch/arm/include/asm/kvm_mmu.h | 1 -
arch/arm/kvm/arm.c | 4
From: Dan Carpenter
My static checker complains that this condition looks like it should be
== instead of =. This isn't a fast path, so we don't need to be fancy.
Signed-off-by: Dan Carpenter
Signed-off-by: Marc Zyngier
From: Andre Przywara
Logically a GICv3 redistributor is assigned to a (v)CPU, so we should
aim to keep redistributor related variables out of our struct vgic_dist.
Let's start by replacing the redistributor related kvm_io_device array
with two members in our existing
As we move towards a selectable HYP VA range, it is obvious that
we don't want to test a variable to find out if we need to use
the bottom VA range, the top VA range, or use the address as is
(for VHE).
Instead, we can expand our current helper to generate the right
mask or nop with code
__hyp_panic_string is passed via the HYP panic code to the panic
function, and is being "upgraded" to a kernel address, as it is
referenced by the HYP code (in a PC-relative way).
This is a bit silly, and we'd be better off obtaining the kernel
address and not mess with it at all. This patch
Paolo, Radim,
Please find below the first batch of 4.8 updates for KVM/ARM. Biggest
feature is the long awaited GICv3 ITS emulation, allowing MSIs to be
delivered into guests running on GICv3 HW. The other big feature is
the removal of the old vgic implementation. Less visible is the revamp
of
Since dealing with VA ranges tends to hurt my brain badly, let's
start with a bit of documentation that will hopefully help
understanding what comes next...
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
hyp_kern_va is now completely unused, so let's remove it entirely.
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
arch/arm/include/asm/kvm_hyp.h | 1 -
arch/arm64/include/asm/kvm_hyp.h | 12
2 files changed, 13
From: Andre Przywara
KVM capabilities can be a per-VM property, though ARM/ARM64 currently
does not pass on the VM pointer to the architecture specific
capability handlers.
Add a "struct kvm*" parameter to those function to later allow proper
per-VM capability reporting.
We have both KERN_TO_HYP and kern_hyp_va, which do the exact same
thing. Let's standardize on the latter.
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
arch/arm/include/asm/kvm_hyp.h | 2 --
arch/arm/include/asm/kvm_mmu.h
We can now remove a number of dead #defines, thanks to the trampoline
code being gone.
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
arch/arm/include/asm/kvm_mmu.h | 9 -
arch/arm64/include/asm/kvm_mmu.h | 10
So far, KVM was getting in the way of kexec on 32bit (and the arm64
kexec hackers couldn't be bothered to fix it on 32bit...).
With simpler page tables, tearing KVM down becomes very easy, so
let's just do it.
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
There should be no reason for mapping the HYP text read/write.
As such, let's have a new set of flags (PAGE_HYP_EXEC) that allows
execution, but makes the page as read-only, and update the two call
sites that deal with mapping code.
Signed-off-by: Marc Zyngier
EL2 page tables can be configured to deny code from being
executed, which is done by setting bit 54 in the page descriptor.
It is the same bit as PTE_UXN, but the "USER" reference felt odd
in the hypervisor code.
Signed-off-by: Marc Zyngier
Signed-off-by: Christoffer Dall
Currently, create_hyp_mappings applies a "one size fits all" page
protection (PAGE_HYP). As we're heading towards separate protections
for different sections, let's make this protection a parameter, and
let the callers pass their prefered protection (PAGE_HYP for everyone
for the time being).
On 2016-07-22 10:38, Andrew Jones wrote:
> On Fri, Jul 22, 2016 at 04:40:15PM +0100, Marc Zyngier wrote:
>> On 22/07/16 15:35, Andrew Jones wrote:
>> > On Fri, Jul 22, 2016 at 11:42:02AM +0100, Andre Przywara wrote:
>> >> Hi Stefan,
>> >>
>> >> On 22/07/16 06:57, Stefan Agner wrote:
>> >>> Hi,
>>
On 22/07/16 18:56, Stefan Agner wrote:
> On 2016-07-22 10:49, Marc Zyngier wrote:
>> On 22/07/16 18:38, Andrew Jones wrote:
>>> On Fri, Jul 22, 2016 at 04:40:15PM +0100, Marc Zyngier wrote:
On 22/07/16 15:35, Andrew Jones wrote:
> On Fri, Jul 22, 2016 at 11:42:02AM +0100, Andre Przywara
On Fri, Jul 22, 2016 at 04:40:15PM +0100, Marc Zyngier wrote:
> On 22/07/16 15:35, Andrew Jones wrote:
> > On Fri, Jul 22, 2016 at 11:42:02AM +0100, Andre Przywara wrote:
> >> Hi Stefan,
> >>
> >> On 22/07/16 06:57, Stefan Agner wrote:
> >>> Hi,
> >>>
> >>> I tried KVM on a Cortex-A7 platform
On Fri, Jul 22, 2016 at 04:37:35PM +0100, Marc Zyngier wrote:
> On 22/07/16 15:38, Andrew Jones wrote:
> > We need to set cpsr before determining the spsr bank, as the bank
> > depends on the target exception level of the injection, not the
> > current mode of the vcpu. Normally this is one in the
With the advent of GICv3 ITS in-kernel emulation, KVM MSI routing
becomes mandated for proper VIRTIO-PCI vhost integration.
In QEMU, when the VIRTIO-PCI device is programmed with the MSI message,
we previously used direct_mapping trick: this consists in extracting the
IRQ ID found in the MSI
On ARM, the MSI msg (address and data) comes along with
out-of-band device ID information. The device ID encodes the
device that writes the MSI msg. Let's convey the device id in
kvm_irq_routing_msi and use KVM_MSI_VALID_DEVID flag value in
kvm_irq_routing_entry to indicate the msi devid is
2016-07-22 16:20+, Eric Auger:
> With the advent of GICv3 ITS in-kernel emulation, KVM MSI routing
> becomes mandated for proper VIRTIO-PCI vhost integration.
Changes to interfaces and common code look ok,
Acked-by: Radim Krčmář
Good work.
From: Andre Przywara
The ARM GICv3 ITS emulation code goes into a separate file, but needs
to be connected to the GICv3 emulation, of which it is an option.
The ITS MMIO handlers require the respective ITS pointer to be passed in,
so we amend the existing VGIC MMIO
From: Andre Przywara
The LPI pending status for a GICv3 redistributor is held in a table
in (guest) memory. To achieve reasonable performance, we cache the
pending bit in our struct vgic_irq. The initial pending state must be
read from guest memory upon enabling LPIs for
The ITS tables are stored in LE format. If the host is reading
a L1 table entry to check its validity, it must convert it to
the CPU endianness.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
Let's restore some of the #defines that have been savagely dropped
by the introduction of the KVM ITS code, as pointlessly break
other users (including series that are already in -next).
Signed-off-by: Marc Zyngier
---
include/linux/irqchip/arm-gic-v3.h | 48
From: Andre Przywara
Introduce a new KVM device that represents an ARM Interrupt Translation
Service (ITS) controller. Since there can be multiple of this per guest,
we can't piggy back on the existing GICv3 distributor device, but create
a new type of KVM device.
On the
Instead of spreading random allocations all over the place,
consolidate allocation/init/freeing of collections in a pair
of constructor/destructor.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 92 ++--
1 file
From: Andre Przywara
Now that all ITS emulation functionality is in place, we advertise
MSI functionality to userland and also the ITS device to the guest - if
userland has configured that.
Signed-off-by: Andre Przywara
Reviewed-by: Marc Zyngier
Going from the ITS structure to the corresponding KVM structure
would be quite handy at times. The kvm_device pointer that is
passed at create time is quite convenient for this, so let's
keep a copy of it in the vgic_its structure.
This will be put to a good use in subsequent patches.
From: Andre Przywara
When userland wants to inject an MSI into the guest, it uses the
KVM_SIGNAL_MSI ioctl, which carries the doorbell address along with
the payload and the device ID.
With the help of the KVM IO bus framework we learn the corresponding
ITS from the
From: Andre Przywara
The (system-wide) LPI configuration table is held in a table in
(guest) memory. To achieve reasonable performance, we cache this data
in our struct vgic_irq. If the guest updates the configuration data
(which consists of the enable bit and the
From: Andre Przywara
In the GICv3 redistributor there are the PENDBASER and PROPBASER
registers which we did not emulate so far, as they only make sense
when having an ITS. In preparation for that emulate those MMIO
accesses by storing the 64-bit data written into it into
On 22/07/16 18:38, Andrew Jones wrote:
> On Fri, Jul 22, 2016 at 04:40:15PM +0100, Marc Zyngier wrote:
>> On 22/07/16 15:35, Andrew Jones wrote:
>>> On Fri, Jul 22, 2016 at 11:42:02AM +0100, Andre Przywara wrote:
Hi Stefan,
On 22/07/16 06:57, Stefan Agner wrote:
> Hi,
>
On Fri, 22 Jul 2016 21:45:00 +0200
Andrew Jones wrote:
> On Fri, Jul 22, 2016 at 07:06:36PM +0100, Marc Zyngier wrote:
> > On 22/07/16 18:38, Andrew Jones wrote:
> > > On Fri, Jul 22, 2016 at 04:40:15PM +0100, Marc Zyngier wrote:
> > >> On 22/07/16 15:35, Andrew Jones
On Fri, Jul 22, 2016 at 07:06:36PM +0100, Marc Zyngier wrote:
> On 22/07/16 18:38, Andrew Jones wrote:
> > On Fri, Jul 22, 2016 at 04:40:15PM +0100, Marc Zyngier wrote:
> >> On 22/07/16 15:35, Andrew Jones wrote:
> >>> On Fri, Jul 22, 2016 at 11:42:02AM +0100, Andre Przywara wrote:
> Hi
Hi,
I tried KVM on a Cortex-A7 platform (i.MX 7Dual SoC) and encountered
this stack trace immediately after invoking qemu-system-arm:
Unable to handle kernel paging request at virtual address ffe4
pgd = 8ca52740
[ffe4] *pgd=8080007003, *pmd=8ff7e003, *pte=
Internal error:
Hi Stefan,
On 22/07/16 06:57, Stefan Agner wrote:
> Hi,
>
> I tried KVM on a Cortex-A7 platform (i.MX 7Dual SoC) and encountered
> this stack trace immediately after invoking qemu-system-arm:
>
> Unable to handle kernel paging request at virtual address ffe4
> pgd = 8ca52740
> [ffe4]
Hi Marc,
On 22/07/2016 09:47, Marc Zyngier wrote:
> Hi Stefan,
>
> On 22/07/16 06:57, Stefan Agner wrote:
>> Hi,
>>
>> I tried KVM on a Cortex-A7 platform (i.MX 7Dual SoC) and encountered
>> this stack trace immediately after invoking qemu-system-arm:
>>
>> Unable to handle kernel paging request
On 22/07/16 08:52, Auger Eric wrote:
> Hi Marc,
>
> On 22/07/2016 09:47, Marc Zyngier wrote:
>> Hi Stefan,
>>
>> On 22/07/16 06:57, Stefan Agner wrote:
>>> Hi,
>>>
>>> I tried KVM on a Cortex-A7 platform (i.MX 7Dual SoC) and encountered
>>> this stack trace immediately after invoking
Hi Marc,
On 2016-07-22 00:47, Marc Zyngier wrote:
> Hi Stefan,
>
> On 22/07/16 06:57, Stefan Agner wrote:
>> Hi,
>>
>> I tried KVM on a Cortex-A7 platform (i.MX 7Dual SoC) and encountered
>> this stack trace immediately after invoking qemu-system-arm:
>>
>> Unable to handle kernel paging request
On 22/07/16 06:57, Stefan Agner wrote:
> Hi,
>
> I tried KVM on a Cortex-A7 platform (i.MX 7Dual SoC) and encountered
> this stack trace immediately after invoking qemu-system-arm:
>
> Unable to handle kernel paging request at virtual address ffe4
> pgd = 8ca52740
> [ffe4]
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