Re: v4.9-rc1 fails booting as a guest on ARM64 Cavium ThunderX

On 21.10.16 13:52:43, Marc Zyngier wrote: > On 21/10/16 13:07, Andrew Jones wrote: > > On Fri, Oct 21, 2016 at 12:57:37PM +0100, Peter Maydell wrote: > >> On 21 October 2016 at 12:49, Andrew Jones wrote: > >>> I also read the register before writing it and saw it was 3. I

[PATCH V4 05/10] acpi: apei: handle SEA notification type for ARMv8

ARM APEI extension proposal added SEA (Synchrounous External Abort) notification type for ARMv8. Add a new GHES error source handling function for SEA. If an error source's notification type is SEA, then this function can be registered into the SEA exception handler. That way GHES will parse and

[PATCH V4 07/10] efi: print unrecognized CPER section

UEFI spec allows for non-standard section in Common Platform Error Record. This is defined in section N.2.3 of UEFI version 2.5. Currently if the CPER section's type (UUID) does not match with one of the section types that the kernel knows how to parse, the section is skipped. Therefore, user is

[PATCH V4 00/10] Add UEFI 2.6 and ACPI 6.1 updates for RAS on ARM64

When a memory error, CPU error, PCIe error, or other type of hardware error that's covered by RAS occurs, firmware should populate the shared GHES memory location with the proper GHES structures to notify the OS of the error. For example, platforms that implement firmware first handling may

[PATCH V4 03/10] efi: parse ARMv8 processor error

Add support for ARMv8 Common Platform Error Record (CPER). UEFI 2.6 specification adds support for ARMv8 specific processor error information to be reported as part of the CPER records. This provides more detail on for processor error logs. Signed-off-by: Jonathan (Zhixiong) Zhang

[PATCH V4 04/10] arm64: exception: handle Synchronous External Abort

SEA exceptions are often caused by an uncorrected hardware error, and are handled when data abort and instruction abort exception classes have specific values for their Fault Status Code. When SEA occurs, before killing the process, go through the handlers registered in the notification list.

[PATCH V4 06/10] acpi: apei: panic OS with fatal error status block

From: "Jonathan (Zhixiong) Zhang" Even if an error status block's severity is fatal, the kernel does not honor the severity level and panic. With the firmware first model, the platform could inform the OS about a fatal hardware error through the non-NMI GHES notification

[PATCH V4 02/10] ras: acpi/apei: cper: generic error data entry v3 per ACPI 6.1

Currently when a RAS error is reported it is not timestamped. The ACPI 6.1 spec adds the timestamp field to the generic error data entry v3 structure. The timestamp of when the firmware generated the error is now being reported. Signed-off-by: Jonathan (Zhixiong) Zhang

[PATCH V4 01/10] acpi: apei: read ack upon ghes record consumption

A RAS (Reliability, Availability, Serviceability) controller may be a separate processor running in parallel with OS execution, and may generate error records for consumption by the OS. If the RAS controller produces multiple error records, then they may be overwritten before the OS has consumed

[PATCH V4 10/10] arm64: KVM: add guest SEA support

Currently external aborts are unsupported by the guest abort handling. Add handling for SEAs so that the host kernel reports SEAs which occur in the guest kernel. Signed-off-by: Tyler Baicar --- arch/arm/include/asm/kvm_arm.h | 1 +

[PATCH V4 08/10] ras: acpi / apei: generate trace event for unrecognized CPER section

UEFI spec allows for non-standard section in Common Platform Error Record. This is defined in section N.2.3 of UEFI version 2.5. Currently if the CPER section's type (UUID) does not match with any section type that the kernel knows how to parse, trace event is not generated for such section. And

[PATCH V4 09/10] trace, ras: add ARM processor error trace event

Currently there are trace events for the various RAS errors with the exception of ARM processor type errors. Add a new trace event for such errors so that the user will know when they occur. These trace events are consistent with the ARM processor error section type defined in UEFI 2.6 spec

Re: [PATCH V4 09/10] trace, ras: add ARM processor error trace event

On Fri, 21 Oct 2016 11:30:12 -0600 Tyler Baicar wrote: > Currently there are trace events for the various RAS > errors with the exception of ARM processor type errors. > Add a new trace event for such errors so that the user > will know when they occur. These trace events

Re: v4.9-rc1 fails booting as a guest on ARM64 Cavium ThunderX

On 21 October 2016 at 12:49, Andrew Jones wrote: > I also read the register before writing it and saw it was 3. I tried > writing 3 instead of 0 to see what would happen, but the failure > persisted. I did read back the register after writing it to confirm the > change took

Re: v4.9-rc1 fails booting as a guest on ARM64 Cavium ThunderX

On Fri, 21 Oct 2016 15:06:39 +0200 Andrew Jones wrote: > On Fri, Oct 21, 2016 at 01:52:43PM +0100, Marc Zyngier wrote: > > On 21/10/16 13:07, Andrew Jones wrote: > > > On Fri, Oct 21, 2016 at 12:57:37PM +0100, Peter Maydell wrote: > > >> On 21 October 2016 at 12:49,

Re: v4.9-rc1 fails booting as a guest on ARM64 Cavium ThunderX

On Fri, 21 Oct 2016 13:58:47 +0100 Peter Maydell wrote: > On 21 October 2016 at 13:52, Marc Zyngier wrote: > > diff --git a/arch/arm/include/asm/arch_gicv3.h > > b/arch/arm/include/asm/arch_gicv3.h > > index a808829..5c03171 100644 > > ---

Re: v4.9-rc1 fails booting as a guest on ARM64 Cavium ThunderX

On Fri, Oct 21, 2016 at 11:46:04AM +0200, Auger Eric wrote: > Hi Marc, > On 21/10/2016 11:40, Marc Zyngier wrote: > > On 21/10/16 10:05, Auger Eric wrote: > >> Hi Marc, > >> > >> On 21/10/2016 10:45, Marc Zyngier wrote: > >>> +Robert > >>> > >>> On 21/10/16 08:01, Auger Eric wrote: > Hi, >

Re: v4.9-rc1 fails booting as a guest on ARM64 Cavium ThunderX

On 21/10/16 13:07, Andrew Jones wrote: > On Fri, Oct 21, 2016 at 12:57:37PM +0100, Peter Maydell wrote: >> On 21 October 2016 at 12:49, Andrew Jones wrote: >>> I also read the register before writing it and saw it was 3. I tried >>> writing 3 instead of 0 to see what would

Re: v4.9-rc1 fails booting as a guest on ARM64 Cavium ThunderX

On Fri, Oct 21, 2016 at 12:57:37PM +0100, Peter Maydell wrote: > On 21 October 2016 at 12:49, Andrew Jones wrote: > > I also read the register before writing it and saw it was 3. I tried > > writing 3 instead of 0 to see what would happen, but the failure > > persisted. I did

Re: v4.9-rc1 fails booting as a guest on ARM64 Cavium ThunderX

On Fri, Oct 21, 2016 at 01:52:43PM +0100, Marc Zyngier wrote: > On 21/10/16 13:07, Andrew Jones wrote: > > On Fri, Oct 21, 2016 at 12:57:37PM +0100, Peter Maydell wrote: > >> On 21 October 2016 at 12:49, Andrew Jones wrote: > >>> I also read the register before writing it and

[RFC PATCH 1/8] irqchip/gic-v3-its: Change unsigned types for AArch32 compatibility

Make sure that constants which are supposed to be applied on 64-bit data is actually unsigned long long, so they won't be truncated when used in 32-bit mode. Signed-off-by: Vladimir Murzin --- drivers/irqchip/irq-gic-v3-its.c | 28 ++--

[RFC PATCH 5/8] ARM: gic-v3-its: Add 32bit support to GICv3 ITS

Wire-up flush_dcache, readq- and writeq-like gic-v3-its assessors, so GICv3 ITS gets all it needs to be built and run. Signed-off-by: Vladimir Murzin --- arch/arm/include/asm/arch_gicv3.h | 59 - 1 file changed, 52 insertions(+), 7

[RFC PATCH 8/8] ARM: KVM: Support vGICv3 ITS

This patch allows to build and use vGICv3 ITS in 32-bit mode. Signed-off-by: Vladimir Murzin --- Documentation/virtual/kvm/api.txt |2 +- arch/arm/include/uapi/asm/kvm.h |2 ++ arch/arm/kvm/Kconfig|1 + arch/arm/kvm/Makefile

[RFC PATCH 4/8] irqchip/gicv3-its: specialise readq and writeq accesses

readq and writeq type of assessors are not supported in AArch32, so we need to specialise them and glue later with series of 32-bit accesses on AArch32 side. Signed-off-by: Vladimir Murzin --- arch/arm64/include/asm/arch_gicv3.h | 16

[RFC PATCH 2/8] irqchip/gic-v3-its: narrow down Entry Size when used as a divider

GITS_BASER's Entry Size is much smaller than 64-bit, but when it used as a divider it forces compiler to generate __aeabi_uldivmod if build in 32-bit mode. So, casting it to int (like it is done in other places) where used as a divider would give a hint to compiler that 32-bit division can be

[RFC PATCH 0/8] Support GICv3 ITS and vITS in 32-bit mode

Hi, This series introduces GICv3 ITS and vITS to 32-bit world. The first six patches make it possible to use ITS in a 32-bit guest with vITS on 64-bit host. The last two patches extend vITS to 32-bit host. I used Andrea's its/v8 branch at [1] for testing with the following diff on top diff

[RFC PATCH 7/8] KVM: arm64: vgic-its: fix compatability with 32-bit

Evaluate GITS_BASER_ENTRY_SIZE once as an int data (GITS_BASER's Entry Size is 5-bit wide only), so when used as divider no reference to __aeabi_uldivmod is generated when build for AArch32. Use unsigned long long for GITS_BASER_PAGE_SIZE_* since they are used in conjunction with 64-bit data.

Re: v4.9-rc1 fails booting as a guest on ARM64 Cavium ThunderX

+Robert On 21/10/16 08:01, Auger Eric wrote: > Hi, > > I am not able to boot 4.9-rc1 as a guest on Cavium ThunderX (dt and acpi > mode). Bisecting the guest shows that the problem shows up at > > 91ef84428a86b75a52e15c6fe4f56b446ba75f93 > irqchip/gic-v3: Reset BPR during initialization > > If

Re: v4.9-rc1 fails booting as a guest on ARM64 Cavium ThunderX

Hi Marc, On 21/10/2016 10:45, Marc Zyngier wrote: > +Robert > > On 21/10/16 08:01, Auger Eric wrote: >> Hi, >> >> I am not able to boot 4.9-rc1 as a guest on Cavium ThunderX (dt and acpi >> mode). Bisecting the guest shows that the problem shows up at >> >>

Re: [RFC PATCH 8/8] ARM: KVM: Support vGICv3 ITS

Hi, On 21/10/16 10:36, Vladimir Murzin wrote: > This patch allows to build and use vGICv3 ITS in 32-bit mode. Ah, what a relief to see that config option go. Thanks for that! I quickly booted an ITS guest on a (64-bit) model and couldn't spot any regressions. > Signed-off-by: Vladimir Murzin

Re: [RFC PATCH 8/8] ARM: KVM: Support vGICv3 ITS

On 21/10/16 12:02, Andre Przywara wrote: > Hi, > > On 21/10/16 10:36, Vladimir Murzin wrote: >> This patch allows to build and use vGICv3 ITS in 32-bit mode. > > Ah, what a relief to see that config option go. Thanks for that! > > I quickly booted an ITS guest on a (64-bit) model and couldn't