Re: [RFC PATCH 09/33] irqchip/gic-v3-its: Split out property table allocation

Hi Marc, On 17/01/2017 11:20, Marc Zyngier wrote: > Move the LPI property table allocation into its own function, as > this is going to be required for those associated with VMs in > the future. > > Signed-off-by: Marc Zyngier > --- > drivers/irqchip/irq-gic-v3-its.c | 28

Re: [RFC PATCH 07/33] irqchip/gic-v3-its: Macro-ize its_send_single_command

On 17/01/2017 11:20, Marc Zyngier wrote: > Most ITS commands do operate on a collection object, and require > a SYNC command to be performed on that collection in order to > guarantee the execution of the first command. > > With GICv4 ITS, another set of commands perform similar operations > on

Re: [RFC PATCH 08/33] irqchip/gic-v3-its: Implement irq_set_irqchip_state for pending state

On 17/01/2017 11:20, Marc Zyngier wrote: > Allow the pending state of an LPI to be set or cleared via > irq_set_irqchip_state. > > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger Eric > --- > drivers/irqchip/irq-gic-v3-its.c | 78 >

Re: [RFC PATCH 10/33] irqchip/gic-v4-its: Allow use of indirect VCPU tables

Hi Marc, On 17/01/2017 11:20, Marc Zyngier wrote: > The VCPU tables can be quite sparse as well, and it makes sense > to use indirect tables as well if possible. > > Signed-off-by: Marc Zyngier > --- > drivers/irqchip/irq-gic-v3-its.c | 20 +--- > 1 file

Re: [PATCH] KVM: race-free exit from KVM_RUN without POSIX signals

> post_kvm_run_save(vcpu); > diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h > index 7964b970b9ad..f51d5082a377 100644 > --- a/include/uapi/linux/kvm.h > +++ b/include/uapi/linux/kvm.h > @@ -218,7 +218,8 @@ struct kvm_hyperv_exit { > struct kvm_run { > /* in */ >

Re: [PATCH V10 05/10] acpi: apei: handle SEA notification type for ARMv8

On 15 February 2017 at 19:51, Tyler Baicar wrote: > ARM APEI extension proposal added SEA (Synchronous External Abort) > notification type for ARMv8. > Add a new GHES error source handling function for SEA. If an error > source's notification type is SEA, then this

Re: [PATCH V10 03/10] efi: parse ARM processor error

On 15 February 2017 at 19:51, Tyler Baicar wrote: > Add support for ARM Common Platform Error Record (CPER). > UEFI 2.6 specification adds support for ARM specific > processor error information to be reported as part of the > CPER records. This provides more detail on for

Re: [PATCH V10 02/10] ras: acpi/apei: cper: generic error data entry v3 per ACPI 6.1

On 15 February 2017 at 19:51, Tyler Baicar wrote: > Currently when a RAS error is reported it is not timestamped. > The ACPI 6.1 spec adds the timestamp field to the generic error > data entry v3 structure. The timestamp of when the firmware > generated the error is now

Re: [PATCH] KVM: race-free exit from KVM_RUN without POSIX signals

2017-02-15 15:43+0100, Paolo Bonzini: > The purpose of the KVM_SET_SIGNAL_MASK API is to let userspace "kick" > a VCPU out of KVM_RUN through a POSIX signal. A signal is attached > to a dummy signal handler; by blocking the signal outside KVM_RUN and > unblocking it inside, this possible race is

Re: [RFC PATCH 07/33] irqchip/gic-v3-its: Macro-ize its_send_single_command

Hi, On 17/01/2017 11:20, Marc Zyngier wrote: > Most ITS commands do operate on a collection object, and require > a SYNC command to be performed on that collection in order to > guarantee the execution of the first command. > > With GICv4 ITS, another set of commands perform similar operations >

Re: [RFC PATCH 08/33] irqchip/gic-v3-its: Implement irq_set_irqchip_state for pending state

Marc, On 17/01/2017 11:20, Marc Zyngier wrote: > Allow the pending state of an LPI to be set or cleared via > irq_set_irqchip_state. > > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger Eric > --- > drivers/irqchip/irq-gic-v3-its.c | 78 >

Re: [RFC PATCH 06/33] irqchip/gic-v3-its: Add probing for VLPI properties

Hi, On 13/02/2017 11:00, Thomas Gleixner wrote: > On Tue, 17 Jan 2017, Marc Zyngier wrote: >> +typer = gic_read_typer(its_base + GITS_TYPER); >> its->base = its_base; >> its->phys_base = res->start; >> -its->ite_size = ((gic_read_typer(its_base + GITS_TYPER) >> 4) & 0xf) + >>

Re: [RFC PATCH 04/33] irqchip/gic-v3-its: Move LPI definitions around

Hi Marc, On 17/01/2017 11:20, Marc Zyngier wrote: > The various LPI definitions are in the middle of the code, and > would be better placed at the beginning, given that we're going > to use some of them much earlier. > > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger

Re: [RFC PATCH 02/33] irqchip/gic-v3: Add VLPI/DirectLPI discovery

Hi, On 17/01/2017 11:20, Marc Zyngier wrote: > Add helper functions that probe for VLPI and DirectLPI properties. > > Signed-off-by: Marc Zyngier Besides the returned value previous questions, Reviewed-by: Eric Auger Eric > --- >

Re: [RFC PATCH 03/33] irqchip/gic-v3-its: Refactor command encoding

On 17/01/2017 11:20, Marc Zyngier wrote: > The way we encode the various ITS command fields is both tedious > and error prone. Let's introduce a helper function that performs > the encoding, and convert the existing encoders to use that > helper. > > Signed-off-by: Marc Zyngier

Re: [RFC PATCH 01/33] irqchip/gic-v3: Add redistributor iterator

Hi Marc, On 17/01/2017 11:20, Marc Zyngier wrote: > In order to discover the VLPI properties, we need to iterate over > the redistributor regions. As we already have code that does this, > let's factor it out and make it slightly more generic. > > Signed-off-by: Marc Zyngier

Re: [PATCH] KVM: arm64: VGIC: fix command handling while ITS being disabled

Hi Andre, On 16/02/2017 11:41, Andre Przywara wrote: > The ITS spec says that ITS commands are only processed when the ITS > is enabled (section 8.19.4, Enabled, bit[0]). Our emulation was not taking > this into account. > Fix this by checking the enabled state before handling CWRITER writes.

[PATCH] KVM: arm64: VGIC: fix command handling while ITS being disabled

The ITS spec says that ITS commands are only processed when the ITS is enabled (section 8.19.4, Enabled, bit[0]). Our emulation was not taking this into account. Fix this by checking the enabled state before handling CWRITER writes. On the other hand that means that CWRITER could advance while