Re: [PATCH 12/15] arm-soc: omap: replace open coded VA->PA calculations

* Ard Biesheuvel [170805 13:54]: > This replaces a couple of open coded calculations to obtain the > physical address of a far symbol with calls to the new adr_l etc > macros. I gave this series a quick test and omap3 no longer boots it seems. Regards, Tony

Re: [PATCH v2 06/16] arm64: entry.S: convert elX_sync

Hi James, On Fri, Jul 28, 2017 at 03:10:09PM +0100, James Morse wrote: > @@ -520,9 +514,16 @@ el1_preempt: > el0_sync: > kernel_entry 0 > mrs x25, esr_el1// read the syndrome register > + mrs x26, far_el1 Just checking, since we are going to access

Re: [PATCH 01/11] KVM: arm64: Store vcpu on the stack during __guest_enter()

On Tue, Aug 08, 2017 at 05:48:29PM +0100, James Morse wrote: > Hi Christoffer, > > On 06/06/17 20:59, Christoffer Dall wrote: > > On Mon, May 15, 2017 at 06:43:49PM +0100, James Morse wrote: > >> KVM uses tpidr_el2 as its private vcpu register, which makes sense for > >> non-vhe world switch as

[PATCH 06/27] arm64/sve: System register and exception syndrome definitions

The SVE architecture adds some system registers, ID register fields and a dedicated ESR exception class. This patch adds the appropriate definitions that will be needed by the kernel. Signed-off-by: Dave Martin --- arch/arm64/include/asm/esr.h | 3 ++-

[PATCH 00/27] ARM Scalable Vector Extension (SVE)

This series implements Linux kernel support for the ARM Scalable Vector Extension (SVE). [1] It supersedes the previous RFC: see [6] for link and a summary of changes. This series depends on some series that are headed for v4.14: see [3], [4], [5]. To reduce spam, some people may not been

[PATCH 05/27] arm64: fpsimd: Simplify uses of {set, clear}_ti_thread_flag()

The existing FPSIMD context switch code contains a couple of instances of {set,clear}_ti_thread(task_thread_info(task)). Since there are thread flag manipulators that operate directly on task_struct, this verbosity isn't strictly needed. For consistency, this patch simplifies the affected calls.

[PATCH 04/27] arm64: Port deprecated instruction emulation to new sysctl interface

Currently, armv8_deprected.c takes charge of the "abi" sysctl directory, which makes life difficult for other code that wants to register sysctls in the same directory. There is a "new" [1] sysctl registration interface that removes the need to define ctl_tables for parent directories explicitly,

[PATCH 02/27] arm64: KVM: Hide unsupported AArch64 CPU features from guests

Currently, a guest kernel sees the true CPU feature registers (ID_*_EL1) when it reads them using MRS instructions. This means that the guest will observe features that are present in the hardware but the host doesn't understand or doesn't provide support for. A guest may legimitately try to use

[PATCH 01/27] regset: Add support for dynamically sized regsets

Currently the regset API doesn't allow for the possibility that regsets (or at least, the amount of meaningful data in a regset) may change in size. In particular, this results in useless padding being added to coredumps in a regset's current size is smaller than its theoretical maximum size.

[PATCH 07/27] arm64/sve: Low-level SVE architectural state manipulation functions

Manipulating the SVE architectural state, including the vector and predicate registers, first-fault register and the vector length, requires the use of dedicated instructions added by SVE. This patch adds suitable assembly functions for saving and restoring the SVE registers and querying the

[PATCH 08/27] arm64/sve: Kconfig update and conditional compilation support

This patch adds CONFIG_ARM64_SVE to control building of SVE support into the kernel, and adds a stub predicate system_supports_sve() to control conditional compilation and runtime SVE support. system_supports_sve() just returns false for now: it will be replaced with a non-trivial implementation

[PATCH 11/27] arm64/sve: Core task context handling

This patch adds the core support for switching and managing the SVE architectural state of user tasks. Calls to the existing FPSIMD low-level save/restore functions are factored out as new functions task_fpsimd_{save,load}(), since SVE now dynamically may or may not need to be handled at these

[PATCH 09/27] arm64/sve: Signal frame and context structure definition

This patch defines the representation that will be used for the SVE register state in the signal frame, and implements support for saving and restoring the SVE registers around signals. The same layout will also be used for the in-kernel task state. Due to the variability of the SVE vector

[PATCH 10/27] arm64/sve: Low-level CPU setup

To enable the kernel to use SVE, all SVE traps from EL1 must be disabled. To take maximum advantage of the hardware, the full available vector length also needs to be enabled for EL1 by programming ZCR_EL2.LEN. (The kernel will program ZCR_EL1.LEN as required, but this cannot override the limit

[PATCH 12/27] arm64/sve: Support vector length resetting for new processes

It's desirable to be able to reset the vector length to some sane default for new processes, since the new binary and its libraries processes may or may not be SVE-aware. This patch tracks the desired post-exec vector length (if any) in a new thread member sve_vl_onexec, and adds a new thread

[PATCH 14/27] arm64/sve: Backend logic for setting the vector length

This patch implements the core logic for changing a task's vector length on request from userspace. This will be used by the ptrace and prctl frontends that are implemented in later patches. The SVE architecture permits, but does not require, implementations to support vector lengths that are

[PATCH 13/27] arm64/sve: Signal handling support

This patch implements support for saving and restoring the SVE registers around signals. A fixed-size header struct sve_context is always included in the signal frame encoding the thread's vector length at the time of signal delivery, optionally followed by a variable-layout structure encoding

[PATCH 15/27] arm64/sve: Probe SVE capabilities and usable vector lengths

This patch uses the cpufeatures framework to determine common SVE capabilities and vector lengths, and configures the runtime SVE support code appropriately. ZCR_ELx is not really a feature register, but it is convenient to use it as a template for recording the maximum vector length supported by

[PATCH 16/27] arm64/sve: Preserve SVE registers around kernel-mode NEON use

Kernel-mode NEON will corrupt the SVE vector registers, due to the way they alias the FPSIMD vector registers in the hardware. This patch ensures that any live SVE register content for the task is saved by kernel_neon_begin(). The data will be restored in the usual way on return to userspace.

[PATCH 19/27] arm64/sve: Add prctl controls for userspace vector length management

This patch adds two arm64-specific prctls, to permit userspace to control its vector length: * PR_SVE_SET_VL: set the thread's SVE vector length and vector length inheritance mode. * PR_SVE_GET_VL: get the same information. Although these calls shadow instruction set features in the SVE

[PATCH 18/27] arm64/sve: ptrace and ELF coredump support

This patch defines and implements a new regset NT_ARM_SVE, which describes a thread's SVE register state. This allows a debugger to manipulate the SVE state, as well as being included in ELF coredumps for post-mortem debugging. Because the regset size and layout are dependent on the thread's

[PATCH 23/27] arm64/sve: KVM: Hide SVE from CPU features exposed to guests

KVM guests cannot currently use SVE, because SVE is always configured to trap to EL2. However, a guest that sees SVE reported as present in ID_AA64PFR0_EL1 may legitimately expect that SVE works and try to use it. Instead of working, the guest will receive an injected undef exception, which may

[PATCH 24/27] arm64/sve: Detect SVE and activate runtime support

This patch enables detection of hardware SVE support via the cpufeatures framework, and reports its presence to the kernel and userspace via the new ARM64_SVE cpucap and HWCAP_SVE hwcap respectively. Userspace can also detect SVE using ID_AA64PFR0_EL1, using the cpufeatures MRS emulation. When

[RFC PATCH 26/27] arm64: signal: Report signal frame size to userspace via auxv

Stateful CPU architecture extensions may require the signal frame to grow to a size that exceeds the arch's MINSIGSTKSZ #define. However, changing this #define is an ABI break. To allow userspace the option of determining the signal frame size in a more forwards-compatible way, this patch adds a

[PATCH 25/27] arm64/sve: Add documentation

This patch adds basic documentation of the user/kernel interface provided by the for SVE. Signed-off-by: Dave Martin --- Documentation/arm64/sve.txt | 454 1 file changed, 454 insertions(+) create mode 100644

[PATCH 20/27] arm64/sve: Add sysctl to set the default vector length for new processes

Because of the effect of SVE on the size of the signal frame, the default vector length used for new processes involves a tradeoff between performance of SVE-enabled software on the one hand, and reliability of non-SVE-aware software on the other hand. For this reason, the best choice depends on

[PATCH 21/27] arm64/sve: KVM: Prevent guests from using SVE

Until KVM has full SVE support, guests must not be allowed to execute SVE instructions. This patch enables the necessary traps, and also ensures that the traps are disabled again on exit from the guest so that the host can still use SVE if it wants to. Signed-off-by: Dave Martin

[PATCH 17/27] arm64/sve: Preserve SVE registers around EFI runtime service calls

The EFI runtime services ABI allows EFI to make free use of the FPSIMD registers during EFI runtime service calls, subject to the callee-save requirements of the AArch64 procedure call standard. However, the SVE architecture allows upper bits of the SVE vector registers to be zeroed as a

[PATCH 22/27] arm64/sve: KVM: Treat guest SVE use as undefined instruction execution

When trapping forbidden attempts by a guest to use SVE, we want the guest to see a trap consistent with SVE not being implemented. This patch injects an undefined instruction exception into the guest in response to such an exception. Signed-off-by: Dave Martin ---

[RFC PATCH 27/27] arm64/sve: signal: Include SVE when computing AT_MINSIGSTKSZ

The SVE context block in the signal frame needs to be considered too when computing the maximum possible signal frame size. Because the size of this block depends on the vector length, this patch computes the size based not on the thread's current vector length but instead on the maximum possible

Re: [PATCH 12/15] arm-soc: omap: replace open coded VA->PA calculations

On 9 August 2017 at 20:05, Tony Lindgren wrote: > * Ard Biesheuvel [170805 13:54]: >> This replaces a couple of open coded calculations to obtain the >> physical address of a far symbol with calls to the new adr_l etc >> macros. > > I gave this series

Re: [PATCH 12/15] arm-soc: omap: replace open coded VA->PA calculations

* Ard Biesheuvel [170809 12:24]: > On 9 August 2017 at 20:05, Tony Lindgren wrote: > > * Ard Biesheuvel [170805 13:54]: > >> This replaces a couple of open coded calculations to obtain the > >> physical address of a far

kvm-unit-tests arm ptimer test

Hello, I have a general question on the ptimer test for KVM unit tests for the ARM/ARM64 platform, as the guest is only allowed to access to the physical counter and access to the physical timer is not allowed for the guest (CNTHCTL.EL1PCTEN is set and CNTHCTL.EL1PCEN is clear), so how is