Re: [PATCH v5 03/40] KVM: arm64: Avoid storing the vcpu pointer on the stack

Hi Christoffer, On 27/02/18 11:33, Christoffer Dall wrote: From: Christoffer Dall We already have the percpu area for the host cpu state, which points to the VCPU, so there's no need to store the VCPU pointer on the stack on every context switch. We can be a

Re: [RFC PATCH 2/2] KVM: arm64: Eliminate most redundant FPSIMD saves and restores

On Fri, Feb 23, 2018 at 06:08:44PM +0100, Christoffer Dall wrote: > Hi Dave, > > On Fri, Feb 16, 2018 at 06:29:31PM +, Dave Martin wrote: > > Currently, KVM doesn't know how host tasks interact with the cpu > > FPSIMD regs, and the host doesn't knoe how vcpus interact with the > > regs. As a

[PATCH] KVM: arm/arm64: Reset mapped IRQs on VM reset

We currently don't allow resetting mapped IRQs from userspace, because their state is controlled by the hardware. But we do need to reset the state when the VM is reset, so we provide a function for the 'owner' of the mapped interrupt to reset the interrupt state. Currently only the timer uses

Re: [PATCH v5 17/40] KVM: arm64: Move userspace system registers into separate function

Hi Christoffer, On 27/02/18 11:34, Christoffer Dall wrote: From: Christoffer Dall There's a semantic difference between the EL1 registers that control operation of a kernel running in EL1 and EL1 registers that only control userspace execution in EL0. Since we

[PATCH v2] arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening

The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead of Silicon provider service ID 0xC2001700. Signed-off-by: Shanker Donthineni

Re: [PATCH] arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening

Hi Shanker, On Fri, Mar 02, 2018 at 03:50:18PM -0600, Shanker Donthineni wrote: > The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC > V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses > the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead > of

Re: [REPOST PATCH] arm/arm64: KVM: Add PSCI version selection API

On 2 March 2018 at 12:26, Auger Eric wrote: > Hi Marc, > On 02/03/18 12:11, Marc Zyngier wrote: >> On Fri, 02 Mar 2018 10:44:48 +, >> Auger Eric wrote: >>> I understand the get/set is called as part of the migration process. >>> So my understanding is the benefit of

Re: [PATCH] arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening

On Fri, Mar 2, 2018 at 3:50 PM, Shanker Donthineni wrote: > diff --git a/arch/arm64/include/asm/cpucaps.h > b/arch/arm64/include/asm/cpucaps.h > index bb26382..6ecc249 100644 > --- a/arch/arm64/include/asm/cpucaps.h > +++ b/arch/arm64/include/asm/cpucaps.h > @@ -43,7

Re: [REPOST PATCH] arm/arm64: KVM: Add PSCI version selection API

On 2 March 2018 at 11:11, Marc Zyngier wrote: > On Fri, 02 Mar 2018 10:44:48 +, > Auger Eric wrote: >> I understand the get/set is called as part of the migration process. >> So my understanding is the benefit of this series is migration fails in >> those cases: >> >>

Re: [PATCH] arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening

Hi Will, On 03/05/2018 09:56 AM, Will Deacon wrote: > Hi Shanker, > > On Fri, Mar 02, 2018 at 03:50:18PM -0600, Shanker Donthineni wrote: >> The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC >> V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses >> the standard

Re: [PATCH] arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening

Hi Will, On 03/05/2018 11:15 AM, Will Deacon wrote: > On Mon, Mar 05, 2018 at 10:57:58AM -0600, Shanker Donthineni wrote: >> Hi Will, >> >> On 03/05/2018 09:56 AM, Will Deacon wrote: >>> Hi Shanker, >>> >>> On Fri, Mar 02, 2018 at 03:50:18PM -0600, Shanker Donthineni wrote: The function

Re: [PATCH] arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening

On Mon, Mar 05, 2018 at 10:57:58AM -0600, Shanker Donthineni wrote: > Hi Will, > > On 03/05/2018 09:56 AM, Will Deacon wrote: > > Hi Shanker, > > > > On Fri, Mar 02, 2018 at 03:50:18PM -0600, Shanker Donthineni wrote: > >> The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC > >>

can we define a KVM_REG_ARM encoding bit for NonSecure/Secure ?

Hi; I've just noticed a bug in QEMU where we weren't migrating Secure-bank register state for AArch32 emulated guest correctly, which turns out to be intertwined with how KVM defines its index values for cp15 registers in the KVM_REG_ARM_* encoding. The problem is that QEMU defines the

Re: [REPOST PATCH] arm/arm64: KVM: Add PSCI version selection API

Hi Peter, On 05/03/18 17:31, Peter Maydell wrote: > On 2 March 2018 at 12:26, Auger Eric wrote: >> Hi Marc, >> On 02/03/18 12:11, Marc Zyngier wrote: >>> On Fri, 02 Mar 2018 10:44:48 +, >>> Auger Eric wrote: I understand the get/set is called as part of the