On Tue, 2015-03-03 at 11:06 +0100, Baptiste Reynal wrote:
> Added Eric Auger for comments.
>
> On Mon, Mar 2, 2015 at 5:59 PM, Baptiste Reynal <
> b.rey...@virtualopensystems.com> wrote:
>
> > This patch series aims to implement VFIO support for platform devices that
> > reside behind an IOMMU. E
On 16 March 2015 at 18:01, Jan Kiszka wrote:
> Can't comment if it's known but, from x86 experiences, such a pattern is
> usually related to inconsistency between "get kvm state" and "put kvm
> state" in QEMU or the related kernel interfaces:
>
> QEMU obtains the in-kernel CPU state when you issue
On 2015-03-16 15:35, Diana Craciun wrote:
> Hi,
>
> I have played the last couple of days with info CPUs command in qemu and
> discovered two issues with it:
>
> 1. One core is displayed as halted, but the core is actually running ok.
>
> (qemu) info cpus
> * CPU #0: thread_id=400
> CPU #1: (h
On 16 March 2015 at 15:28, Christoffer Dall wrote:
> On Fri, Mar 06, 2015 at 03:34:39PM +0100, Ard Biesheuvel wrote:
>> The page size and the number of translation levels, and hence the supported
>> virtual address range, are build-time configurables on arm64 whose optimal
>> values are use case d
Hi,
I have played the last couple of days with info CPUs command in qemu and
discovered two issues with it:
1. One core is displayed as halted, but the core is actually running ok.
(qemu) info cpus
* CPU #0: thread_id=400
CPU #1: (halted) thread_id=401
Looking a little bit into the qemu co
On Fri, Mar 06, 2015 at 03:34:39PM +0100, Ard Biesheuvel wrote:
> The page size and the number of translation levels, and hence the supported
> virtual address range, are build-time configurables on arm64 whose optimal
> values are use case dependent. However, in the current implementation, if
> th
There is an interesting bug in the vgic code, which manifests itself
when the KVM run loop has a signal pending or needs a vmid generation
rollover after having disabled interrupts but before actually switching
to the guest.
In this case, we flush the vgic as usual, but we sync back the vgic
state
From: Wei Yongjun
Add the missing unlock before return from function kvm_vgic_create()
in the error handling case.
Signed-off-by: Wei Yongjun
Signed-off-by: Christoffer Dall
---
virt/kvm/arm/vgic.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/virt/kvm/arm/vgic.c b
From: Marc Zyngier
We're using __get_free_pages with to allocate the guest's stage-2
PGD. The standard behaviour of this function is to return a set of
pages where only the head page has a valid refcount.
This behaviour gets us into trouble when we're trying to increment
the refcount on a non-he
Hi Marcelo and Paolo,
Please pull the following fixes for KVM/ARM for 4.0-rc5.
They fix page refcounting issues in our Stage-2 page table management code, a
missing unlock in a gicv3 error path, and a race that can cause lost interrupts
if signals are pending just prior to entering the guest.
Th
From: Marc Zyngier
The kernel's pgd_index macro is designed to index a normal, page
sized array. KVM is a bit diffferent, as we can use concatenated
pages to have a bigger address space (for example 40bit IPA with
4kB pages gives us an 8kB PGD.
In the above case, the use of pgd_index will always
From: Marc Zyngier
Commit 87366d8cf7b3 ("arm64: Add boot time configuration of
Intermediate Physical Address size") removed the hardcoded setting
of VTCR_EL2.PS to use ID_AA64MMFR0_EL1.PARange instead, but didn't
remove the (now rather misleading) comment.
Fix the comments to match reality (at l
On Mon, Mar 16, 2015 at 11:01:55AM +, Alex Bennée wrote:
> From: Christoffer Dall
>
> The current code was negatively indexing the cpu state array and not
> synchronizing banked spsr register state with the current mode's spsr
> state, causing occasional failures with migration.
>
> Some mun
On Mon, Mar 16, 2015 at 11:01:53AM +, Alex Bennée wrote:
> As there is logic to deal with the difference between edge and level
> triggered interrupts in the kernel we must ensure it knows the
> configuration of the IRQs before we restore the pending state.
>
> Signed-off-by: Alex Bennée
> Ac
From: Christoffer Dall
The current code was negatively indexing the cpu state array and not
synchronizing banked spsr register state with the current mode's spsr
state, causing occasional failures with migration.
Some munging is done to take care of the aarch64 mapping and also to
ensure the mos
This adds the saving and restore of the current Multi-Processing state
of the machine. While the KVM_GET/SET_MP_STATE API exposes a number of
potential states for x86 we only use two for ARM. Either the process is
running or not. We then save this state into the cpu_powered TCG state
to avoid chang
This is hopefully the final update to the series. I've skipped v3 for
the purposes of having a sane relationship to the branch name ;-)
v4
- Dropped the pl011 IRQ fiddling patch
- Save/Restore MP STATE
- moved into kvm.c
- changed MP_STATE to STOPPED
- Sync FP State
- Removed sup
For migration to work we need to sync all of the register state. This is
especially noticeable when GCC starts using FP registers as spill
registers even with integer programs.
Signed-off-by: Alex Bennée
---
v4:
- fixed merge conflicts
- rm superfluous reg.id++
diff --git a/target-arm/kvm6
I was getting very confused about the duplication of state so wanted to
make it explicit.
Signed-off-by: Alex Bennée
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 083211c..6dc1799 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -155,6 +155,11 @@ typedef struct CPUARMState {
As there is logic to deal with the difference between edge and level
triggered interrupts in the kernel we must ensure it knows the
configuration of the IRQs before we restore the pending state.
Signed-off-by: Alex Bennée
Acked-by: Christoffer Dall
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/a
On VM entry, we disable access to the VFP registers in order to
perform a lazy save/restore of these registers.
On VM exit, we restore access, test if we did enable them before,
and save/restore the guest/host registers if necessary. In this
sequence, the FPEXC register is always accessed, irrespe
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