On Tue, Jul 07, 2015 at 05:30:00PM +0100, Alex Bennée wrote:
This introduces a level of indirection for the debug registers. Instead
of using the sys_regs[] directly we store registers in a structure in
the vcpu. The new kvm_arm_reset_debug_ptr() sets the debug ptr to the
guest context.
Hi, Will,
Are you happy with this?:
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
+bool hw_breakpoint_enabled(void)
+{
+struct perf_event **slots;
+int i;
+
+slots = this_cpu_ptr(bp_on_reg);
+for (i = 0; i core_num_brps; i++) {
+if
On Tue, Jul 07, 2015 at 05:30:03PM +0100, Alex Bennée wrote:
This includes trace points for:
kvm_arch_setup_guest_debug
kvm_arch_clear_guest_debug
I've also added some generic register setting trace events and also a
trace point to dump the array of hardware registers.
Signed-off-by:
ARMv8.1 comes with the Virtualization Host Extension (VHE for
short), which enables simpler support of Type-2 hypervisors.
This extension allows the kernel to directly run at EL2, and
significantly reduces the number of system registers shared between
host and guest, reducing the overhead of
With the ARMv8.1 VHE, the kernel can run in HYP mode, and thus
use the HYP timer instead of the normal guest timer in a mostly
transparent way, except for the interrupt line.
This patch reworks the arch timer code to allow the selection of
the HYP PPI, possibly falling back to the guest timer if
Add a new ARM64_HAS_VIRT_HOST_EXTN features to indicate that the
CPU has the ARMv8,1 VHE capability.
This will be used to trigger kernel patching in KVM.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/include/asm/cpufeature.h | 3 ++-
arch/arm64/kernel/cpufeature.c | 11
Running the kernel in HYP mode requires the HCR_E2H bit to be set
at all times, and the HCR_TGE bit to be set when running as a host
(and cleared when running as a guest).
Also add some cryptic macros to deal with cpp macro expansion inside
asm macros...
Signed-off-by: Marc Zyngier
With ARMv8.1 VHE extension, it will be possible to run the kernel
at EL2 (aka HYP mode). In order for the kernel to easily find out
where it is running, add a new predicate that returns whether or
not the kernel is in HYP mode.
For completeness, the 32bit code also get such a predicate (always
On 8 July 2015 at 16:56, Marc Zyngier marc.zyng...@arm.com wrote:
On 29/06/15 18:37, Peter Maydell wrote:
On 29 June 2015 at 18:20, Claudio Fontana claudio.font...@huawei.com wrote:
On 26.06.2015 06:49, Jan Kiszka wrote:
QEMU has the concept of write-back levels: KVM_PUT_RUNTIME_STATE,
With the ARMv8.1 VHE, the architecture is able to (almost) transparently
run the kernel at EL2, despite being written for EL1.
This patch takes care of the almost part, mostly preventing the kernel
from dropping from EL2 to EL1, and setting up the HYP configuration.
Signed-off-by: Marc Zyngier
With VHE, the host never issues an HVC instruction to get into the
KVM code, as we can simply branch there.
Use runtime code patching to simplify things a bit.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/kvm/hyp.S| 43 ---
Having both VHE and non-VHE capable CPUs in the same system
is likely to be a recipe for disaster.
If the boot CPU has VHE, but a secondary is not, we won't be
able to downgrade and run the kernel at EL1. Add CPU hotplug
to the mix, and this produces a terrifying mess.
Let's solve the problem
The kern_hyp_va macro is pretty meaninless with VHE, as there is
only one mapping - the kernel one.
In order to keep the code readable and efficient, use runtime
patching to replace the 'and' instruction used to compute the VA
with a 'nop'.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
With VHE enabled, it is possible to let the kernel handle an interrupt
without saving the full guest context, and without restoring the full
host context either. This reduces the latency of handling an interrupt.
When an interrupt fires we can:
- save the guest's general purpose registers, shared
On 08/07/15 17:06, Peter Maydell wrote:
On 8 July 2015 at 16:56, Marc Zyngier marc.zyng...@arm.com wrote:
On 29/06/15 18:37, Peter Maydell wrote:
On 29 June 2015 at 18:20, Claudio Fontana claudio.font...@huawei.com
wrote:
On 26.06.2015 06:49, Jan Kiszka wrote:
QEMU has the concept of
On Wed, Jul 08, 2015 at 11:50:22AM +0100, Zhichao Huang wrote:
Are you happy with this?:
You miss the reserved breakpoint, I think.
I also still don't understand why this is preferable to trapping.
Will
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On 08/07/2015 18:19, Marc Zyngier wrote:
+/* Hack to allow stringification of macros... */
+#define __S__(a,args...) __stringify(a, ##args)
+#define _S_(a,args...) __S__(a, args)
+
+.macro ifnvhe nonvhe vhe
+ alternative_insn\nonvhe, \vhe,
On Mon, Jul 06, 2015 at 03:17:31AM +0100, shannon.z...@linaro.org wrote:
From: Shannon Zhao shannon.z...@linaro.org
To use the ARMv8 PMU related register defines from the KVM code,
we move the relevant definitions to asm/pmu.h header file.
Signed-off-by: Anup Patel anup.pa...@linaro.org
As we're about to cram more information in the vgic_lr structure
(HW interrupt number and additional state information), we switch
to a layout similar to the HW's:
- use bitfields to save space (we don't need more than 10 bits
to represent the irq numbers)
- source CPU and HW interrupt can
As we're about to introduce some serious GIC-poking to the vgic code,
it is important to make sure that we're going to poke the part of
the GIC that belongs to the CPU we're about to run on (otherwise,
we'd end up with some unexpected interrupts firing)...
Introducing a non-preemptible section in
Now that struct vgic_lr supports the LR_HW bit and carries a hwirq
field, we can encode that information into the list registers.
This patch provides implementations for both GICv2 and GICv3.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
include/linux/irqchip/arm-gic-v3.h | 3 +++
On 08/07/15 18:14, Paolo Bonzini wrote:
On 08/07/2015 18:19, Marc Zyngier wrote:
+/* Hack to allow stringification of macros... */
+#define __S__(a,args...)__stringify(a, ##args)
+#define _S_(a,args...) __S__(a, args)
+
+.macro ifnvhe nonvhe vhe
+alternative_insn
As we now inject the timer interrupt when we're about to enter
the guest, it makes a lot more sense to make sure this happens
before the vgic code queues the pending interrupts.
Otherwise, we get the interrupt on the following exit, which is
not great for latency (and leads to all kind of bizarre
In order to remove the crude hack where we sneak the masked bit
into the timer's control register, make use of the phys_irq_map
API control the active state of the interrupt.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
include/kvm/arm_arch_timer.h | 3 +++
virt/kvm/arm/arch_timer.c
We only set the irq_queued flag for level interrupts, meaning
that !vgic_irq_is_queued(vcpu, irq) is a good enough predicate
for all interrupts.
This will allow us to inject edge HW interrupts, for which the
state ACTIVE+PENDING is not allowed.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
On 07/08/2015 09:19 AM, Marc Zyngier wrote:
In order to switch between host and guest, a VHE-enabled kernel
must use different accessors for certain system registers.
This patch uses runtime patching to use the right instruction
when required...
Signed-off-by: Marc Zyngier
On 8 July 2015 at 17:37, Marc Zyngier marc.zyng...@arm.com wrote:
On 08/07/15 17:06, Peter Maydell wrote:
I'd prefer it if somebody could investigate to see why QEMU
is actually doing this -- so far we just have speculation.
I'd prefer that too, but so far people seem to be more comfortable
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