Will Deacon writes:
> On Fri, Aug 26, 2016 at 10:37:08AM +0100, Punit Agrawal wrote:
>> > Will Deacon writes:
>> >> The easiest thing to do is just TLBI VMALLE1IS for all trapped operations,
>> >> but you might want to see how that performs.
>> >
>> >
Hi Drew,
On 15/07/2016 15:00, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
> ---
> v2: add more details in the output if a test fails,
> report spurious interrupts if we get them
> ---
> arm/Makefile.common | 6 +-
> arm/gic.c | 194
>
Hi Drew,
On 15/07/2016 15:00, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
>
> ---
> v2: use IRM for gicv3 broadcast
> ---
> arm/gic.c | 157
> ++
> arm/unittests.cfg | 6 +++
> 2 files changed, 154
On 30/08/2016 19:59, Bhaktipriya Shridhar wrote:
> The workqueue "irqfd_cleanup_wq" queues a single work item
> >shutdown and hence doesn't require ordering. It is a host-wide
> workqueue for issuing deferred shutdown requests aggregated from all
> vm* instances. It is not being used on a memory
On 01/09/16 15:29, Vladimir Murzin wrote:
> SCTLR_EL2.SPAN bit controls what happens with the PSTATE.PAN bit on an
> exception. However, this bit has no effect on the PSTATE.PAN when
> HCR_EL2.E2H or HCR_EL2.TGE is unset. Thus when VHE is used and
> exception taken from a guest PSTATE.PAN bit left
On Fri, Aug 26, 2016 at 10:37:08AM +0100, Punit Agrawal wrote:
> > Will Deacon writes:
> >> The easiest thing to do is just TLBI VMALLE1IS for all trapped operations,
> >> but you might want to see how that performs.
> >
> > That sounds reasonable for correctness. But I
On Thu, Sep 01, 2016 at 03:28:36PM +0100, Marc Zyngier wrote:
> On 01/09/16 13:46, Christoffer Dall wrote:
> > On Fri, Aug 19, 2016 at 01:38:13PM +0100, Marc Zyngier wrote:
> >> In order to efficiently perform the GICV access on behalf of the
> >> guest, we need to be able to do avoid going back
On 1 September 2016 at 15:28, Marc Zyngier wrote:
> On 01/09/16 13:46, Christoffer Dall wrote:
>> On Fri, Aug 19, 2016 at 01:38:13PM +0100, Marc Zyngier wrote:
>>> +__skip_instr(vcpu);
>>
>> does this interact in any amusing way with single-step guest
SCTLR_EL2.SPAN bit controls what happens with the PSTATE.PAN bit on an
exception. However, this bit has no effect on the PSTATE.PAN when
HCR_EL2.E2H or HCR_EL2.TGE is unset. Thus when VHE is used and
exception taken from a guest PSTATE.PAN bit left unchanged and we
continue with a value guest has
On 01/09/16 13:46, Christoffer Dall wrote:
> On Fri, Aug 19, 2016 at 01:38:13PM +0100, Marc Zyngier wrote:
>> In order to efficiently perform the GICV access on behalf of the
>> guest, we need to be able to do avoid going back all the way to
>
> s/do//
>
>> the host kernel.
>>
>> For this, we
On Tue, Aug 30, 2016 at 07:00:20PM +0100, Mark Rutland wrote:
> On Tue, Aug 30, 2016 at 05:05:54PM +0100, Mark Rutland wrote:
> > As noted in a jailhouse thread a short while ago [1,2], the presence of the
> > virtualization extensions implies that page table walks are coherent, and do
> > not
Hi Drew,
On 15/07/2016 15:00, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
>
> ---
> v2: configure irqs as NS GRP1
> ---
> lib/arm/asm/arch_gicv3.h | 184 ++
> lib/arm/asm/gic-v3.h | 321
> +
>
Hi,
On 15/07/2016 15:00, Andrew Jones wrote:
> Reviewed-by: Alex Bennée
> Signed-off-by: Andrew Jones
> ---
> lib/arm/asm/processor.h | 10 ++
> lib/arm64/asm/processor.h | 10 ++
> 2 files changed, 20 insertions(+)
>
> diff --git
Hi Drew,
On 15/07/2016 15:00, Andrew Jones wrote:
> Allow a thread to wait some specified amount of time. Can
> specify in cycles, usecs, and msecs.
>
> Reviewed-by: Alex Bennée
> Signed-off-by: Andrew Jones
> ---
> lib/arm/asm/processor.h | 19
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