Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

Hi Mark, On 01/30/2017 05:56 AM, Mark Rutland wrote: > Hi, > > On Fri, Jan 27, 2017 at 04:52:23PM -0500, Christopher Covington wrote: >> On 01/27/2017 09:38 AM, Mark Rutland wrote: >>> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: > Replacing the above sequence

Re: [RFC v2 00/10] Provide the EL1 physical timer to the VM

Hi Marc, On Sun, Jan 29, 2017 at 10:55 AM, Marc Zyngier wrote: > Hi Jintack, > > On Fri, Jan 27 2017 at 01:04:50 AM, Jintack Lim > wrote: >> The ARM architecture defines the EL1 physical timer and the virtual timer, >> and it is reasonable for an

Re: [RFC v2 06/10] KVM: arm/arm64: Update the physical timer interrupt level

On Mon, Jan 30, 2017 at 06:48:02PM +, Marc Zyngier wrote: > On 30/01/17 18:41, Christoffer Dall wrote: > > On Mon, Jan 30, 2017 at 05:50:03PM +, Marc Zyngier wrote: > >> On 30/01/17 15:02, Christoffer Dall wrote: > >>> On Sun, Jan 29, 2017 at 03:21:06PM +, Marc Zyngier wrote: > On

Re: [RFC v2 05/10] KVM: arm/arm64: Initialize the emulated EL1 physical timer

On Mon, Jan 30, 2017 at 05:44:20PM +, Marc Zyngier wrote: > On 30/01/17 14:58, Christoffer Dall wrote: > > On Sun, Jan 29, 2017 at 12:07:48PM +, Marc Zyngier wrote: > >> On Fri, Jan 27 2017 at 01:04:55 AM, Jintack Lim > >> wrote: > >>> Initialize the emulated EL1

Re: [RFC v2 06/10] KVM: arm/arm64: Update the physical timer interrupt level

On 30/01/17 18:41, Christoffer Dall wrote: > On Mon, Jan 30, 2017 at 05:50:03PM +, Marc Zyngier wrote: >> On 30/01/17 15:02, Christoffer Dall wrote: >>> On Sun, Jan 29, 2017 at 03:21:06PM +, Marc Zyngier wrote: On Fri, Jan 27 2017 at 01:04:56 AM, Jintack Lim

Re: [RFC v2 02/10] KVM: arm/arm64: Move cntvoff to each timer context

On Mon, Jan 30, 2017 at 1:05 PM, Marc Zyngier wrote: > On 30/01/17 17:58, Jintack Lim wrote: >> On Sun, Jan 29, 2017 at 6:54 AM, Marc Zyngier wrote: >>> On Fri, Jan 27 2017 at 01:04:52 AM, Jintack Lim >>> wrote: Make

Re: [RFC v2 06/10] KVM: arm/arm64: Update the physical timer interrupt level

On Mon, Jan 30, 2017 at 05:50:03PM +, Marc Zyngier wrote: > On 30/01/17 15:02, Christoffer Dall wrote: > > On Sun, Jan 29, 2017 at 03:21:06PM +, Marc Zyngier wrote: > >> On Fri, Jan 27 2017 at 01:04:56 AM, Jintack Lim > >> wrote: > >>> Now that we maintain the

Re: [RFC v2 02/10] KVM: arm/arm64: Move cntvoff to each timer context

On Sun, Jan 29, 2017 at 6:54 AM, Marc Zyngier wrote: > On Fri, Jan 27 2017 at 01:04:52 AM, Jintack Lim > wrote: >> Make cntvoff per each timer context. This is helpful to abstract kvm >> timer functions to work with timer context without

Re: [RFC v2 06/10] KVM: arm/arm64: Update the physical timer interrupt level

On 30/01/17 15:02, Christoffer Dall wrote: > On Sun, Jan 29, 2017 at 03:21:06PM +, Marc Zyngier wrote: >> On Fri, Jan 27 2017 at 01:04:56 AM, Jintack Lim >> wrote: >>> Now that we maintain the EL1 physical timer register states of VMs, >>> update the physical timer

Re: [RFC v2 05/10] KVM: arm/arm64: Initialize the emulated EL1 physical timer

On 30/01/17 14:58, Christoffer Dall wrote: > On Sun, Jan 29, 2017 at 12:07:48PM +, Marc Zyngier wrote: >> On Fri, Jan 27 2017 at 01:04:55 AM, Jintack Lim >> wrote: >>> Initialize the emulated EL1 physical timer with the default irq number. >>> >>> Signed-off-by:

Re: [RFC v2 02/10] KVM: arm/arm64: Move cntvoff to each timer context

On Mon, Jan 30, 2017 at 9:51 AM, Marc Zyngier wrote: > On 30/01/17 14:45, Christoffer Dall wrote: >> On Sun, Jan 29, 2017 at 11:54:05AM +, Marc Zyngier wrote: >>> On Fri, Jan 27 2017 at 01:04:52 AM, Jintack Lim >>> wrote: Make cntvoff per

Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

Hi Peter, On Mon, Jan 30, 2017 at 12:26 PM, Peter Maydell wrote: > On 30 January 2017 at 17:08, Jintack Lim wrote: >> On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier wrote: >>> Shouldn't we take the ENABLE bit into

Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

On 30/01/17 17:26, Peter Maydell wrote: > On 30 January 2017 at 17:08, Jintack Lim wrote: >> On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier wrote: >>> Shouldn't we take the ENABLE bit into account? The ARMv8 ARM version I >>> have at hand (version

Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

On 30 January 2017 at 17:08, Jintack Lim wrote: > On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier wrote: >> Shouldn't we take the ENABLE bit into account? The ARMv8 ARM version I >> have at hand (version h) seems to indicate that we should, but we

Re: [PATCH v2 1/3] arm64: cacheinfo: add support for alternative format of CCSIDR_EL1

On 30/01/17 16:57, Sudeep Holla wrote: Could this be static ? I could not see it used anywhere else outside this file. Used in arch/arm64/kernel/cpuinfo.c Ah, you're right. Suzuki ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu

Re: [RFC v2 03/10] KVM: arm/arm64: Decouple kvm timer functions from virtual timer

Hi Christoffer, On Mon, Jan 30, 2017 at 9:49 AM, Christoffer Dall wrote: > On Thu, Jan 26, 2017 at 08:04:53PM -0500, Jintack Lim wrote: >> Now that we have a separate structure for timer context, make functions >> general so that they can work with any timer context,

Re: [RFC v2 03/10] KVM: arm/arm64: Decouple kvm timer functions from virtual timer

On Sun, Jan 29, 2017 at 7:01 AM, Marc Zyngier wrote: > On Fri, Jan 27 2017 at 01:04:53 AM, Jintack Lim > wrote: >> Now that we have a separate structure for timer context, make functions >> general so that they can work with any timer context, not

Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

Hi Marc, On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier wrote: > On Fri, Jan 27 2017 at 01:05:00 AM, Jintack Lim > wrote: >> Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL. >> Now VMs are able to use the EL1 physical timer.

Re: [PATCH v2 1/3] arm64: cacheinfo: add support for alternative format of CCSIDR_EL1

On 30/01/17 16:47, Suzuki K Poulose wrote: > On 30/01/17 16:25, Sudeep Holla wrote: >> The number of sets described for each cache level in the CCSIDR is >> limited to 32K and the associativity is limited to 1024 ways. >> >> As part of the ARM8.3 extensions, an alternative format for the >>

Re: [PATCH v2 1/3] arm64: cacheinfo: add support for alternative format of CCSIDR_EL1

On 30/01/17 16:25, Sudeep Holla wrote: The number of sets described for each cache level in the CCSIDR is limited to 32K and the associativity is limited to 1024 ways. As part of the ARM8.3 extensions, an alternative format for the CCSIDR_EL1 is introduced for AArch64, and for AArch32, a new

[PATCH v2 3/3] arm64: kvm: add support for the extended 64bit ccsidr

csselr and ccsidr are treated as 64-bit values already elsewhere in the kernel. It also aligns well with the architecture extensions that allow 64-bit format for ccsidr. This patch upgrades the existing accesses to csselr and ccsidr from 32-bit to 64-bit in preparation to add support to those

[PATCH v2 1/3] arm64: cacheinfo: add support for alternative format of CCSIDR_EL1

The number of sets described for each cache level in the CCSIDR is limited to 32K and the associativity is limited to 1024 ways. As part of the ARM8.3 extensions, an alternative format for the CCSIDR_EL1 is introduced for AArch64, and for AArch32, a new CCSIDR2 register is introduced to hold the

[PATCH v2 2/3] arm64: kvm: reuse existing cache type/info related macros

We already have various macros related to cache type and bitfields in CLIDR system register. We can replace some of the hardcoded values here using those existing macros. This patch reuses those existing cache type/info related macros and replaces the hardcorded values. It also removes some of

Re: [RFC 01/13] KVM: arm/arm64: Add vITS save/restore API documentation

Hi Marc, On 13/01/2017 10:46, Marc Zyngier wrote: > On 13/01/17 09:07, Auger Eric wrote: >> Hi Marc, >> >> On 12/01/2017 17:52, Marc Zyngier wrote: >>> Hi Eric, >>> >>> On 12/01/17 15:56, Eric Auger wrote: Add description for how to access vITS registers and how to flush/restore vITS

Re: [RFC v2 06/10] KVM: arm/arm64: Update the physical timer interrupt level

On Sun, Jan 29, 2017 at 03:21:06PM +, Marc Zyngier wrote: > On Fri, Jan 27 2017 at 01:04:56 AM, Jintack Lim > wrote: > > Now that we maintain the EL1 physical timer register states of VMs, > > update the physical timer interrupt level along with the virtual one. > >

Re: [RFC v2 05/10] KVM: arm/arm64: Initialize the emulated EL1 physical timer

On Sun, Jan 29, 2017 at 12:07:48PM +, Marc Zyngier wrote: > On Fri, Jan 27 2017 at 01:04:55 AM, Jintack Lim > wrote: > > Initialize the emulated EL1 physical timer with the default irq number. > > > > Signed-off-by: Jintack Lim > > --- > >

Re: [RFC v2 03/10] KVM: arm/arm64: Decouple kvm timer functions from virtual timer

On Thu, Jan 26, 2017 at 08:04:53PM -0500, Jintack Lim wrote: > Now that we have a separate structure for timer context, make functions > general so that they can work with any timer context, not just the > virtual timer context. This does not change the virtual timer > functionality. > >

Re: [RFC v2 02/10] KVM: arm/arm64: Move cntvoff to each timer context

On 30/01/17 14:45, Christoffer Dall wrote: > On Sun, Jan 29, 2017 at 11:54:05AM +, Marc Zyngier wrote: >> On Fri, Jan 27 2017 at 01:04:52 AM, Jintack Lim >> wrote: >>> Make cntvoff per each timer context. This is helpful to abstract kvm >>> timer functions to work

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

Hi, On Fri, Jan 27, 2017 at 04:52:23PM -0500, Christopher Covington wrote: > On 01/27/2017 09:38 AM, Mark Rutland wrote: > > On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: > >> Replacing the above sequence with the one below will ensure that no TLB > >> entries with an