Re: [PATCH v3 0/4] kvm: arm/arm64: vgic: APRn uaccess support.

On 2017/9/1 4:33, Christoffer Dall wrote: > Hi Wanghaibin, > > On Wed, Aug 23, 2017 at 09:05:22AM +0800, wanghaibin wrote: >> v3: Coding style fix. >> Add the valid APRn access check which Marc proposed. >> >> v2: Split the patch again to make it easier for review >> some fixes were

Re: [PATCH v3 0/4] kvm: arm/arm64: vgic: APRn uaccess support.

Hi Wanghaibin, On Wed, Aug 23, 2017 at 09:05:22AM +0800, wanghaibin wrote: > v3: Coding style fix. > Add the valid APRn access check which Marc proposed. > > v2: Split the patch again to make it easier for review > some fixes were proposed by Marc Usually we put the changelog at the

Re: [PATCH v6 3/7] acpi: apei: remove the unused code

Hi Dongjiu Geng, On 28/08/17 11:38, Dongjiu Geng wrote: > In current code logic, the two functions ghes_sea_add() and > ghes_sea_remove() are only called when CONFIG_ACPI_APEI_SEA > is defined. If not, it will return errors in the ghes_probe() > and not contiue. Hence, remove the unnecessary

Re: [PATCH v6 1/7] arm64: cpufeature: Detect CPU RAS Extentions

Hi Dongjiu Geng, On 28/08/17 11:38, Dongjiu Geng wrote: > From: Xie XiuQi > > ARM's v8.2 Extentions add support for Reliability, Availability and > Serviceability (RAS). On CPUs with these extensions system software > can use additional barriers to isolate errors and

Re: [PATCH v6 0/7] Add RAS virtualization support for SEA/SEI notification type in KVM

Hi Dongjiu Geng, On 28/08/17 11:38, Dongjiu Geng wrote: > In the firmware-first RAS solution, corrupt data is detected in a > memory location when guest OS application software executing at EL0 > or guest OS kernel El1 software are reading from the memory. The > memory node records errors in an

[PATCH v2 07/28] arm64/sve: Low-level SVE architectural state manipulation functions

Manipulating the SVE architectural state, including the vector and predicate registers, first-fault register and the vector length, requires the use of dedicated instructions added by SVE. This patch adds suitable assembly functions for saving and restoring the SVE registers and querying the

[RFC PATCH v2 27/28] arm64: signal: Report signal frame size to userspace via auxv

Stateful CPU architecture extensions may require the signal frame to grow to a size that exceeds the arch's MINSIGSTKSZ #define. However, changing this #define is an ABI break. To allow userspace the option of determining the signal frame size in a more forwards-compatible way, this patch adds a

[PATCH v2 26/28] arm64/sve: Add documentation

This patch adds basic documentation of the user/kernel interface provided by the for SVE. Signed-off-by: Dave Martin Cc: Alex Bennée Cc: Mark Rutland --- Changes since v1 Requested by Alex Bennée: * Add

[PATCH v2 23/28] arm64/sve: KVM: Treat guest SVE use as undefined instruction execution

When trapping forbidden attempts by a guest to use SVE, we want the guest to see a trap consistent with SVE not being implemented. This patch injects an undefined instruction exception into the guest in response to such an exception. Signed-off-by: Dave Martin ---

[RFC PATCH v2 28/28] arm64/sve: signal: Include SVE when computing AT_MINSIGSTKSZ

The SVE context block in the signal frame needs to be considered too when computing the maximum possible signal frame size. Because the size of this block depends on the vector length, this patch computes the size based not on the thread's current vector length but instead on the maximum possible

[PATCH v2 20/28] arm64/sve: Add prctl controls for userspace vector length management

This patch adds two arm64-specific prctls, to permit userspace to control its vector length: * PR_SVE_SET_VL: set the thread's SVE vector length and vector length inheritance mode. * PR_SVE_GET_VL: get the same information. Although these calls shadow instruction set features in the SVE

[PATCH v2 24/28] arm64/sve: KVM: Hide SVE from CPU features exposed to guests

KVM guests cannot currently use SVE, because SVE is always configured to trap to EL2. However, a guest that sees SVE reported as present in ID_AA64PFR0_EL1 may legitimately expect that SVE works and try to use it. Instead of working, the guest will receive an injected undef exception, which may

[PATCH v2 21/28] arm64/sve: Add sysctl to set the default vector length for new processes

Because of the effect of SVE on the size of the signal frame, the default vector length used for new processes involves a tradeoff between performance of SVE-enabled software on the one hand, and reliability of non-SVE-aware software on the other hand. For this reason, the best choice depends on

[PATCH v2 16/28] arm64/sve: Probe SVE capabilities and usable vector lengths

This patch uses the cpufeatures framework to determine common SVE capabilities and vector lengths, and configures the runtime SVE support code appropriately. ZCR_ELx is not really a feature register, but it is convenient to use it as a template for recording the maximum vector length supported by

[PATCH v2 25/28] arm64/sve: Detect SVE and activate runtime support

This patch enables detection of hardware SVE support via the cpufeatures framework, and reports its presence to the kernel and userspace via the new ARM64_SVE cpucap and HWCAP_SVE hwcap respectively. Userspace can also detect SVE using ID_AA64PFR0_EL1, using the cpufeatures MRS emulation. When

[PATCH v2 22/28] arm64/sve: KVM: Prevent guests from using SVE

Until KVM has full SVE support, guests must not be allowed to execute SVE instructions. This patch enables the necessary traps, and also ensures that the traps are disabled again on exit from the guest so that the host can still use SVE if it wants to. This patch introduces another instance of

[PATCH v2 18/28] arm64/sve: Preserve SVE registers around EFI runtime service calls

The EFI runtime services ABI allows EFI to make free use of the FPSIMD registers during EFI runtime service calls, subject to the callee-save requirements of the AArch64 procedure call standard. However, the SVE architecture allows upper bits of the SVE vector registers to be zeroed as a

[PATCH v2 19/28] arm64/sve: ptrace and ELF coredump support

This patch defines and implements a new regset NT_ARM_SVE, which describes a thread's SVE register state. This allows a debugger to manipulate the SVE state, as well as being included in ELF coredumps for post-mortem debugging. Because the regset size and layout are dependent on the thread's

[PATCH v2 17/28] arm64/sve: Preserve SVE registers around kernel-mode NEON use

Kernel-mode NEON will corrupt the SVE vector registers, due to the way they alias the FPSIMD vector registers in the hardware. This patch ensures that any live SVE register content for the task is saved by kernel_neon_begin(). The data will be restored in the usual way on return to userspace.

[PATCH v2 12/28] arm64/sve: Support vector length resetting for new processes

It's desirable to be able to reset the vector length to some sane default for new processes, since the new binary and its libraries processes may or may not be SVE-aware. This patch tracks the desired post-exec vector length (if any) in a new thread member sve_vl_onexec, and adds a new thread

[PATCH v2 13/28] arm64/sve: Signal handling support

This patch implements support for saving and restoring the SVE registers around signals. A fixed-size header struct sve_context is always included in the signal frame encoding the thread's vector length at the time of signal delivery, optionally followed by a variable-layout structure encoding

[PATCH v2 14/28] arm64/sve: Backend logic for setting the vector length

This patch implements the core logic for changing a task's vector length on request from userspace. This will be used by the ptrace and prctl frontends that are implemented in later patches. The SVE architecture permits, but does not require, implementations to support vector lengths that are

[PATCH v2 11/28] arm64/sve: Core task context handling

This patch adds the core support for switching and managing the SVE architectural state of user tasks. Calls to the existing FPSIMD low-level save/restore functions are factored out as new functions task_fpsimd_{save,load}(), since SVE now dynamically may or may not need to be handled at these

[PATCH v2 09/28] arm64/sve: Signal frame and context structure definition

This patch defines the representation that will be used for the SVE register state in the signal frame, and implements support for saving and restoring the SVE registers around signals. The same layout will also be used for the in-kernel task state. Due to the variability of the SVE vector

[PATCH v2 08/28] arm64/sve: Kconfig update and conditional compilation support

This patch adds CONFIG_ARM64_SVE to control building of SVE support into the kernel, and adds a stub predicate system_supports_sve() to control conditional compilation and runtime SVE support. system_supports_sve() just returns false for now: it will be replaced with a non-trivial implementation

[PATCH v2 10/28] arm64/sve: Low-level CPU setup

To enable the kernel to use SVE, all SVE traps from EL1 must be disabled. To take maximum advantage of the hardware, the full available vector length also needs to be enabled for EL1 by programming ZCR_EL2.LEN. (The kernel will program ZCR_EL1.LEN as required, but this cannot override the limit

[PATCH v2 03/28] arm64: efi: Add missing Kconfig dependency on KERNEL_MODE_NEON

The EFI runtime services ABI permits calls to EFI to clobber certain FPSIMD/NEON registers, as per the AArch64 procedure call standard. Saving/restoring the clobbered registers around such calls needs KERNEL_MODE_NEON, but the dependency is missing from Kconfig. This patch adds the missing

[PATCH v2 06/28] arm64/sve: System register and exception syndrome definitions

The SVE architecture adds some system registers, ID register fields and a dedicated ESR exception class. This patch adds the appropriate definitions that will be needed by the kernel. Signed-off-by: Dave Martin Cc: Alex Bennée --- Changes since v1

[PATCH v2 05/28] arm64: fpsimd: Simplify uses of {set, clear}_ti_thread_flag()

The existing FPSIMD context switch code contains a couple of instances of {set,clear}_ti_thread(task_thread_info(task)). Since there are thread flag manipulators that operate directly on task_struct, this verbosity isn't strictly needed. For consistency, this patch simplifies the affected calls.

[PATCH v2 02/28] arm64: KVM: Hide unsupported AArch64 CPU features from guests

Currently, a guest kernel sees the true CPU feature registers (ID_*_EL1) when it reads them using MRS instructions. This means that the guest will observe features that are present in the hardware but the host doesn't understand or doesn't provide support for. A guest may legimitately try to use

[PATCH v2 01/28] regset: Add support for dynamically sized regsets

Currently the regset API doesn't allow for the possibility that regsets (or at least, the amount of meaningful data in a regset) may change in size. In particular, this results in useless padding being added to coredumps in a regset's current size is smaller than its theoretical maximum size.

[PATCH v2 04/28] arm64: Port deprecated instruction emulation to new sysctl interface

Currently, armv8_deprected.c takes charge of the "abi" sysctl directory, which makes life difficult for other code that wants to register sysctls in the same directory. There is a "new" [1] sysctl registration interface that removes the need to define ctl_tables for parent directories explicitly,

Re: [PATCH v3 41/59] KVM: arm/arm64: GICv4: Wire mapping/unmapping of VLPIs in VFIO irq bypass

On Thu, Aug 31, 2017 at 11:24:37AM +0100, Marc Zyngier wrote: > On 30/08/17 20:59, Christoffer Dall wrote: > > On Wed, Aug 30, 2017 at 01:53:30PM +0100, Marc Zyngier wrote: > >> On 30/08/17 12:46, Christoffer Dall wrote: > >>> On Wed, Aug 30, 2017 at 11:28:08AM +0100, Marc Zyngier wrote: > On

Re: [PATCH v3 51/59] KVM: arm/arm64: GICv4: Add doorbell interrupt handling

On 28/08/17 19:18, Christoffer Dall wrote: > On Fri, Aug 04, 2017 at 08:44:04AM +0100, Marc Zyngier wrote: >> On 31/07/17 18:26, Marc Zyngier wrote: >>> When a vPE is not running, a VLPI being made pending results in a >>> doorbell interrupt being delivered. Let's handle this interrupt >>> and

Re: [PATCH v3 41/59] KVM: arm/arm64: GICv4: Wire mapping/unmapping of VLPIs in VFIO irq bypass

On 30/08/17 20:59, Christoffer Dall wrote: > On Wed, Aug 30, 2017 at 01:53:30PM +0100, Marc Zyngier wrote: >> On 30/08/17 12:46, Christoffer Dall wrote: >>> On Wed, Aug 30, 2017 at 11:28:08AM +0100, Marc Zyngier wrote: On 26/08/17 20:48, Christoffer Dall wrote: > On Mon, Jul 31, 2017 at

Re: [RFC 00/11] KVM, EFI, arm64: EFI Runtime Services Sandboxing

Hi Florent, On Fri, Aug 25, 2017 at 09:31:30AM +0100, Florent Revest wrote: > Hi, > > This series implements a mechanism to sandbox EFI Runtime Services on arm64. > It can be enabled with CONFIG_EFI_SANDBOX. At boot it spawns an internal KVM > virtual machine that is ran everytime an EFI Runtime

Re: [RFC 04/11] KVM, arm, arm64: Offer PAs to IPAs idmapping to internal VMs

Hi Florent, I'd like for the UEFI folks and arm64 kernel maintainers to express their views on this overall approach before I do an in-depth review, but I have some random comments based on reading this patch: On Fri, Aug 25, 2017 at 09:31:34AM +0100, Florent Revest wrote: > Usual KVM virtual

Re: [PATCH v3 51/59] KVM: arm/arm64: GICv4: Add doorbell interrupt handling

On 30/08/17 21:58, Christoffer Dall wrote: > On Wed, Aug 30, 2017 at 04:36:06PM +0100, Marc Zyngier wrote: >> On 28/08/17 19:18, Christoffer Dall wrote: >>> On Mon, Jul 31, 2017 at 06:26:29PM +0100, Marc Zyngier wrote: When a vPE is not running, a VLPI being made pending results in a

Re: [PATCH] [stable] kvm: arm/arm64: Fix race in resetting stage2 PGD

On Wed, Aug 30, 2017 at 12:30:52PM +0100, Suzuki K Poulose wrote: > commit 6c0d706b563af732adb094c5bf807437e8963e84 upstream. > > In kvm_free_stage2_pgd() we check the stage2 PGD before holding > the lock and proceed to take the lock if it is valid. And we unmap > the page tables, followed by