Re: [RFC v7 7/7] KVM: arm: enable KVM_SIGNAL_MSI and MSI routing

On 22/07/2016 15:56, Radim Krčmář wrote: > 2016-07-22 15:52+0200, Auger Eric: >> On 22/07/2016 15:39, Radim Krčmář wrote: >>> 2016-07-21 23:10+0200, Auger Eric: >>>> On 21/07/2016 18:33, Radim Krčmář wrote: >>>>> 2016-07-18 13:25+, Eric Auger

Re: [RFC v7 7/7] KVM: arm: enable KVM_SIGNAL_MSI and MSI routing

Hi Radim, On 22/07/2016 15:39, Radim Krčmář wrote: > 2016-07-21 23:10+0200, Auger Eric: >> On 21/07/2016 18:33, Radim Krčmář wrote: >>> 2016-07-18 13:25+, Eric Auger: >>>> If the ITS modality is not available, let's simply support MSI >>>> injection b

Re: [RFC v8 6/7] KVM: arm/arm64: Enable MSI routing

On 22/07/2016 16:14, Radim Krčmář wrote: > 2016-07-22 13:46+, Eric Auger: >> Up to now, only irqchip routing entries could be set. This patch >> adds the capability to insert MSI routing entries. >> >> For ARM64, let's also increase KVM_MAX_IRQ_ROUTES to 4096: this >> include SPI irqchip

Re: [RFC v8 5/7] KVM: arm/arm64: Enable irqchip routing

Hi Radim On 22/07/2016 16:24, Radim Krčmář wrote: > 2016-07-22 13:46+, Eric Auger: >> This patch adds compilation and link against irqchip. >> >> Main motivation behind using irqchip code is to enable MSI >> routing code. In the future irqchip routing may also be useful >> when targeting

Re: KVM on ARM crashes with new VGIC v4.7-rc7

Hi, On 22/07/2016 17:40, Marc Zyngier wrote: > On 22/07/16 15:35, Andrew Jones wrote: >> On Fri, Jul 22, 2016 at 11:42:02AM +0100, Andre Przywara wrote: >>> Hi Stefan, >>> >>> On 22/07/16 06:57, Stefan Agner wrote: Hi, I tried KVM on a Cortex-A7 platform (i.MX 7Dual SoC) and

Re: [PATCH v11 4/8] iommu/msi-iommu: initialization

Hi Dennis, On 20/07/2016 13:43, Dennis Chen wrote: > Hi Eric, > Some small questions/comments below: > > On Tue, Jul 19, 2016 at 12:55:07PM +, Eric Auger wrote: >> iommu_get/put_msi_cookie allocates/frees the resource used to store >> and ref count the MSI doorbell mappings.

Re: [RFC v7 7/7] KVM: arm: enable KVM_SIGNAL_MSI and MSI routing

Hi Radim, On 21/07/2016 18:33, Radim Krčmář wrote: > 2016-07-18 13:25+, Eric Auger: >> If the ITS modality is not available, let's simply support MSI >> injection by transforming the MSI.data into an SPI ID. >> >> This becomes possible to use KVM_SIGNAL_MSI ioctl and MSI >> routing for arm

Re: [RFC v7 1/7] KVM: api: pass the devid in the msi routing entry

Hi, On 21/07/2016 19:15, Radim Krčmář wrote: > 2016-07-21 17:43+0100, Andre Przywara: >> Hi Radim, >> >> On 21/07/16 17:01, Radim Krčmář wrote: >>> 2016-07-18 13:25+, Eric Auger: On ARM, the MSI msg (address and data) comes along with out-of-band device ID information. The device ID

Re: [RFC v7 6/7] KVM: arm/arm64: enable MSI routing

Hi Radim, On 21/07/2016 18:21, Radim Krčmář wrote: > 2016-07-18 13:25+, Eric Auger: >> Up to now, only irqchip routing entries could be set. This patch >> adds the capability to insert MSI routing entries. >> >> For ARM64, let's also increase KVM_MAX_IRQ_ROUTES to 4096: this >> include SPI

Re: [RFC v7 2/7] KVM: kvm_host: add devid in kvm_kernel_irq_routing_entry

Hi, On 21/07/2016 19:25, Marc Zyngier wrote: > On 21/07/16 18:22, Radim Krčmář wrote: >> 2016-07-21 17:54+0100, Marc Zyngier: >>> On 21/07/16 17:13, Radim Krčmář wrote: 2016-07-18 13:25+, Eric Auger: > Extend kvm_kernel_irq_routing_entry to transport the device id > field, devid.

Re: KVM on ARM crashes with new VGIC v4.7-rc7

Hi Marc, On 22/07/2016 09:47, Marc Zyngier wrote: > Hi Stefan, > > On 22/07/16 06:57, Stefan Agner wrote: >> Hi, >> >> I tried KVM on a Cortex-A7 platform (i.MX 7Dual SoC) and encountered >> this stack trace immediately after invoking qemu-system-arm: >> >> Unable to handle kernel paging request

Re: [RFC v9 0/6] KVM: arm/arm64: gsi routing support

Hi Andre, On 29/07/2016 00:31, André Przywara wrote: > Hi, > > On 22/07/16 17:20, Eric Auger wrote: >> With the advent of GICv3 ITS in-kernel emulation, KVM MSI routing >> becomes mandated for proper VIRTIO-PCI vhost integration. >> >> In QEMU, when the VIRTIO-PCI device is programmed with the

Re: [PATCH v11 09/10] genirq/msi: map/unmap the MSI doorbells on msi_domain_alloc/free_irqs

Hi Thomas, On 26/07/2016 11:00, Thomas Gleixner wrote: > B1;2802;0cEric, > > On Mon, 25 Jul 2016, Auger Eric wrote: >> On 20/07/2016 11:04, Thomas Gleixner wrote: >>> On Tue, 19 Jul 2016, Eric Auger wrote: >>>> + if (ret) { >

Re: [PATCH v11 09/10] genirq/msi: map/unmap the MSI doorbells on msi_domain_alloc/free_irqs

Hi Thomas, On 20/07/2016 11:04, Thomas Gleixner wrote: > On Tue, 19 Jul 2016, Eric Auger wrote: >> /** >> + * msi_handle_doorbell_mappings: in case the irq data corresponds to an >> + * MSI that requires iommu mapping, traverse the irq domain hierarchy >> + * to retrieve the doorbells to handle

Re: [PATCH v11 10/10] genirq/msi: use the MSI doorbell's IOVA when requested

Hi Thomas, On 20/07/2016 11:09, Thomas Gleixner wrote: > On Tue, 19 Jul 2016, Eric Auger wrote: > > First of all - valid for all patches: > > Subject: sys/subsys: Sentence starts with an uppercase letter OK understood. > > Now for this particular one: > > genirq/msi: use the MSI doorbell's

Re: [PATCH v11 4/8] vfio/type1: handle unmap/unpin and replay for VFIO_IOVA_RESERVED slots

Hi, On 24/07/2016 03:41, kbuild test robot wrote: > Hi, > > [auto build test ERROR on vfio/next] > [also build test ERROR on v4.7-rc7 next-20160722] > [if your patch is applied to the wrong git tree, please drop us a note to > help improve the system] > > url: >

Re: [PATCH] KVM: arm64: ITS: move ITS registration into first VCPU run

On 03/08/2016 19:56, Auger Eric wrote: > Hi > > On 03/08/2016 19:48, Auger Eric wrote: >> Hi Andre, Christoffer, >> >> On 03/08/2016 19:18, Andre Przywara wrote: >>> Hi, >>> >>> On 03/08/16 18:11, Christoffer Dall wrote: >>>&

Re: [PATCH] KVM: arm64: ITS: move ITS registration into first VCPU run

Hi Andre, Christoffer, On 03/08/2016 19:18, Andre Przywara wrote: > Hi, > > On 03/08/16 18:11, Christoffer Dall wrote: >> On Wed, Aug 03, 2016 at 03:57:45PM +0100, Andre Przywara wrote: >>> Currently we register ITS devices upon userland issuing the CTRL_INIT >>> ioctl to mark initialization of

Re: [PATCH] KVM: arm64: ITS: move ITS registration into first VCPU run

Hi On 03/08/2016 19:48, Auger Eric wrote: > Hi Andre, Christoffer, > > On 03/08/2016 19:18, Andre Przywara wrote: >> Hi, >> >> On 03/08/16 18:11, Christoffer Dall wrote: >>> On Wed, Aug 03, 2016 at 03:57:45PM +0100, Andre Przywara wrote: >>>>

Re: [PATCH] KVM: arm64: ITS: move ITS registration into first VCPU run

Hi Andre, On 04/08/2016 12:17, Andre Przywara wrote: > Hi Eric, > > On 04/08/16 11:11, Auger Eric wrote: >> Hi Andre, >> >> On 03/08/2016 16:57, Andre Przywara wrote: >>> Currently we register ITS devices upon userland issuing the CTRL_INIT >>> io

Re: [PATCH] KVM: arm64: ITS: move ITS registration into first VCPU run

Hi Andre, On 03/08/2016 16:57, Andre Przywara wrote: > Currently we register ITS devices upon userland issuing the CTRL_INIT > ioctl to mark initialization of the ITS as done. > This deviates from the initialization sequence of the existing GIC > devices and does not play well with the way QEMU

Re: [RFC v6 4/6] KVM: arm/arm64: enable irqchip routing

Hi Andre, On 11/07/2016 18:25, Andre Przywara wrote: > Hi Eric, > > On 06/07/16 09:47, Eric Auger wrote: >> This patch adds compilation and link against irqchip. >> >> Main motivation behind using irqchip code is to enable MSI >> routing code. In the future irqchip routing may also be useful >>

Re: [RFC v6 4/6] KVM: arm/arm64: enable irqchip routing

Hi Drew, Radim, On 08/07/2016 22:55, Radim Krčmář wrote: > 2016-07-08 10:52+0200, Andrew Jones: >> On Fri, Jul 08, 2016 at 10:16:53AM +0200, Auger Eric wrote: >>> On 07/07/2016 19:20, Andrew Jones wrote: >>>> On Wed, Jul 06, 2016 at 10:47:53AM +0200, Eric Auger wrot

Re: [RFC v6 6/6] KVM: arm: enable KVM_SIGNAL_MSI and MSI routing

Hi Andre, On 11/07/2016 18:26, Andre Przywara wrote: > Hi, > > On 06/07/16 09:47, Eric Auger wrote: >> If the ITS modality is not available, let's simply support MSI >> injection by transforming the MSI.data into an SPI ID. >> >> This becomes possible to use KVM_SIGNAL_MSI ioctl and MSI >>

Re: [PATCH v11 06/10] genirq/msi-doorbell: msi_doorbell_safe

Hi, On 20/07/2016 10:12, Thomas Gleixner wrote: > On Tue, 19 Jul 2016, Eric Auger wrote: >> +bool msi_doorbell_safe(void) >> +{ >> +struct irqchip_doorbell *db; >> +bool irq_remapping = true; >> + >> +mutex_lock(_doorbell_mutex); >> +list_for_each_entry(db, _doorbell_list, next) {

Re: [PATCH v11 05/10] genirq/msi-doorbell: msi_doorbell_pages

Hi Thomas, On 19/07/2016 16:38, Thomas Gleixner wrote: > On Tue, 19 Jul 2016, Eric Auger wrote: >> msi_doorbell_pages sum up the number of iommu pages of a given order > > adding () to the function name would make it immediately clear that > msi_doorbell_pages is a function. > >> +/** >> + *

Re: [PATCH v10 00/17] KVM: arm64: GICv3 ITS emulation

Hi Andre, On 15/07/2016 13:43, Andre Przywara wrote: > Hi, > > this series allows those KVM guests that use an emulated GICv3 to use LPIs > as well, though in the moment this is limited to emulated PCI devices. > This is based on kvmarm/queue, which now only features the new VGIC >

Re: [PATCH v10 09/17] KVM: arm64: introduce ITS emulation file with MMIO framework

Hi Andre, On 18/07/2016 18:34, Andre Przywara wrote: > Hi Eric, > > On 18/07/16 10:18, Auger Eric wrote: >> Hi Andre, Marc, >> >> On 15/07/2016 13:43, Andre Przywara wrote: >>> The ARM GICv3 ITS emulation code goes into a separate file, but needs >&g

Re: [PATCH v11 0/8] KVM PCIe/MSI passthrough on ARM/ARM64: kernel part 1/3: iommu changes

Hi Dennis On 20/07/2016 11:56, Dennis Chen wrote: > Hi Eric, > > On Tue, Jul 19, 2016 at 12:55:03PM +, Eric Auger wrote: >> This series introduces the msi-iommu api used to: >> >> - allocate/free resources for MSI IOMMU mapping >> - set the MSI iova window aperture >> - map/unmap physical

Re: [RFC v7 5/7] KVM: arm/arm64: enable irqchip routing

Hi Marc, On 19/07/2016 18:16, Marc Zyngier wrote: > On 19/07/16 16:46, Paolo Bonzini wrote: >> >> >> On 19/07/2016 16:56, Marc Zyngier wrote: >>> On 18/07/16 14:25, Eric Auger wrote: This patch adds compilation and link against irqchip. Main motivation behind using irqchip code is

Re: [PATCH v11 05/10] genirq/msi-doorbell: msi_doorbell_pages

Hi Thomas, On 19/07/2016 16:38, Thomas Gleixner wrote: > On Tue, 19 Jul 2016, Eric Auger wrote: >> msi_doorbell_pages sum up the number of iommu pages of a given order > > adding () to the function name would make it immediately clear that > msi_doorbell_pages is a function. > >> +/** >> + *

Re: [PATCH v11 04/10] genirq/msi-doorbell: allow MSI doorbell (un)registration

Hi Thomas, On 19/07/2016 16:22, Thomas Gleixner wrote: > On Tue, 19 Jul 2016, Eric Auger wrote: >> + >> +#include >> +#include >> +#include >> + >> +struct irqchip_doorbell { >> +struct irq_chip_msi_doorbell_info info; >> +struct list_head next; > > Again, please align the struct

Re: [PATCH v10 09/17] KVM: arm64: introduce ITS emulation file with MMIO framework

Hi Andre, Marc, On 15/07/2016 13:43, Andre Przywara wrote: > The ARM GICv3 ITS emulation code goes into a separate file, but needs > to be connected to the GICv3 emulation, of which it is an option. > The ITS MMIO handlers require the respective ITS pointer to be passed in, > so we amend the

Re: [PATCH v10 09/17] KVM: arm64: introduce ITS emulation file with MMIO framework

Hi, On 18/07/2016 11:43, Marc Zyngier wrote: > On 18/07/16 10:18, Auger Eric wrote: >> Hi Andre, Marc, >> >> On 15/07/2016 13:43, Andre Przywara wrote: >>> The ARM GICv3 ITS emulation code goes into a separate file, but needs >>> to be connected to the GI

Re: [PATCH v7 10/17] KVM: arm64: introduce new KVM ITS device

Hi Andre, On 04/07/2016 19:40, Andre Przywara wrote: > Hi Eric, > > On 04/07/16 16:00, Auger Eric wrote: >> Hi Peter, >> >> On 04/07/2016 16:32, Peter Maydell wrote: >>> On 4 July 2016 at 15:27, Auger Eric <eric.au...@redhat.com> wrote: >>>>

Re: [PATCH v7 10/17] KVM: arm64: introduce new KVM ITS device

Hi Andre, On 04/07/2016 19:40, Andre Przywara wrote: > Hi Eric, > > On 04/07/16 16:00, Auger Eric wrote: >> Hi Peter, >> >> On 04/07/2016 16:32, Peter Maydell wrote: >>> On 4 July 2016 at 15:27, Auger Eric <eric.au...@redhat.com> wrote: >>>>

Re: [PATCH v7 10/17] KVM: arm64: introduce new KVM ITS device

On 05/07/2016 10:59, Andre Przywara wrote: > Hi Eric, > > thank you very much for the elaborate explanation! > > On 05/07/16 08:40, Auger Eric wrote: >> Hi Andre, >> On 04/07/2016 19:40, Andre Przywara wrote: >>> Hi Eric, >>> >>&

Re: [PATCH] KVM: arm/arm64: remove kvm_vgic_*early_init() functions

Hi Andre, On 05/07/2016 15:50, Andre Przywara wrote: > kvm_vgic_early_init() and kvm_vgic_vcpu_early_init() were only used > with the old VGIC, on the new VGIC these functions do nothing. > Follow the comment in vgic-init.c and remove those functions and > their calls. > > Signed-off-by: Andre

Re: [RFC v6 4/6] KVM: arm/arm64: enable irqchip routing

Hi Drew, On 07/07/2016 19:20, Andrew Jones wrote: > On Wed, Jul 06, 2016 at 10:47:53AM +0200, Eric Auger wrote: >> This patch adds compilation and link against irqchip. >> >> Main motivation behind using irqchip code is to enable MSI >> routing code. In the future irqchip routing may also be

Re: [PATCH v7 09/17] KVM: arm64: introduce ITS emulation file with MMIO framework

On 04/07/2016 16:00, Andre Przywara wrote: > Hi, > > On 04/07/16 14:54, Auger Eric wrote: >> Hi Andre, >> >> On 04/07/2016 15:38, Andre Przywara wrote: >>> 2) on KVM_DEV_ARM_VGIC_GRP_ADDR check that "initialized" is false >>> 3) on KVM_D

Re: [PATCH v7 10/17] KVM: arm64: introduce new KVM ITS device

Andre, On 04/07/2016 16:05, Andre Przywara wrote: > Hi, > > On 04/07/16 10:00, Auger Eric wrote: >> Hi Andre, >> >> On 28/06/2016 14:32, Andre Przywara wrote: >>> Introduce a new KVM device that represents an ARM Interrupt Translation >>> Service

Re: [PATCH v7 10/17] KVM: arm64: introduce new KVM ITS device

Hi Peter, On 04/07/2016 16:32, Peter Maydell wrote: > On 4 July 2016 at 15:27, Auger Eric <eric.au...@redhat.com> wrote: >> Andre, >> >> On 04/07/2016 16:05, Andre Przywara wrote: >>> Hi, >>> >>> On 04/07/16 10:00, Auger Eric wrote: >>

Re: [PATCH v8 00/17] KVM: arm64: GICv3 ITS emulation

Hi Andre, On 05/07/2016 13:22, Andre Przywara wrote: > Hi, > > this series allows those KVM guests that use an emulated GICv3 to use LPIs > as well, though in the moment this is limited to emulated PCI devices. > This is based on kvmarm/queue, which now only features the new VGIC >

Re: [PATCH v2] KVM: arm64: ITS: move ITS registration into first VCPU run

Hi Andre, On 08/08/2016 17:45, Andre Przywara wrote: > Currently we register an ITS device upon userland issuing the CTLR_INIT > ioctl to mark initialization of the ITS as done. > This deviates from the initialization sequence of the existing GIC > devices and does not play well with the way QEMU

Re: [PATCH v7 00/17] KVM: arm64: GICv3 ITS emulation

Hi, On 30/06/2016 13:40, Andrew Jones wrote: > On Thu, Jun 30, 2016 at 11:09:30AM +0100, Andre Przywara wrote: >> Hi, >> >> On 29/06/16 05:43, Bharat Bhushan wrote: >>> >>> -Original Message- From: kvmarm-boun...@lists.cs.columbia.edu [mailto:kvmarm-

Re: [PATCH v7 01/17] KVM: arm/arm64: move redistributor kvm_io_devices

Hi Andre, On 28/06/2016 14:32, Andre Przywara wrote: > Logically a GICv3 redistributor is assigned to a (v)CPU, so we should > aim to keep redistributor related variables out of our struct vgic_dist. > > Let's start by replacing the redistributor related kvm_io_device array > with two members in

Re: [PATCH v7 02/17] KVM: arm/arm64: check return value for kvm_register_vgic_device

On 28/06/2016 14:32, Andre Przywara wrote: > kvm_register_device_ops() can return an error, so lets check its return returned > value and propagate this up the call chain. > > Signed-off-by: Andre Przywara > --- > virt/kvm/arm/vgic/vgic-kvm-device.c | 15

Re: [PATCH v7 05/17] KVM: kvm_io_bus: add kvm_io_bus_get_dev() call

On 28/06/2016 14:32, Andre Przywara wrote: > The kvm_io_bus framework is a nice place of holding information about > various MMIO regions for kernel emulated devices. > Add a call to retrieve the kvm_io_device structure which is associated > with a certain MMIO address. This avoids to duplicate

Re: [PATCH v7 06/17] KVM: arm/arm64: VGIC: add refcounting for IRQs

Hi Andre, On 28/06/2016 14:32, Andre Przywara wrote: > In the moment our struct vgic_irq's are statically allocated at guest > creation time. So getting a pointer to an IRQ structure is trivial and > safe. LPIs are more dynamic, they can be mapped and unmapped at any time > during the guest's

Re: [PATCH v7 08/17] KVM: arm64: handle ITS related GICv3 redistributor registers

Hi Andre, On 28/06/2016 14:32, Andre Przywara wrote: > In the GICv3 redistributor there are the PENDBASER and PROPBASER > registers which we did not emulate so far, as they only make sense > when having an ITS. In preparation for that emulate those MMIO > accesses by storing the 64-bit data

Re: [PATCH v7 17/17] KVM: arm64: enable ITS emulation as a virtual MSI controller

Hi Andre, On 28/06/2016 14:32, Andre Przywara wrote: > Now that all ITS emulation functionality is in place, we advertise > MSI functionality to userland and also the ITS device to the guest - if > userland has configured that. > > Signed-off-by: Andre Przywara > --- >

Re: [PATCH] KVM: arm64: Increase number of memslots to 512

Hi Linu, On 11/01/2017 17:52, linucher...@gmail.com wrote: > From: Linu Cherian > > Having only 32 memslots is a real constraint for the maximum number of > PCI devices that can be assigned to a single guest. Assuming each PCI > device/virtual function having two memory

Re: [PATCH v2] KVM: arm/arm64: vgic: Add debugfs vgic-state file

Hi Christoffer, On 24/01/2017 14:25, Christoffer Dall wrote: > Add a file to debugfs to read the in-kernel state of the vgic. We don't > do any locking of the entire VGIC state while traversing all the IRQs, > so if the VM is running the user/developer may not see a quiesced state, > but should

Re: [PATCH v11 1/8] arm/arm64: vgic: Implement support for userspace access

Hi, On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > Read and write of some registers like ISPENDR and ICPENDR > from userspace requires special handling when compared to > guest access for these registers. > > Refer to

Re: [PATCH v11 2/8] arm/arm64: vgic: Add distributor and redistributor access

Hi, On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > VGICv3 Distributor and Redistributor registers are accessed using > KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_REDIST_REGS > with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR

Re: [PATCH v11 5/8] arm/arm64: vgic: Introduce VENG0 and VENG1 fields to vmcr struct

Hi, On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable > and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member > variables to struct vmcr to support read and write of

Re: [PATCH v11 6/8] arm/arm64: vgic: Implement VGICv3 CPU interface access

Hi, On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > VGICv3 CPU interface registers are accessed using > KVM_DEV_ARM_VGIC_CPU_SYSREGS ioctl. These registers are accessed > as 64-bit. The cpu MPIDR value is passed along with register id. > It

Re: [PATCH v11 7/8] arm/arm64: vgic: Implement KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO ioctl

Hi, On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > Userspace requires to store and restore of line_level for > level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO. > > Signed-off-by: Vijaya Kumar K

Re: [PATCH v11 7/8] arm/arm64: vgic: Implement KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO ioctl

Hi, On 27/01/2017 09:32, Auger Eric wrote: > Hi, > > On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: >> From: Vijaya Kumar K <vijaya.ku...@cavium.com> >> >> Userspace requires to store and restore of line_level for >> level triggered interrupts usin

Re: [PATCH v11 8/8] arm/arm64: Documentation: Update arm-vgic-v3.txt

Hi Vijaya, On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > Update error code returned for Invalid CPU interface register > value and access in AArch32 mode. > > Signed-off-by: Vijaya Kumar K Reviewed-by: Eric

Re: [PATCH v11 0/8] arm/arm64: vgic: Implement API for vGICv3 live migration

Hi Vijaya, On 26/01/2017 15:20, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > This patchset adds API for saving and restoring > of VGICv3 registers to support live migration with new vgic feature. > This API definition is as per version of VGICv3

Re: [RFC 01/13] KVM: arm/arm64: Add vITS save/restore API documentation

Hi Marc, On 13/01/2017 10:46, Marc Zyngier wrote: > On 13/01/17 09:07, Auger Eric wrote: >> Hi Marc, >> >> On 12/01/2017 17:52, Marc Zyngier wrote: >>> Hi Eric, >>> >>> On 12/01/17 15:56, Eric Auger wrote: >>>> Add description for how

Re: [RFC PATCH 07/33] irqchip/gic-v3-its: Macro-ize its_send_single_command

On 17/01/2017 11:20, Marc Zyngier wrote: > Most ITS commands do operate on a collection object, and require > a SYNC command to be performed on that collection in order to > guarantee the execution of the first command. > > With GICv4 ITS, another set of commands perform similar operations > on

Re: [RFC PATCH 08/33] irqchip/gic-v3-its: Implement irq_set_irqchip_state for pending state

On 17/01/2017 11:20, Marc Zyngier wrote: > Allow the pending state of an LPI to be set or cleared via > irq_set_irqchip_state. > > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger Eric > --- > drivers/irqchip/irq-gic-v3-its.c | 78 >

Re: [RFC PATCH 09/33] irqchip/gic-v3-its: Split out property table allocation

Hi Marc, On 17/01/2017 11:20, Marc Zyngier wrote: > Move the LPI property table allocation into its own function, as > this is going to be required for those associated with VMs in > the future. > > Signed-off-by: Marc Zyngier > --- > drivers/irqchip/irq-gic-v3-its.c | 28

Re: [RFC PATCH 10/33] irqchip/gic-v4-its: Allow use of indirect VCPU tables

Hi Marc, On 17/01/2017 11:20, Marc Zyngier wrote: > The VCPU tables can be quite sparse as well, and it makes sense > to use indirect tables as well if possible. > > Signed-off-by: Marc Zyngier > --- > drivers/irqchip/irq-gic-v3-its.c | 20 +--- > 1 file

Re: [PATCH] KVM: arm/arm64: vgic-v3: Don't pretend to support IRQ/FIQ bypass

Hi Marc, On 22/02/2017 13:13, Marc Zyngier wrote: > Our GICv3 emulation always presents ICC_SRE_EL1 with DIB/DFB set to > zero, which implies that there is a way to bypass the GIC and > inject raw IRQ/FIQ by driving the CPU pins. > > Of course, we don't allow that when the GIC is configured, but

Re: [RFC v2 05/19] KVM: arm64: ITS: Implement vgic_its_has_attr_regs and attr_regs_access

Hi Andre, On 10/02/2017 18:06, Andre Przywara wrote: > Hi, > > On 10/02/17 12:26, Auger Eric wrote: >> Hi Andre, >> >> On 10/02/2017 12:57, Andre Przywara wrote: >>> On 08/02/17 11:43, Eric Auger wrote: >>> >>> Salut Eric, >>> >

Re: [RFC v2 05/19] KVM: arm64: ITS: Implement vgic_its_has_attr_regs and attr_regs_access

Hi Andre, On 10/02/2017 12:57, Andre Przywara wrote: > On 08/02/17 11:43, Eric Auger wrote: > > Salut Eric, > > one minor thing below, but first a general question: > I take it that the state of the ITS (enabled/disabled) shouldn't matter > when it comes to reading/writing registers, right?

Re: [RFC PATCH 02/33] irqchip/gic-v3: Add VLPI/DirectLPI discovery

Hi, On 17/01/2017 11:20, Marc Zyngier wrote: > Add helper functions that probe for VLPI and DirectLPI properties. > > Signed-off-by: Marc Zyngier Besides the returned value previous questions, Reviewed-by: Eric Auger Eric > --- >

Re: [RFC PATCH 03/33] irqchip/gic-v3-its: Refactor command encoding

On 17/01/2017 11:20, Marc Zyngier wrote: > The way we encode the various ITS command fields is both tedious > and error prone. Let's introduce a helper function that performs > the encoding, and convert the existing encoders to use that > helper. > > Signed-off-by: Marc Zyngier

Re: [RFC PATCH 04/33] irqchip/gic-v3-its: Move LPI definitions around

Hi Marc, On 17/01/2017 11:20, Marc Zyngier wrote: > The various LPI definitions are in the middle of the code, and > would be better placed at the beginning, given that we're going > to use some of them much earlier. > > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger

Re: [RFC PATCH 06/33] irqchip/gic-v3-its: Add probing for VLPI properties

Hi, On 13/02/2017 11:00, Thomas Gleixner wrote: > On Tue, 17 Jan 2017, Marc Zyngier wrote: >> +typer = gic_read_typer(its_base + GITS_TYPER); >> its->base = its_base; >> its->phys_base = res->start; >> -its->ite_size = ((gic_read_typer(its_base + GITS_TYPER) >> 4) & 0xf) + >>

Re: [RFC PATCH 01/33] irqchip/gic-v3: Add redistributor iterator

Hi Marc, On 17/01/2017 11:20, Marc Zyngier wrote: > In order to discover the VLPI properties, we need to iterate over > the redistributor regions. As we already have code that does this, > let's factor it out and make it slightly more generic. > > Signed-off-by: Marc Zyngier

Re: [PATCH] KVM: arm64: VGIC: fix command handling while ITS being disabled

Hi Andre, On 16/02/2017 11:41, Andre Przywara wrote: > The ITS spec says that ITS commands are only processed when the ITS > is enabled (section 8.19.4, Enabled, bit[0]). Our emulation was not taking > this into account. > Fix this by checking the enabled state before handling CWRITER writes.

Re: [RFC PATCH 08/33] irqchip/gic-v3-its: Implement irq_set_irqchip_state for pending state

Marc, On 17/01/2017 11:20, Marc Zyngier wrote: > Allow the pending state of an LPI to be set or cleared via > irq_set_irqchip_state. > > Signed-off-by: Marc Zyngier Reviewed-by: Eric Auger Eric > --- > drivers/irqchip/irq-gic-v3-its.c | 78 >

Re: [RFC PATCH 07/33] irqchip/gic-v3-its: Macro-ize its_send_single_command

Hi, On 17/01/2017 11:20, Marc Zyngier wrote: > Most ITS commands do operate on a collection object, and require > a SYNC command to be performed on that collection in order to > guarantee the execution of the first command. > > With GICv4 ITS, another set of commands perform similar operations >

Re: [RFC v2 18/19] KVM: arm64: ITS: Device table save/restore

Hi all, On 08/02/2017 12:43, Eric Auger wrote: > This patch flushes the device table entries into guest RAM. > Both flat table and 2 stage tables are supported. DeviceId > indexing is used. > > For each device listed in the device table, we also flush > the translation table using the

Re: [Qemu-devel] [kvm-unit-tests PATCH v3 07/10] arm/arm64: add initial gicv3 support

Hi Drew, On 15/07/2016 15:00, Andrew Jones wrote: > Signed-off-by: Andrew Jones > > --- > v2: configure irqs as NS GRP1 > --- > lib/arm/asm/arch_gicv3.h | 184 ++ > lib/arm/asm/gic-v3.h | 321 > + >

Re: [Qemu-devel] [kvm-unit-tests PATCH v3 05/10] arm/arm64: irq enable/disable

Hi, On 15/07/2016 15:00, Andrew Jones wrote: > Reviewed-by: Alex Bennée > Signed-off-by: Andrew Jones > --- > lib/arm/asm/processor.h | 10 ++ > lib/arm64/asm/processor.h | 10 ++ > 2 files changed, 20 insertions(+) > > diff --git

Re: [Qemu-devel] [kvm-unit-tests PATCH v3 04/10] arm/arm64: add some delay routines

Hi Drew, On 15/07/2016 15:00, Andrew Jones wrote: > Allow a thread to wait some specified amount of time. Can > specify in cycles, usecs, and msecs. > > Reviewed-by: Alex Bennée > Signed-off-by: Andrew Jones > --- > lib/arm/asm/processor.h | 19

Re: [Qemu-devel] [kvm-unit-tests PATCH v3 10/10] arm/arm64: gic: don't just use zero

Hi Drew, On 15/07/2016 15:00, Andrew Jones wrote: > Allow user to select who sends ipis and with which irq, > rather than just always sending irq=0 from cpu0. > > Signed-off-by: Andrew Jones > > --- > v2: actually check that the irq received was the irq sent, > and (for

Re: [Qemu-devel] [kvm-unit-tests PATCH v3 03/10] arm/arm64: smp: support more than 8 cpus

Hi Drew, Proper commit message? ... also selects the vgic model corresponding to the host > Reviewed-by: Alex Bennée > Signed-off-by: Andrew Jones > --- > arm/run | 19 --- > arm/selftest.c| 5 - >

Re: [Qemu-devel] [kvm-unit-tests PATCH v3 01/10] lib: xstr: allow multiple args

Hi Drew, On 15/07/2016 15:00, Andrew Jones wrote: > Make implementation equivalent to Linux's include/linux/stringify.h > > Signed-off-by: Andrew Jones > --- > lib/libcflat.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/lib/libcflat.h

Re: [Qemu-devel] [kvm-unit-tests PATCH v3 02/10] arm64: fix get_"sysreg32" and make MPIDR 64bit

Hi, On 15/07/2016 15:00, Andrew Jones wrote: > mrs is always 64bit, so we should always use a 64bit register. > Sometimes we'll only want to return the lower 32, but not for > MPIDR, as that does define fields in the upper 32. > > Reviewed-by: Alex Bennée >

Re: [Qemu-devel] [kvm-unit-tests PATCH v3 09/10] arm/arm64: gicv3: add an IPI test

Hi Drew, On 15/07/2016 15:00, Andrew Jones wrote: > Signed-off-by: Andrew Jones > > --- > v2: use IRM for gicv3 broadcast > --- > arm/gic.c | 157 > ++ > arm/unittests.cfg | 6 +++ > 2 files changed, 154

Re: [Qemu-devel] [kvm-unit-tests PATCH v3 08/10] arm/arm64: gicv2: add an IPI test

Hi Drew, On 15/07/2016 15:00, Andrew Jones wrote: > Signed-off-by: Andrew Jones > --- > v2: add more details in the output if a test fails, > report spurious interrupts if we get them > --- > arm/Makefile.common | 6 +- > arm/gic.c | 194 >

Re: [PATCH v2 2/2] KVM: arm/arm64: Rename vgic_attr_regs_access to vgic_attr_regs_access_v2

Hi, On 16/08/2016 19:35, Christoffer Dall wrote: > Just a rename so we can implement a v3-specific function later. > > We take the chance to get rid of the V2/V3 ops comments as well. > > No functional change. > > Signed-off-by: Christoffer Dall > --- >

Re: [PATCH v2 1/2] KVM: arm/arm64: Factor out vgic_attr_regs_access functionality

Hi Christoffer, On 16/08/2016 19:35, Christoffer Dall wrote: > As we are about to deal with multiple data types and situations where > the vgic should not be initialized when doing userspace accesses on the > register attributes, factor out the functionality of > vgic_attr_regs_access into

Re: [kvm-unit-tests PATCH v6 11/11] arm/arm64: gic: don't just use zero

Hi, On 14/11/2016 22:08, Andrew Jones wrote: > Allow user to select who sends ipis and with which irq, > rather than just always sending irq=0 from cpu0. >From a user point of view is there a way to know the list of available tests and their arg? > > Signed-off-by: Andrew Jones

Re: [kvm-unit-tests PATCH v6 09/11] arm/arm64: add initial gicv3 support

Hi Drew, On 14/11/2016 22:08, Andrew Jones wrote: > Reviewed-by: Alex Bennée > Signed-off-by: Andrew Jones > > --- > v6: > - added comments [Alex] > - added stride parameter to gicv3_set_redist_base [Andre] > - redist-wait s/rwp/uwp/ and comment

Re: [kvm-unit-tests PATCH v6 08/11] libcflat: add IS_ALIGNED() macro, and page sizes

Hi, On 14/11/2016 22:08, Andrew Jones wrote: > From: Peter Xu > > These macros will be useful to do page alignment checks. > > Reviewed-by: Andre Przywara > Signed-off-by: Peter Xu > [drew: also added SZ_64K and changed to shifts]

Re: [kvm-unit-tests PATCH v6 06/11] arm/arm64: add initial gicv2 support

Hi, On 14/11/2016 22:08, Andrew Jones wrote: > Add some gicv2 support. This just adds init and enable > functions, allowing unit tests to start messing with it. > > Reviewed-by: Andre Przywara > Signed-off-by: Andrew Jones > > --- > v6: added

Re: [Qemu-devel] [kvm-unit-tests PATCH 3/4] arm/arm64: GICv2: add GICD_ITARGETSR testing

Hi Andre, On 23/11/2016 14:24, Auger Eric wrote: > Hi, > > On 18/11/2016 15:20, Andrew Jones wrote: >> On Thu, Nov 17, 2016 at 05:57:51PM +, Andre Przywara wrote: >>> Some tests for the ITARGETS registers. >>> Bits corresponding to non-existent CPUs must be

Re: [kvm-unit-tests PATCH v6 11/11] arm/arm64: gic: don't just use zero

On 23/11/2016 14:01, Andrew Jones wrote: > On Wed, Nov 23, 2016 at 12:28:34PM +0100, Auger Eric wrote: >> Hi, >> >> On 14/11/2016 22:08, Andrew Jones wrote: >>> Allow user to select who sends ipis and with which irq, >>> rather than just always sendin

Re: [Qemu-devel] [kvm-unit-tests PATCH 2/4] arm/arm64: GICv2: add GICD_IPRIORITYR testing

Hi Andre, On 18/11/2016 15:02, Andrew Jones wrote: > On Thu, Nov 17, 2016 at 05:57:50PM +, Andre Przywara wrote: >> Some tests for the IPRIORITY registers. The significant number of bits >> is IMPLEMENTATION DEFINED, but should be the same for every IRQ. >> Also these registers must be

Re: [Qemu-devel] [kvm-unit-tests PATCH 3/4] arm/arm64: GICv2: add GICD_ITARGETSR testing

Hi, On 18/11/2016 15:20, Andrew Jones wrote: > On Thu, Nov 17, 2016 at 05:57:51PM +, Andre Przywara wrote: >> Some tests for the ITARGETS registers. >> Bits corresponding to non-existent CPUs must be RAZ/WI. >> These registers must be byte-accessible, also check that accesses beyond >> the

Re: [kvm-unit-tests PATCH v7 09/11] arm/arm64: add initial gicv3 support

Hi Drew, On 23/11/2016 17:54, Andrew Jones wrote: > Reviewed-by: Alex Bennée > Reviewed-by: Eric Auger > Signed-off-by: Andrew Jones > > --- > v7: split lib/arm/gic.c into gic-v2/3.c [Eric] > v6: > - added comments [Alex] >

Re: [kvm-unit-tests PATCH v7 11/11] arm/arm64: gic: don't just use zero

Hi, On 23/11/2016 17:54, Andrew Jones wrote: > Allow user to select who sends ipis and with which irq, > rather than just always sending irq=0 from cpu0. > > Signed-off-by: Andrew Jones Reviewed-by: Eric Auger Tested-by: Eric Auger

Re: [Qemu-devel] [kvm-unit-tests PATCH v7 11/11] arm/arm64: gic: don't just use zero

Hi Drew, On 24/11/2016 15:11, Andrew Jones wrote: > On Thu, Nov 24, 2016 at 10:57:01AM +0100, Auger Eric wrote: >> Hi, >> >> On 23/11/2016 17:54, Andrew Jones wrote: >>> Allow user to select who sends ipis and with which irq, >>> rather than just always send

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