On Wed, Feb 08, 2017 at 12:45:41PM +0530, linucher...@gmail.com wrote:
> From: Linu Cherian
>
> Having only 32 memslots is a real constraint for the maximum
> number of PCI devices that can be assigned to a single guest.
> Assuming each PCI device/virtual function having two memory BAR
> regions,
cache type/info related macros and
> replaces the hardcorded values. It also removes some of the comments
> that become trivial with the macro names.
>
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Christoffer Dall
> Cc: Marc Zyngier
> Signed-off-by: Su
Hi Mark,
On Tue, Jan 31, 2017 at 06:05:38PM +, Mark Rutland wrote:
> Whenever we add new functionality involving new system registers, we need to
> add sys_reg() definitions so that we can access the registers regardless of
> whether the toolchain can assemble them. At the same time, we have t
On Fri, Feb 24, 2017 at 09:55:09AM +, Raz wrote:
> Hello
> I am reading the arm8a book. According to the documentation the output
> address of each level 3 entry in TTBRx_EL1points to an address in the
> physical memory.
> By looking in the mmu tab in the DS5 studio I can see the TTBRs tables.
that when the GIC is configured, but
> we fail to indicate that to the guest. The obvious fix is to
> set these bits (and never let them being changed again).
>
> Reported-by: Peter Maydell
> Signed-off-by: Marc Zyngier
Acked-by: Christoffer Dall
> ---
> include/linux/irqchip
On Sun, Feb 26, 2017 at 12:36:58PM +0530, Linu Cherian wrote:
> On Thu, Feb 23, 2017 at 3:44 PM, Christoffer Dall wrote:
> > On Wed, Feb 08, 2017 at 12:45:41PM +0530, linucher...@gmail.com wrote:
> >> From: Linu Cherian
> >>
> >> Having only 32 memslots
t to clear before invalidating TLBs.
>
> Address the issue by introducing two wrappers (__tlb_switch_to_guest
> and __tlb_switch_to_host) that take care of both the VTTBR_EL2
> and HCR_EL2.TGE switching.
>
> Reported-by: Tomasz Nowicki
> Tested-by: Tomasz Nowicki
> Signed-off-by
On Sun, Feb 26, 2017 at 12:12:35PM +0200, Roman Livshits wrote:
> Hi
>
> I am trying to run Android on qemu virt machine.
> I want to use virt as this was used by the op-tee for implementing
> TEE for ARM TrustZone, see
> https://github.com/OP-TEE/build#op-tee-buildgit, so hope that
> running Andr
Hi Marc,
On Wed, Feb 22, 2017 at 11:47:20AM +, Marc Zyngier wrote:
> Running the following code:
>
> root@zomby-woof:~# cat test-pmu.c
> int main(int argc, char *argv[])
> {
> unsigned int val;
> asm ("mrc p15, 0, %0, c9, c13, 0\n" : "=r" (val));
> return val;
> }
>
> in a
From: Jintack Lim
Currently, if a vcpu thread tries to change its own active state when
the irq is already in AP list, it'll loop forever. Since the VCPU thread
has already synced back LR state to the struct vgic_irq, let it modify
its own state safely.
Signed-off-by: Jintack Lim
---
virt/kvm/
From: Jintack Lim
Currently, if a vcpu thread tries to change the active state of an
interrupt which is already on the same vcpu's AP list, Since the VGIC
mmio handler is called after a vcpu has already synced back the LR state
to the struct vgic_irq, we can just let it proceed safely.
Signed-of
From: Christoffer Dall
We found a deadlock when changing the active state of an interrupt while
the interrupt is queued on the LR of the running VCPU.
Defend KVM against this bug in the future now when we've introduced a
fix.
Signed-off-by: Christoffer Dall
---
arm/gic.c
the guest, with a corresponding (ratelimited) warning in
> the host dmesg. We could later improve on this with with a new (opt-in)
> exit to the host userspace.
>
> Signed-off-by: Mark Rutland
> Cc: Christoffer Dall
> Cc: Dave Martin
> Cc: Marc Zyngier
> Cc: Suzuki K
t; The patch makes KVM handle any unknown EC by injecting an UNDEFINED
> exception into the guest, with a corresponding (ratelimited) warning in
> the host dmesg. We could later improve on this with with a new (opt-in)
> exit to the host userspace.
>
> Signed-off-by: Mark Rutland
&g
From: Christoffer Dall
We found a deadlock when changing the active state of an interrupt while
the interrupt is queued on the LR of the running VCPU.
Defend KVM against this bug in the future now when we've introduced a
fix.
Signed-off-by: Christoffer Dall
---
Sending with the right su
On Tue, Mar 07, 2017 at 09:33:37AM +, Marc Zyngier wrote:
> On Sun, Mar 05 2017 at 3:01:09 pm GMT, Christoffer Dall
> wrote:
> > Hi Marc,
> >
> > On Wed, Feb 22, 2017 at 11:47:20AM +, Marc Zyngier wrote:
> >> Running the following code:
> >&g
Hi Yasutaka,
On Thu, Mar 02, 2017 at 09:57:50AM -0500, Yasutaka Tanaka wrote:
> Hello KVM/ARM community,
>
> I am now trying to execute KVM on Raspberry Pi 3 Model B (RPI3).
> Does anyone know whether KVM/ARM can run with 32-bit mode on ARM Cortex A53?
Theoretically, it should.
>
> The CPU of
On Mon, Mar 06, 2017 at 02:20:44PM -0500, Jintack Lim wrote:
> Hi Christoffer,
>
> thanks for submitting this patch.
>
> On Mon, Mar 6, 2017 at 8:42 AM, Christoffer Dall
> wrote:
> > From: Jintack Lim
> >
> > Currently, if a vcpu thread tries to change
ite_its_ctlr(struct kvm *kvm, struct vgic_its *its,
> + gpa_t addr, unsigned int len,
> + unsigned long val)
> +{
> + mutex_lock(&its->cmd_lock);
> +
> + its->enabled = !!(val & GITS_CTLR_ENABLE);
> +
> + /*
> + * Try to process any pending commands. This function bails out early
> + * if the ITS is disabled or no commands have been queued.
> + */
> + vgic_its_process_commands(kvm, its);
> +
> + mutex_unlock(&its->cmd_lock);
> +}
> +
> #define REGISTER_ITS_DESC(off, rd, wr, length, acc) \
> {\
> .reg_offset = off, \
> --
> 2.9.0
>
Reviewed-by: Christoffer Dall
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On Tue, Mar 07, 2017 at 11:22:41AM +0530, linucher...@gmail.com wrote:
> From: Linu Cherian
Please add a patch description, even if it just repeats the subject line
as in this case.
Otherwise:
Acked-by: Christoffer Dall
>
> Signed-off-by: Linu Cherian
> ---
> Documentat
On Tue, Mar 07, 2017 at 08:34:33PM +0100, Radim Krčmář wrote:
> 2017-03-07 17:58+0100, Andrew Jones:
> > On Mon, Mar 06, 2017 at 07:16:09AM -0800, Christoffer Dall wrote:
> > > From: Christoffer Dall
> > >
> > > We found a deadlock when changing the active s
On Mon, Feb 27, 2017 at 06:55:04PM +0100, Andrew Jones wrote:
> QEMU would already prefer having control over the vcpu MPIDRs
> in order to correctly map vcpus to virtual numa nodes without
> having to first instantiate the vcpus. Also, when virtual cpu
> topologies are eventually describable, QEMU
>
> Signed-off-by: Andrew Jones
Acked-by: Christoffer Dall
> ---
> arch/arm/kvm/handle_exit.c | 1 +
> arch/arm/kvm/psci.c | 1 +
> arch/arm64/kvm/handle_exit.c | 1 +
> 3 files changed, 3 insertions(+)
>
> diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/
On Mon, Feb 27, 2017 at 06:55:01PM +0100, Andrew Jones wrote:
> This not only ensures visibility of changes to pause by using
> atomic ops, but also plugs a small race where a vcpu could get
> its pause state enabled just after its last check before entering
> the guest. With this patch, while the
On Wed, Mar 08, 2017 at 03:27:28PM +0100, Peter Maydell wrote:
> On 8 March 2017 at 14:19, Christoffer Dall
> wrote:
> > Isn't this all super racy? What prevents two VCPUs from getting the
> > same MPIDR at the same time?
>
> From a userspace API point of vie
Hi Drew,
On Mon, Feb 27, 2017 at 06:54:59PM +0100, Andrew Jones wrote:
> This series fixes four races. Two are easy to produce with a
> kvm-unit-test test[1], but the other two would be quite hard. I
> didn't even try to produce those. The two hard to produce races are
> addressed by changing vcpu
e/asm/kvm_host.h | 3 +--
> > 4 files changed, 8 insertions(+), 3 deletions(-)
>
> For the whole series:
>
> Acked-by: Marc Zyngier
>
> Christoffer: if you're happy with this series, I'll take it as part of
> the next batch of fixes.
>
Yes:
Reviewed-by: Christoffer Dall
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Hi Shanker,
On Sun, Mar 05, 2017 at 08:33:18PM -0600, Shanker Donthineni wrote:
> Now all the cpu_hwcaps features have their own static keys. We don't
> need a separate function hyp_alternate_select() to patch the vhe/nvhe
> code. We can achieve the same functionality by using has_vhe(). It
> impr
On Mon, Jan 16, 2017 at 05:33:29PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Move invariant_sys_regs before emulate_sys_reg so that it can be used
> later.
>
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/kvm/sys_regs.c | 193
> --
> 1 f
On Mon, Jan 16, 2017 at 05:33:31PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao
Please provide a commit message.
Thanks,
-Christoffer
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On Sat, Jan 28, 2017 at 03:47:54PM +0100, Andrew Jones wrote:
> On Mon, Jan 16, 2017 at 05:33:32PM +0800, Shannon Zhao wrote:
> > From: Shannon Zhao
> >
> > Add a capability to tell userspace that KVM supports cross type vCPU.
> > Add a cpu feature for userspace to set when it doesn't use host ty
On Mon, Jan 16, 2017 at 05:33:34PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Check if the configuration is fine.
This commit message really needs some love and attention.
>
> Signed-off-by: Shannon Zhao
> ---
> arch/arm64/kvm/sys_regs.c | 32 +++-
> 1 fi
On Wed, Mar 08, 2017 at 03:44:11PM +0100, Andrew Jones wrote:
> On Wed, Mar 08, 2017 at 06:33:12AM -0800, Christoffer Dall wrote:
> > > static int kvm_vcpu_initialized(struct kvm_vcpu *vcpu)
> > > @@ -621,7 +617,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu,
>
On Mon, Mar 13, 2017 at 06:27:55PM +0100, Andrew Jones wrote:
> On Mon, Mar 13, 2017 at 11:30:05AM +0100, Christoffer Dall wrote:
> > On Wed, Mar 08, 2017 at 03:44:11PM +0100, Andrew Jones wrote:
> > > On Wed, Mar 08, 2017 at 06:33:12AM -0800, Christoffer Dall wrote:
>
On Fri, Mar 10, 2017 at 08:17:22AM +, Marc Zyngier wrote:
> On Thu, Mar 09 2017 at 5:07:12 pm GMT, Mark Rutland
> wrote:
> > Currently we duplicate effort in maintaining system register encodings
> > across
> > arm64's , KVM's sysreg tables, and other places. This
> > redundancy
> > is unf
db105c997 ("arm/arm64: KVM: Introduce stage2_unmap_vm")
> Cc: sta...@vger.kernel.org # v3.19+
> Cc: Christoffer Dall
> Signed-off-by: Marc Zyngier
> Signed-off-by: Suzuki K Poulose
> ---
> arch/arm/kvm/mmu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff
ying to
> unmap a range.
>
> Fixes: commit d5d8184d35c9 ("KVM: ARM: Memory virtualization setup")
> Cc: sta...@vger.kernel.org # v3.10+
> Cc: Marc Zyngier
> Cc: Christoffer Dall
> Signed-off-by: Suzuki K Poulose
> ---
> arch/arm/kvm/mmu.c | 3 +++
> 1 fil
On Wed, Mar 15, 2017 at 09:39:26AM +, Marc Zyngier wrote:
> On 15/03/17 09:21, Christoffer Dall wrote:
> > On Tue, Mar 14, 2017 at 02:52:34PM +, Suzuki K Poulose wrote:
> >> In kvm_free_stage2_pgd() we don't hold the kvm->mmu_lock while calling
> >>
On Wed, Mar 15, 2017 at 09:34:53AM +, Marc Zyngier wrote:
> On 15/03/17 09:17, Christoffer Dall wrote:
> > On Tue, Mar 14, 2017 at 02:52:32PM +, Suzuki K Poulose wrote:
> >> From: Marc Zyngier
> >>
> >> We don't hold the mmap_sem while searching fo
uot;arm/arm64: KVM: map MMIO regions at creation
> time")
> Cc: Ard Biesheuvel
> Cc: Christoffer Dall
> Cc: Eric Auger
> Cc: sta...@vger.kernel.org # v3.18+
> Signed-off-by: Marc Zyngier
> [ Handle dirty page logging failure case ]
> Signed-off-by: Suzuki K Poulos
Hi Drew,
[Replying here to try to capture the discussion about this patch we had
at connect].
On Sat, Jan 28, 2017 at 03:55:51PM +0100, Andrew Jones wrote:
> On Mon, Jan 16, 2017 at 05:33:33PM +0800, Shannon Zhao wrote:
> > From: Shannon Zhao
> >
> > When initializing KVM, check whether physica
On Wed, Mar 15, 2017 at 01:28:07PM +, Marc Zyngier wrote:
> On 15/03/17 10:56, Christoffer Dall wrote:
> > On Wed, Mar 15, 2017 at 09:39:26AM +, Marc Zyngier wrote:
> >> On 15/03/17 09:21, Christoffer Dall wrote:
> >>> On Tue, Mar 14, 2017 at 02:52:34PM
On Wed, Mar 15, 2017 at 01:51:13PM +0100, Andrew Jones wrote:
> On Wed, Mar 15, 2017 at 12:50:44PM +0100, Christoffer Dall wrote:
> > Hi Drew,
> >
> > [Replying here to try to capture the discussion about this patch we had
> > at connect].
> >
> > On Sat, J
On Wed, Mar 15, 2017 at 03:06:33PM +0100, Andrew Jones wrote:
> On Wed, Mar 15, 2017 at 02:36:45PM +0100, Christoffer Dall wrote:
> > > If QEMU wants to know
> > > whether or not the host it's running on is heterogeneous, then
> > > it can just query sysfs, rathe
On Wed, Mar 15, 2017 at 07:50:36PM -0400, Yasutaka, T wrote:
> Hi Christopher and other KVM/ARM community members,
>
> I tried the following QEMU and Kernel combinations on Raspberry Pi 3
> (AArch64 mode) but failed:
>
> Latest commit of Alexander Graf's no-kvm-irqchip QEMU branch:
> https://gith
Marc Zyngier
> [ Added assert_spin_locked check ]
> Signed-off-by: Suzuki K Poulose
Reviewed-by: Christoffer Dall
> ---
> arch/arm/kvm/mmu.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
> index 7628ef1..3
kernel.org # v3.10+
> Cc: Paolo Bonzini
> Cc: Marc Zyngier
> Cc: Christoffer Dall
> Signed-off-by: Suzuki K Poulose
> [ Avoid vCPU starvation and lockup detector warnings ]
> Signed-off-by: Marc Zyngier
> Signed-off-by: Suzuki K Poulose
Reviewed-by: Christoffer Dal
On Fri, Mar 17, 2017 at 01:09:22AM -0400, Yasutaka, T wrote:
> 2017-03-16 5:38 GMT-04:00 Christoffer Dall :
>
> > On Wed, Mar 15, 2017 at 07:50:36PM -0400, Yasutaka, T wrote:
> > > Hi Christopher and other KVM/ARM community members,
> > >
> > > I tried the
From: Christoffer Dall
We currently have some code to clear the list registers on GICv3, but we
never call this code, because the caller got nuked when removing the old
vgic. We also used to have a similar GICv2 part, but that got lost in
the process too.
Let's reintroduce the logic for
On Sat, Mar 18, 2017 at 02:07:47PM +, Marc Zyngier wrote:
> On Sat, Mar 18 2017 at 12:56:56 pm GMT, Christoffer Dall
> wrote:
>
> Hi Christoffer,
>
> > From: Christoffer Dall
> >
> > We currently have some code to clear the list registers on GICv3, but we
der-X.
Patches also available on:
git://git.kernel.org/pub/scm/linux/kernel/git/cdall/linux.git gic-optimize
Thanks,
-Christoffer
Christoffer Dall (8):
KVM: arm/arm64: vgic: Defer touching GICH_VMCR to vcpu_load/put
KVM: arm/arm64: vgic: Get rid of live_lrs
KVM: arm/arm64: vgic: Get r
d-off-by: Christoffer Dall
---
virt/kvm/arm/vgic/vgic.c | 8
1 file changed, 8 insertions(+)
diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
index 2ac0def..1436c2e 100644
--- a/virt/kvm/arm/vgic/vgic.c
+++ b/virt/kvm/arm/vgic/vgic.c
@@ -637,12 +637,17 @@ static
From: Christoffer Dall
There is no need to calculate and maintain live_lrs when we always
populate the lowest numbered LRs first on every entry and clear all LRs
on every exit.
Signed-off-by: Christoffer Dall
---
include/kvm/arm_vgic.h| 2 --
virt/kvm/arm/hyp/vgic-v2-sr.c | 39
From: Christoffer Dall
We don't have to save/restore the VMCR on every entry to/from the guest,
since on GICv2 we can access the control interface from EL1 and on VHE
systems with GICv3 we can access the control interface from KVM running
in EL2.
GICv3 systems without VHE becomes the rare
From: Christoffer Dall
Now when we don't look at the MISR and EISR values anymore, we can get
rid of the logic to save them in the GIC save/restore code.
Signed-off-by: Christoffer Dall
---
virt/kvm/arm/hyp/vgic-v2-sr.c | 40
virt/kvm/arm/hyp/vg
(uses READ_ONCE) and can
therefore check if a list is empty or not without the need to take the
spinlock protecting the list.
Signed-off-by: Christoffer Dall
---
virt/kvm/arm/vgic/vgic.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
index
pty or not without the need to take the
spinlock protecting the list.
Signed-off-by: Christoffer Dall
---
virt/kvm/arm/vgic/vgic.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
index 093873e..8ecb009 100644
---
From: Christoffer Dall
We don't use these fields anymore so let's nuke them completely.
Signed-off-by: Christoffer Dall
---
include/kvm/arm_vgic.h| 4
virt/kvm/arm/hyp/vgic-v2-sr.c | 2 --
virt/kvm/arm/hyp/vgic-v3-sr.c | 2 --
3 files changed, 8 deletions(-)
diff --git
check additional initialization flags to ensure
they don't look at uninitialized data structures.
Signed-off-by: Christoffer Dall
---
virt/kvm/arm/vgic/vgic-init.c | 96 +--
1 file changed, 56 insertions(+), 40 deletions(-)
diff --git a/virt/kvm/arm
From: Christoffer Dall
Since we always read back the LRs that we wrote to the guest and the
MISR and EISR registers simply provide a summary of the configuration of
the bits in the LRs, there is really no need to read back those status
registers and process them. We can might as well just
On Thu, Mar 16, 2017 at 11:45:34AM +, Marc Zyngier wrote:
> We allow userspace to save/restore the GICC_PMR values in order
> to allow migration. This value is extracted from GICH_PMCR, where
> it occupies a 5 bit field. But the canonical PMR is an 8 bit
> value and we fail to shift the virtual
On Thu, Mar 16, 2017 at 11:45:35AM +, Marc Zyngier wrote:
> Similarily to the GICv2 case, we need to expose a PMR value that
> is either the 8bit value (KVM_DEV_ARM_VGIC_CTRL_CANONICAL_PMR
> being set) or the 5bit, truncated value otherwise.
I'm a bit puzzled by this patch as well. The struct
On Mon, Mar 20, 2017 at 03:12:05PM +, Marc Zyngier wrote:
> On 20/03/17 14:24, Christoffer Dall wrote:
> > On Thu, Mar 16, 2017 at 11:45:34AM +, Marc Zyngier wrote:
> >> We allow userspace to save/restore the GICC_PMR values in order
> >> to allow migration. T
On Mon, Mar 20, 2017 at 07:31:29PM +0100, Christoffer Dall wrote:
> On Mon, Mar 20, 2017 at 03:12:05PM +, Marc Zyngier wrote:
> > On 20/03/17 14:24, Christoffer Dall wrote:
> > > On Thu, Mar 16, 2017 at 11:45:34AM +, Marc Zyngier wrote:
> > >> We allow
between the ICH_VMCR register format
stored in memory and the ICC_X_EL1 registers exported to user space.
Signed-off-by: Christoffer Dall
---
arch/arm64/kvm/vgic-sys-reg-v3.c | 133 +++
virt/kvm/arm/vgic/vgic-mmio.c| 4 +-
virt/kvm/arm/vgic/vgic-v3.c
ff-by: Christoffer Dall
---
arch/arm64/kvm/vgic-sys-reg-v3.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/kvm/vgic-sys-reg-v3.c b/arch/arm64/kvm/vgic-sys-reg-v3.c
index 48848db..33f111c 100644
--- a/arch/arm64/kvm/vgic-sys-reg-v3.c
+++ b/arch/arm6
ser access functions and get rid
of the VMCR structure entirely, which results in a rather nice diffstat
considering I've added quite a few lines of comments.
Based on v4.11-rc1.
Thanks,
-Christoffer
Christoffer Dall (5):
KVM: arm/arm64: Clarify GICC_PMR export format
KVM: arm64: v
ned-off-by: Christoffer Dall
---
arch/arm64/kvm/vgic-sys-reg-v3.c | 134 ++-
1 file changed, 75 insertions(+), 59 deletions(-)
diff --git a/arch/arm64/kvm/vgic-sys-reg-v3.c b/arch/arm64/kvm/vgic-sys-reg-v3.c
index 79f37e3..48848db 100644
--- a/arch/arm64/kvm/vg
rid of struct vmcr and its common
accessor functions.
Signed-off-by: Christoffer Dall
---
virt/kvm/arm/vgic/vgic-mmio-v2.c | 51 +---
virt/kvm/arm/vgic/vgic-mmio.c| 16 -
virt/kvm/arm/vgic/vgic-v2.c | 29 ---
virt/kvm/arm
We are exporting the format of the priority field as it's stored in the
GICH_VMCR.VMPriMask field using the lower five bits when accessing
register state using the GICC_PMR offset. This is unfortunate, but it's
ABI already, so we simply have to make it clear.
Signed-off-by: Christ
On Tue, Mar 21, 2017 at 10:29:08AM +, Marc Zyngier wrote:
> On 20/03/17 10:58, Christoffer Dall wrote:
> > From: Christoffer Dall
> >
> > We don't have to save/restore the VMCR on every entry to/from the guest,
> > since on GICv2 we can access the contr
On Tue, Mar 21, 2017 at 10:57:49AM +, Marc Zyngier wrote:
> On 20/03/17 10:58, Christoffer Dall wrote:
> > From: Shih-Wei Li
> >
> > We do not need to flush vgic states in each world switch unless
> > there is pending IRQ queued to the vgic's ap list. We can
On Tue, Mar 21, 2017 at 02:32:29PM +0800, gengdongjiu wrote:
>
>
> On 2017/3/20 23:08, James Morse wrote:
> > Hi Dongjiu Geng,
> >
> > On 20/03/17 13:58, Marc Zyngier wrote:
> >> On 20/03/17 12:28, gengdongjiu wrote:
> >>> On 2017/3/20 19:24, Marc Zyngier wrote:
> Please include James Morse
On Tue, Mar 21, 2017 at 11:36:19AM +, Marc Zyngier wrote:
> On 20/03/17 10:58, Christoffer Dall wrote:
> > From: Christoffer Dall
> >
> > Since we always read back the LRs that we wrote to the guest and the
> > MISR and EISR registers simply provide a summary of t
On Tue, Mar 21, 2017 at 12:05:30PM +, Marc Zyngier wrote:
> On 20/03/17 10:58, Christoffer Dall wrote:
> > Implement early initialization for both the distributor and the CPU
> > interfaces. The basic idea is that even though the VGIC is not
> > functional or not requ
On Tue, Mar 21, 2017 at 12:08:15PM +, Marc Zyngier wrote:
> On 20/03/17 10:58, Christoffer Dall wrote:
> > Now when we do an early init of the static parts of the VGIC data
> > structures, we can do things like checking if the AP lists are empty
> > directly without havin
On Tue, Mar 21, 2017 at 01:26:52PM +, Marc Zyngier wrote:
> On 21/03/17 12:26, Christoffer Dall wrote:
> > On Tue, Mar 21, 2017 at 11:36:19AM +, Marc Zyngier wrote:
> >> On 20/03/17 10:58, Christoffer Dall wrote:
> >>> From: Christoffer Dall
> >>&g
On Tue, Mar 21, 2017 at 01:29:06PM +, Marc Zyngier wrote:
> On 20/03/17 10:58, Christoffer Dall wrote:
> > There is no need to call any functions to fold LRs when we don't use any
> > LRs and we don't need to mess with overflow flags, take spinlocks, or
> > prun
On Tue, Mar 21, 2017 at 02:36:00PM +, Marc Zyngier wrote:
> On 21/03/17 11:05, Christoffer Dall wrote:
> > There is no common code in the VGIC that uses the VMCR, so we have no
> > use of the intermediate architecture-agnostic representation of the VMCR
> > and might a
On Tue, Mar 21, 2017 at 8:11 PM, James Morse wrote:
> Hi Christoffer,
>
> On 21/03/17 11:34, Christoffer Dall wrote:
> > On Tue, Mar 21, 2017 at 02:32:29PM +0800, gengdongjiu wrote:
> >> On 2017/3/20 23:08, James Morse wrote:
> >>>>>> On 20/03/17 07
[resending as clear text - I thought GMail supported that - sorry]
On Tue, Mar 21, 2017 at 07:11:44PM +, James Morse wrote:
> Hi Christoffer,
>
> On 21/03/17 11:34, Christoffer Dall wrote:
> > On Tue, Mar 21, 2017 at 02:32:29PM +0800, gengdongjiu wrote:
> >> On 2017
-off-by: Christoffer Dall
---
Documentation/virtual/kvm/devices/arm-vgic.txt | 6 ++
include/linux/irqchip/arm-gic.h| 3 +++
virt/kvm/arm/vgic/vgic-mmio-v2.c | 20 ++--
virt/kvm/arm/vgic/vgic-v2.c| 8
virt/kvm/arm
check additional initialization flags to ensure
they don't look at uninitialized data structures.
Acked-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
virt/kvm/arm/vgic/vgic-init.c | 96 +--
1 file changed, 56 insertions(+), 40 deletions(-)
di
: Christoffer Dall
---
Changes since v1:
- Moved note about checking list_empty to other patch commit message
- Removed check in both sync/flush in this patch
virt/kvm/arm/vgic/vgic.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
index
tomic read (uses READ_ONCE) and can
therefore check if a list is empty or not without the need to take the
spinlock protecting the list.
Signed-off-by: Shih-Wei Li
Signed-off-by: Christoffer Dall
---
Changes since v1:
- Added comment in kvm_vgic_flush_hwstate
virt/kvm/arm/vgic/vgic.c
From: Christoffer Dall
We don't have to save/restore the VMCR on every entry to/from the guest,
since on GICv2 we can access the control interface from EL1 and on VHE
systems with GICv3 we can access the control interface from KVM running
in EL2.
GICv3 systems without VHE become the rare
der-X.
Changelogs are in the patches.
Patches also available on:
git://git.kernel.org/pub/scm/linux/kernel/git/cdall/linux.git gic-optimize-v2
Thanks,
-Christoffer
Christoffer Dall (9):
KVM: arm/arm64: vgic: Defer touching GICH_VMCR to vcpu_load/put
KVM: arm/arm64: vgic: Get rid of live_lrs
logic to only setting the underflow
interrupt when we actually run out of LRs.
As it turns out, this allows us to further simplify the handling in
vgic_sync_hwstate in later patches.
Signed-off-by: Christoffer Dall
---
Changes since v1:
- New patch
virt/kvm/arm/vgic/vgic.c | 10 ++
1
From: Christoffer Dall
Now when we don't look at the MISR and EISR values anymore, we can get
rid of the logic to save them in the GIC save/restore code.
Acked-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
virt/kvm/arm/hyp/vgic-v2-sr.c
pty or not without the need to take the
spinlock protecting the list.
Signed-off-by: Christoffer Dall
---
Changes since v1:
- Moved clearing used_lrs into fold_lr_state
- Moved hunk that removes check for vgic_initialized into previous
patch
virt/kvm/arm/vgic/vgic-v2.c | 7 +--
virt/kv
From: Christoffer Dall
We don't use these fields anymore so let's nuke them completely.
Acked-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
include/kvm/arm_vgic.h| 4
virt/kvm/arm/hyp/vgic-v2-sr.c | 2 --
virt/kvm/arm/hyp/vgic-v3-sr.c | 2 --
3 files changed, 8
From: Christoffer Dall
There is no need to calculate and maintain live_lrs when we always
populate the lowest numbered LRs first on every entry and clear all LRs
on every exit.
Acked-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
include/kvm/arm_vgic.h| 2 --
virt/kvm/arm/hyp
From: Christoffer Dall
Since we always read back the LRs that we wrote to the guest and the
MISR and EISR registers simply provide a summary of the configuration of
the bits in the LRs, there is really no need to read back those status
registers and process them. We can might as well just
Hi Marc,
On Tue, Mar 21, 2017 at 07:20:30PM +, Marc Zyngier wrote:
> As noticed by RMK in this thread[1], the hyp-stub API on 32bit ARM
> could do with some TLC (it cannot perform a soft-restart at HYP, and
> has holes in the hyp-stub support in a number of places). In general,
> it would be
On Wed, Mar 22, 2017 at 04:14:44PM +, Marc Zyngier wrote:
> Hi Christoffer,
>
> On 22/03/17 13:37, Christoffer Dall wrote:
> > Hi Marc,
> >
> >
> > On Tue, Mar 21, 2017 at 07:20:30PM +, Marc Zyngier wrote:
> >> As noticed by RMK in thi
On Thu, Mar 23, 2017 at 10:53:04AM +, Marc Zyngier wrote:
> On 22/03/17 17:27, Christoffer Dall wrote:
> > On Wed, Mar 22, 2017 at 04:14:44PM +, Marc Zyngier wrote:
> >> Hi Christoffer,
> >>
> >> On 22/03/17 13:37, Christoffer Dall wrote:
> >&g
On Thu, Mar 23, 2017 at 03:16:49PM +, Marc Zyngier wrote:
> On 23/03/17 14:39, Christoffer Dall wrote:
> > On Thu, Mar 23, 2017 at 10:53:04AM +, Marc Zyngier wrote:
> >> On 22/03/17 17:27, Christoffer Dall wrote:
> >>>
> >>> I don't think ther
On Tue, Mar 21, 2017 at 07:20:58PM +, Marc Zyngier wrote:
> In order to help people understanding the hyp-stub API that exists
> between the host kernel and the hypervisor mode (whether a hypervisor
> has been installed or not), let's document said API.
>
> As with any form of documentation, I
On Tue, Mar 21, 2017 at 07:20:35PM +, Marc Zyngier wrote:
> In order to restore HYP mode to its original condition, KVM currently
> implements __kvm_hyp_reset(). As we're moving towards a hyp-stub
> defined API, it becomes necessary to implement HVC_RESET_VECTORS.
>
> This patch adds the HVC_R
On Tue, Mar 21, 2017 at 07:20:49PM +, Marc Zyngier wrote:
> We now have a full hyp-stub implementation in the KVM init code,
> but the main KVM code only supports HVC_GET_VECTORS, which is not
> enough.
>
> Instead of reinventing the wheel, let's reuse the init implementation
> by branching to
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