are always written with 1, not 0.
This patch only addresses CPTR_EL2. Initialisation of other system
registers may still need review.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/include/asm/kvm_arm.h |1 +
arch/arm64/kvm/hyp/switch.c |8 ++--
2 files chan
. In particular,
the layout and definition of CPTR_EL2 are changed by enabling VHE
so that they resemble CPACR_EL1, so existing code to initialise
CPTR_EL2 becomes architecturally wrong in this case.
This patch simply skips the affected initialisation code in the
non-VHE case.
Signed-off-by: Dave Martin
On Tue, Aug 15, 2017 at 06:44:45PM +0100, Ard Biesheuvel wrote:
> On 9 August 2017 at 13:05, Dave Martin <dave.mar...@arm.com> wrote:
> > The EFI runtime services ABI allows EFI to make free use of the
> > FPSIMD registers during EFI runtime service calls, subject t
On Wed, Aug 16, 2017 at 12:10:53PM +0100, Marc Zyngier wrote:
> On 16/08/17 11:54, Dave Martin wrote:
> > On Tue, Aug 15, 2017 at 05:37:55PM +0100, Marc Zyngier wrote:
> >> On 09/08/17 13:05, Dave Martin wrote:
[...]
> >>> + if (id == SYS_ID_AA64PFR0_EL1) {
>
On Tue, Aug 15, 2017 at 06:31:05PM +0100, Ard Biesheuvel wrote:
> Hi Dave,
>
> On 9 August 2017 at 13:05, Dave Martin <dave.mar...@arm.com> wrote:
> > This patch adds the core support for switching and managing the SVE
> > architectural state of user tasks.
> >
On Tue, Aug 15, 2017 at 05:37:55PM +0100, Marc Zyngier wrote:
> On 09/08/17 13:05, Dave Martin wrote:
> > KVM guests cannot currently use SVE, because SVE is always
> > configured to trap to EL2.
> >
> > However, a guest that sees SVE reported as present in
> >
On Wed, Aug 16, 2017 at 12:20:41PM +0100, Marc Zyngier wrote:
> On 16/08/17 11:50, Dave Martin wrote:
> > On Tue, Aug 15, 2017 at 05:33:15PM +0100, Marc Zyngier wrote:
> >> On 09/08/17 13:05, Dave Martin wrote:
> >>> Until KVM has full SVE support, guests must not b
On Tue, Aug 15, 2017 at 05:33:15PM +0100, Marc Zyngier wrote:
> On 09/08/17 13:05, Dave Martin wrote:
> > Until KVM has full SVE support, guests must not be allowed to
> > execute SVE instructions.
> >
> > This patch enables the necessary traps, and also ensures that
On Fri, Aug 11, 2017 at 08:46:28AM +0100, Yao Qi wrote:
> Hi Mark,
>
> On 19/07/17 17:01, Mark Rutland wrote:
> >+#define HWCAP_APIA (1 << 16)
>
> Can you rename it to HWCAP_ARM64_APIA or HWCAP_ARM_APIA? When we
> use it in user space, at least in GDB, we usually do this,
>
> #ifndef
On Wed, Aug 16, 2017 at 06:48:01PM +0100, Suzuki K Poulose wrote:
> On 09/08/17 13:05, Dave Martin wrote:
> >[This sender failed our fraud detection checks and may not be who they
> >appear to be. Learn about spoofing at http://aka.ms/LearnAboutSpoofing]
Any idea what this is ^
On Thu, Aug 17, 2017 at 09:45:51AM +0100, Marc Zyngier wrote:
> On 16/08/17 21:32, Dave Martin wrote:
> > On Wed, Aug 16, 2017 at 12:10:38PM +0100, Marc Zyngier wrote:
> >> On 09/08/17 13:05, Dave Martin wrote:
> >>> Currently, a guest kernel sees the true CPU fea
On Wed, Aug 16, 2017 at 06:53:07PM +0100, Suzuki K Poulose wrote:
> On 09/08/17 13:05, Dave Martin wrote:
> >[This sender failed our fraud detection checks and may not be who they
> >appear to be. Learn about spoofing at http://aka.ms/LearnAboutSpoofing]
> >
> >T
On Wed, Jul 19, 2017 at 05:01:21PM +0100, Mark Rutland wrote:
> This series adds support for the ARMv8.3 pointer authentication extension.
>
> Since RFC [1]:
> * Make the KVM context switch (semi-lazy)
> * Rebase to v4.13-rc1
> * Improve pointer authentication documentation
> * Add hwcap
t;?
I'm not sure of the history here.
> Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
> Cc: Catalin Marinas <catalin.mari...@arm.com>
> Cc: Dave Martin <dave.mar...@arm.com>
> Cc: Suzuki K Poulose <suzuki.poul...@arm.com>
> Cc: Will De
On Mon, Apr 03, 2017 at 04:19:23PM +0100, Mark Rutland wrote:
> When pointer authentication is in use, data/instruction pointers have a
> number of PAC bits inserted into them. The number and position of these
> bits depends on the configured TCR_ELx.TxSZ and whether tagging is
> enabled. ARMv8.3
On Tue, Jul 25, 2017 at 03:59:04PM +0100, Mark Rutland wrote:
> On Tue, Jul 25, 2017 at 01:11:48PM +0100, Dave Martin wrote:
> > On Mon, Apr 03, 2017 at 04:19:23PM +0100, Mark Rutland wrote:
> > > +/*
> > > + * The pointer bits used by a pointer authentication code.
On Wed, Jul 19, 2017 at 05:01:28PM +0100, Mark Rutland wrote:
> This patch adds basic support for pointer authentication, allowing
> userspace to make use of APIAKey. The kernel maintains an APIAKey value
> for each process (shared by all threads within), which is initialised to
> a random value
On Mon, May 15, 2017 at 06:43:55PM +0100, James Morse wrote:
> The Software Delegated Exception Interface (SDEI) is an ARM standard
> for registering callbacks from the platform firmware into the OS.
> This is typically used to implement RAS notifications.
>
> Add the code for detecting the SDEI
On Wed, Jul 19, 2017 at 05:01:27PM +0100, Mark Rutland wrote:
> To allow EL0 (and/or EL1) to use pointer authentication functionality,
> we must ensure that pointer authentication instructions and accesses to
> pointer authentication keys are not trapped to EL2 (where we will not be
> able to
The SVE architecture adds some system registers, ID register fields
and a dedicated ESR exception class.
This patch adds the appropriate definitions that will be needed by
the kernel.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/include/asm/esr.h | 3 ++-
arch
functionality has only been performed on
the model.
Regression testing using LTP is under way and has also been completed on
previous versions of this series.
Series summary:
* Patches 1-5 contain some individual bits of preparatory spadework,
which are indirectly related to SVE.
Dave Martin (5
. This
should have no impact on behaviour.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/kernel/fpsimd.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 138fcfa..9c1f268e 100644
---
rectories explicitly, which
is ideal here.
This patch ports register_insn_emulation_sysctl() over to the
register_sysctl() interface and removes the redundant ctl_table for
"abi".
Signed-off-by: Dave Martin <dave.mar...@arm.com>
[1] fea478d4101a (sysctl: Add register_sysctl for nor
for AArch32: however,
these could be handled in a similar way in future, as necessary.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/kvm/hyp/switch.c | 6 ++
arch/arm64/kvm/sys_regs.c | 224 +++-
2 files changed, 185 insertions(
a get_size() implementation.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
fs/binfmt_elf.c| 6 ++---
include/linux/regset.h | 67 --
2 files changed, 63 insertions(+), 10 deletions(-)
diff --git a/fs/binfmt_elf.c b/fs/binfmt_elf.c
the vector length.
Setting of the vector length is done as part of register restore.
Since people building kernels may not all get an SVE-enabled
toolchain for a while, this patch uses macros that generate
explicit opcodes in place of assembler mnemonics.
Signed-off-by: Dave Martin <dave.mar...@arm.
in a later patch, once
SVE support is complete enough to be enabled safely.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/Kconfig | 11 +++
arch/arm64/include/asm/cpufeature.h | 5 +
2 files changed, 16 insertions(+)
diff --git a/arch/arm64/K
: this is an
obvious slow path and a hint that we are running a new binary that
may not use SVE.
Code is added to sync data between thread.fpsimd_state and
thread.sve_state whenever enabling/disabling SVE, in a manner
consistent with the SVE architectural programmer's model.
Signed-off-by: Dave Martin
length, it is not possible
to define a fixed C struct to describe all the registers. Instead,
Macros are defined in sigcontext.h to facilitate access to the
parts of the structure.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/include/uapi/asm/sigcontext.h
set by ZCR_EL2.)
In advance of full SVE support being implemented for userspace, it
also necessary to ensure that SVE traps from EL0 are enabled.
This patch makes the appropriate changes to the primary and
secondary CPU initialisation code.
Signed-off-by: Dave Martin <dave.mar...@arm.
flag
TIF_SVE_VL_INHERIT to control whether to inherit or reset the
vector length. Currently these are inactive. Subsequent patches
will provide the capability to configure them.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/include/asm/processor.h | 1 +
arch/arm64/inclu
that are not a power of two. To handle
this, logic is added to check a requested vector length against a
possibly sparse bitmap of available vector lengths at runtime, so
that the best supported value can be chosen.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/include/asm/fpsimd.h
of the
SVE state, this flush is hoisted before the sigframe layout phase,
so that the layout and population phases see a consistent view of
the thread.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/include/asm/fpsimd.h | 1 +
arch/arm64/kernel/fpsimd.c | 23 --
arch
() remains hardwired to false.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/include/asm/cpu.h| 4 ++
arch/arm64/include/asm/cpufeature.h | 28 ++
arch/arm64/include/asm/fpsimd.h | 10
arch/arm64/kernel/cpufeature.c | 48
.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/kernel/fpsimd.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 955c873..b7fb836 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/
instructions.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/include/asm/fpsimd.h| 14
arch/arm64/include/asm/processor.h | 4
arch/arm64/kernel/fpsimd.c | 46 ++
include/uapi/linux/prctl.h | 4
, which the recipient can use to
figure out the content, size and layout of the reset of the regset.
Accessor macros are defined to allow the vector-length-dependent
parts of the regset to be manipulated.
Signed-off-by: Alan Hayward <alan.hayw...@arm.com>
Signed-off-by: Dave Martin <dave.mar..
as
reading as zero, which is consistent with SVE not being
implemented.
This is a temporary measure, and will be removed in a later series
when full KVM support for SVE is implemented.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/kvm/sys_regs.c | 14 +-
1 file c
running on hardware that supports SVE, this enables runtime
kernel support for SVE, and allows user tasks to execute SVE
instructions and make of the of the SVE-specific user/kernel
interface extensions implemented by this series.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch
s internal SIGFRAME_MAXSZ is supposed to sanity-check
against generting frames that we consider _impossibly_ large. In
this case, SIGSTKSZ is returned as a "reasonable guess that is at
least bigger than MINSIGSTKSZ" and we WARN().
Signed-off-by: Dave Martin <dave.mar...@arm.com>
-
This patch adds basic documentation of the user/kernel interface
provided by the for SVE.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
Documentation/arm64/sve.txt | 454
1 file changed, 454 insertions(+)
create mode 100644 Documentation
existing
process.
The intended usage model is that if userspace is known to be fully
SVE-tolerant (or a developer is curious to find out) then init
scripts can crank this up during startup.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/kernel/fpsimd.
Until KVM has full SVE support, guests must not be allowed to
execute SVE instructions.
This patch enables the necessary traps, and also ensures that the
traps are disabled again on exit from the guest so that the host
can still use SVE if it wants to.
Signed-off-by: Dave Martin <dave.
must be saved and restored too.
No attempt is made to restore the restore the vector length after
a call, for now. It is deemed rather insane for EFI to change it,
and contemporary EFI implementations certainly won't.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/kernel/fp
When trapping forbidden attempts by a guest to use SVE, we want the
guest to see a trap consistent with SVE not being implemented.
This patch injects an undefined instruction exception into the
guest in response to such an exception.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
vector length: this
determines the maximum size of SVE context block that can be
observed in any signal frame for the lifetime of the process.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
---
arch/arm64/kernel/signal.c | 15 +++
1 file changed, 11 insertions(+), 4 del
On Wed, Aug 16, 2017 at 12:10:38PM +0100, Marc Zyngier wrote:
> On 09/08/17 13:05, Dave Martin wrote:
> > Currently, a guest kernel sees the true CPU feature registers
> > (ID_*_EL1) when it reads them using MRS instructions. This means
> > that the guest will observe feat
On Tue, Aug 22, 2017 at 05:22:11PM +0100, Alex Bennée wrote:
>
> Dave Martin <dave.mar...@arm.com> writes:
>
> > It's desirable to be able to reset the vector length to some sane
> > default for new processes, since the new binary and its libraries
> > proc
On Tue, Aug 22, 2017 at 05:21:19PM +0100, Alex Bennée wrote:
>
> Dave Martin <dave.mar...@arm.com> writes:
[...]
> > --- a/arch/arm64/include/asm/processor.h
> > +++ b/arch/arm64/include/asm/processor.h
> > @@ -85,6 +85,8 @@ struct thread_struct {
> >
On Tue, Aug 22, 2017 at 04:03:20PM +0100, Alex Bennée wrote:
>
> Dave Martin <dave.mar...@arm.com> writes:
>
> > On Tue, Aug 22, 2017 at 02:53:49PM +0100, Alex Bennée wrote:
[...]
> >> +
> >> +#define SVE_VQ_BITS 128 /* 128 bits in one
On Tue, Aug 22, 2017 at 02:53:49PM +0100, Alex Bennée wrote:
>
> Dave Martin <dave.mar...@arm.com> writes:
>
> > On Tue, Aug 22, 2017 at 11:22:44AM +0100, Alex Bennée wrote:
> >>
> >> Dave Martin <dave.mar...@arm.com> writes:
[...]
> >&
On Tue, Aug 22, 2017 at 04:04:28PM +0100, Alex Bennée wrote:
>
> Dave Martin <dave.mar...@arm.com> writes:
>
> > To enable the kernel to use SVE, all SVE traps from EL1 must be
> > disabled. To take maximum advantage of the hardware, the full
> > available vecto
On Wed, Aug 23, 2017 at 10:38:51AM +0100, Alex Bennée wrote:
>
> Dave Martin <dave.mar...@arm.com> writes:
>
> > This patch implements support for saving and restoring the SVE
> > registers around signals.
> >
> > A fixed-size header struct sve_context is
On Tue, Aug 15, 2017 at 06:31:05PM +0100, Ard Biesheuvel wrote:
> Hi Dave,
>
> On 9 August 2017 at 13:05, Dave Martin <dave.mar...@arm.com> wrote:
> > This patch adds the core support for switching and managing the SVE
> > architectural state of user tas
gt; > possibly sparse bitmap of available vector lengths at runtime, so
> > that the best supported value can be chosen.
> >
> > Signed-off-by: Dave Martin <dave.mar...@arm.com>
> > Cc: Alex Bennée <alex.ben...@linaro.org>
>
> Can this be merged with
On Wed, Sep 13, 2017 at 06:32:06AM -0700, Catalin Marinas wrote:
> On Thu, Aug 31, 2017 at 06:00:42PM +0100, Dave P Martin wrote:
> > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> > index 877d42f..dd22ef2 100644
> > --- a/arch/arm64/mm/proc.S
> > +++ b/arch/arm64/mm/proc.S
> > @@
On Wed, Sep 20, 2017 at 06:08:21PM +, Alan Hayward wrote:
>
> > On 20 Sep 2017, at 12:09, Dave Martin <dave.mar...@foss.arm.com> wrote:
[...]
> >> Given, sve_set_vector_length is called when setting the vector length in
> >> PTRACE_SETREGSET, it looks to
On Wed, Sep 13, 2017 at 06:36:18AM -0700, Catalin Marinas wrote:
> On Thu, Aug 31, 2017 at 06:00:41PM +0100, Dave P Martin wrote:
> > +/*
> > + * The SVE architecture leaves space for future expansion of the
> > + * vector length beyond its initial architectural limit of 2048 bits
> > + * (16
On Wed, Sep 13, 2017 at 03:21:29PM -0700, Catalin Marinas wrote:
> On Wed, Sep 13, 2017 at 08:17:07PM +0100, Dave P Martin wrote:
> > On Wed, Sep 13, 2017 at 10:26:05AM -0700, Catalin Marinas wrote:
> > > On Thu, Aug 31, 2017 at 06:00:43PM +0100, Dave P Martin wrote:
> > > > +/*
> > > > + *
On Wed, Sep 13, 2017 at 07:33:25AM -0700, Catalin Marinas wrote:
> On Thu, Aug 31, 2017 at 06:00:43PM +0100, Dave P Martin wrote:
> > +/*
> > + * Handle SVE state across fork():
> > + *
> > + * dst and src must not end up with aliases of the same sve_state.
> > + * Because a task cannot fork
On Wed, Sep 13, 2017 at 03:37:42PM +0100, Alex Bennée wrote:
>
> Dave Martin <dave.mar...@arm.com> writes:
[...]
> > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
> > index 945e79c..35a90b8 100644
> > --- a/arch/arm64/kvm/hyp/switch.
On Wed, Sep 20, 2017 at 10:59:55AM +, Alan Hayward wrote:
> (Resending without disclaimer)
>
> > On 31 Aug 2017, at 18:00, Dave Martin <dave.mar...@arm.com> wrote:
>
> >
> > +int sve_set_vector_length(struct task_struct *task,
> > +
On Wed, Sep 13, 2017 at 08:21:11PM +0100, Dave Martin wrote:
> On Wed, Sep 13, 2017 at 06:32:06AM -0700, Catalin Marinas wrote:
> > On Thu, Aug 31, 2017 at 06:00:42PM +0100, Dave P Martin wrote:
> > > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> > > in
On Fri, Oct 06, 2017 at 04:43:43PM +0100, Szabolcs Nagy wrote:
> On 31/08/17 18:00, Dave Martin wrote:
> > +9. System runtime configuration
> > +
> > +
> > +* To mitigate the ABI impact of expansion of the signal frame, a policy
&
On Fri, Oct 06, 2017 at 02:36:40PM +0100, Catalin Marinas wrote:
> On Fri, Oct 06, 2017 at 02:10:09PM +0100, Dave P Martin wrote:
> > On Thu, Oct 05, 2017 at 12:28:35PM +0100, Catalin Marinas wrote:
> > > On Tue, Oct 03, 2017 at 12:33:03PM +0100, Dave P Martin wrote:
> > > > TIF_FOREIGN_FPSTATE's
, which the recipient can use to
figure out the content, size and layout of the reset of the regset.
Accessor macros are defined to allow the vector-length-dependent
parts of the regset to be manipulated.
Signed-off-by: Alan Hayward <alan.hayw...@arm.com>
Signed-off-by: Dave Martin <dave.mar..
flag
TIF_SVE_VL_INHERIT to control whether to inherit or reset the
vector length. Currently these are inactive. Subsequent patches
will provide the capability to configure them.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
---
arch/a
The SVE architecture adds some system registers, ID register fields
and a dedicated ESR exception class.
This patch adds the appropriate definitions that will be needed by
the kernel.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org&g
for AArch32: however,
these could be handled in a similar way in future, as necessary.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Cc: Marc Zyngier <marc.zyng...@arm.com>
---
arch/arm64/include/asm/sysreg.h | 3 +
arch/arm64/kvm/hyp/switch.c | 6 +
arch/arm64/kvm/sys_regs.c
s internal SIGFRAME_MAXSZ is supposed to sanity-check
against generting frames that we consider _impossibly_ large. In
this case, SIGSTKSZ is returned as a "reasonable guess that is at
least bigger than MINSIGSTKSZ" and we WARN().
Signed-off-by: Dave Martin <dave.mar...@arm.com>
-
: this is an
obvious slow path and a hint that we are running a new binary that
may not use SVE.
Code is added to sync data between thread.fpsimd_state and
thread.sve_state whenever enabling/disabling SVE, in a manner
consistent with the SVE architectural programmer's model.
Signed-off-by: Dave Martin
instructions.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Cc: Alex Bennée <alex.ben...@linaro.org>
---
Dropped Alex Bennée's Reviewed-by, since there are non-trivial changes
since v2.
Changes since v2
Bug fixes:
* Remove preempt_disable() from sve_set_current
When trapping forbidden attempts by a guest to use SVE, we want the
guest to see a trap consistent with SVE not being implemented.
This patch injects an undefined instruction exception into the
guest in response to such an exception.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Re
(). This
should be fine, since cpu_pm_enter() is supposed to be called only
with interrupts disabled.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org&g
must be saved and restored too.
No attempt is made to restore the restore the vector length after
a call, for now. It is deemed rather insane for EFI to change it,
and contemporary EFI implementations certainly won't.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Reviewed-by: Alex
.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
---
arch/arm64/kernel/fpsimd.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kernel/fps
() remains hardwired to false.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Cc: Alex Bennée <alex.ben...@linaro.org>
Cc: Suzuki K Poulose <suzuki.poul...@arm.com>
---
Dropped Alex Bennée's Reviewed-by, since there is new logic in this
patch.
Changes since v2
as
reading as zero, which is consistent with SVE not being
implemented.
This is a temporary measure, and will be removed in a later series
when full KVM support for SVE is implemented.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Cc:
running on hardware that supports SVE, this enables runtime
kernel support for SVE, and allows user tasks to execute SVE
instructions and make of the of the SVE-specific user/kernel
interface extensions implemented by this series.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Cc: Suzuki K P
vector length: this
determines the maximum size of SVE context block that can be
observed in any signal frame for the lifetime of the process.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Alex Bennée <alex.ben...@linaro.org&g
This patch adds basic documentation of the user/kernel interface
provided by the for SVE.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Cc: Alex Bennée <alex.ben...@linaro.org>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Alan Hayward <alan.hayw...@arm.com>
the vector length.
Setting of the vector length is done as part of register restore.
Since people building kernels may not all get an SVE-enabled
toolchain for a while, this patch uses macros that generate
explicit opcodes in place of assembler mnemonics.
Signed-off-by: Dave Martin <dave.mar...@arm.
in a later patch, once
SVE support is complete enough to be enabled safely.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
---
arch/arm64/Kconfig | 11 +++
arch/arm64/include/asm/cpufeature.h | 5 +
2 f
length, it is not possible
to define a fixed C struct to describe all the registers. Instead,
Macros are defined in sigcontext.h to facilitate access to the
parts of the structure.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Cc: Alex Bennée <alex.ben...@linaro.org>
---
Chan
that are not a power of two. To handle
this, logic is added to check a requested vector length against a
possibly sparse bitmap of available vector lengths at runtime, so
that the best supported value can be chosen.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Cc: Alex Bennée <alex.ben...@l
. This
should have no impact on behaviour.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
---
arch/arm64/kernel/fpsimd.c | 6 ++
1 file changed, 2 insertions(+), 4 deleti
the limit set by ZCR_EL2.)
Traps from EL0 to EL1 are also left enabled by virtue of setting
the relevant CPACR bit at its default (RES0) value.
This patch makes the appropriate changes to the primary and
secondary CPU initialisation code.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Cc: C
existing
process.
The intended usage model is that if userspace is known to be fully
SVE-tolerant (or a developer is curious to find out) then init
scripts can crank this up during startup.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Reviewed-by: Alex Bennée <alex.ben...@l
a get_size() implementation.
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
---
fs/binfmt_elf.c| 6 ++---
include/linux/regset.h | 67 --
2 files changed, 63 insertions(+), 10 deleti
dependency.
This will aid bisection of the patches implementing support for the
ARM Scalable Vector Extension (SVE).
Signed-off-by: Dave Martin <dave.mar...@arm.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
---
arch/arm64/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
yet, testing of the SVE functionality has only been
performed on the model.
Regression testing of v3 is under way.
Series summary:
* Patches 1-5 contain some individual bits of preparatory spadework,
which are indirectly related to SVE.
Dave Martin (5):
regset: Add support for dynamically
On Thu, Oct 05, 2017 at 12:04:12PM +0100, Suzuki K Poulose wrote:
> On 05/10/17 11:47, Dave Martin wrote:
[...]
> >>>On Thu, Aug 31, 2017 at 06:00:42PM +0100, Dave P Martin wrote:
> >>>>diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> >>>>i
cture permits, but does not require, implementations
> > > > to support vector lengths that are not a power of two. To handle
> > > > this, logic is added to check a requested vector length against a
> > > > possibly sparse bitmap of available vector lengths at runt
On Thu, Oct 05, 2017 at 05:39:24PM +0100, Szabolcs Nagy wrote:
> On 31/08/17 18:00, Dave Martin wrote:
[...]
> > + PR_SVE_SET_VL_ONEXEC
> > +
> > + Defer the requested vector length change until the next execve().
> > + This allows launching of a new prog
On Thu, Oct 05, 2017 at 05:53:34PM +0100, Catalin Marinas wrote:
> On Thu, Oct 05, 2017 at 05:42:29PM +0100, Dave P Martin wrote:
> > On Wed, Sep 13, 2017 at 03:11:23PM -0700, Catalin Marinas wrote:
> > > On Wed, Sep 13, 2017 at 08:06:12PM +0100, Dave P Martin wrote:
> > > > On Wed, Sep 13, 2017
On Mon, Oct 16, 2017 at 05:27:59PM +0100, Suzuki K Poulose wrote:
> On 16/10/17 16:46, Dave Martin wrote:
> >On Thu, Oct 12, 2017 at 01:56:51PM +0100, Suzuki K Poulose wrote:
> >>On 10/10/17 19:38, Dave Martin wrote:
[...]
> >>>@@ -670,6 +689,14 @@ vo
On Thu, Oct 12, 2017 at 01:56:51PM +0100, Suzuki K Poulose wrote:
> On 10/10/17 19:38, Dave Martin wrote:
> >This patch uses the cpufeatures framework to determine common SVE
> >capabilities and vector lengths, and configures the runtime SVE
> >support code appropri
On Mon, Oct 16, 2017 at 05:47:16PM +0100, Suzuki K Poulose wrote:
> On 16/10/17 17:44, Dave Martin wrote:
> >On Mon, Oct 16, 2017 at 05:27:59PM +0100, Suzuki K Poulose wrote:
> >>On 16/10/17 16:46, Dave Martin wrote:
> >>>On Thu, Oct 12, 2017 at 01:56:51PM
On Tue, Oct 17, 2017 at 06:58:16AM -0700, Christoffer Dall wrote:
> On Tue, Oct 10, 2017 at 07:38:41PM +0100, Dave Martin wrote:
> > KVM guests cannot currently use SVE, because SVE is always
> > configured to trap to EL2.
> >
> > However, a guest that s
On Tue, Oct 17, 2017 at 01:50:24PM +0200, Christoffer Dall wrote:
> On Tue, Oct 10, 2017 at 07:38:39PM +0100, Dave Martin wrote:
> > Until KVM has full SVE support, guests must not be allowed to
> > execute SVE instructions.
> >
> > This patch enables the necess
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