Re: [RFC v2 06/10] KVM: arm/arm64: Update the physical timer interrupt level

On Wed, Feb 1, 2017 at 3:04 AM, Christoffer Dall <christoffer.d...@linaro.org> wrote: > On Sun, Jan 29, 2017 at 03:21:06PM +, Marc Zyngier wrote: >> On Fri, Jan 27 2017 at 01:04:56 AM, Jintack Lim <jint...@cs.columbia.edu> >> wrote: >> > Now that we main

[RFC v3 03/10] KVM: arm/arm64: Decouple kvm timer functions from virtual timer

Now that we have a separate structure for timer context, make functions generic so that they can work with any timer context, not just the virtual timer context. This does not change the virtual timer functionality. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Acked-by: Marc Z

[RFC v3 02/10] KVM: arm/arm64: Move cntvoff to each timer context

make sense. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/include/asm/kvm_host.h | 3 --- arch/arm/kvm/arm.c| 1 - arch/arm64/include/asm/kvm_host.h | 3 --- include/kvm/arm_arch_timer.h | 9 +++-- virt/kvm/arm/arch_timer.c

[RFC v3 10/10] KVM: arm/arm64: Emulate the EL1 phys timer registers

Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL. Now VMs are able to use the EL1 physical timer. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/kvm/sys_regs.c| 37 ++--- include/kvm/arm_arch_timer.h | 2 ++ vi

[RFC v3 04/10] KVM: arm/arm64: Add the EL1 physical timer context

Add the EL1 physical timer context. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- include/kvm/arm_arch_timer.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index f46fa3b..6445a3d 100644 --- a/inclu

[RFC v3 08/10] KVM: arm/arm64: Set up a background timer for the physical timer emulation

use the virtual timer since the physical timer is always not enabled. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- virt/kvm/arm/arch_timer.c | 25 - 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/virt/kvm/arm/arch_timer.c b/virt/k

[RFC v3 01/10] KVM: arm/arm64: Abstract virtual timer context into separate structure

Abstract virtual timer context into a separate structure and change all callers referring to timer registers, irq state and so on. No change in functionality. This is about to become very handy when adding the EL1 physical timer. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu>

[RFC v3 07/10] KVM: arm/arm64: Set a background timer to the earliest timer expiration

When scheduling a background timer, consider both of the virtual and physical timer and pick the earliest expiration time. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/kvm/arm.c| 3 ++- virt/kvm/arm/arch_timer.

[RFC v3 09/10] KVM: arm64: Add the EL1 physical timer access handler

KVM traps on the EL1 phys timer accesses from VMs, but it doesn't handle those traps. This results in terminating VMs. Instead, set a handler for the EL1 phys timer access, and inject an undefined exception as an intermediate step. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> ---

[RFC v3 00/10] Provide the EL1 physical timer to the VM

cal timer emulation on every entry to the VM and cancel it on exit. - Change timer_context structure to have cntvoff and restore enable field back to arch_timer_cpu structure Jintack Lim (10): KVM: arm/arm64: Abstract virtual timer context into separate structure KVM: arm/arm64: Move cntvoff to e

[RFC v3 05/10] KVM: arm/arm64: Initialize the emulated EL1 physical timer

Initialize the emulated EL1 physical timer with the default irq number. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/kvm/reset.c | 9 - arch/arm64/kvm/reset.c | 9 - include/kvm/arm_arch_timer.h | 3 ++- virt/kvm/arm/arch_timer.c

[RFC v3 06/10] KVM: arm/arm64: Update the physical timer interrupt level

Now that we maintain the EL1 physical timer register states of VMs, update the physical timer interrupt level along with the virtual one. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- virt/kvm/arm/arch_timer.c | 4 1 file changed, 4 insertions(+) diff --git a/virt/k

Re: [RFC v3 00/10] Provide the EL1 physical timer to the VM

On Thu, Feb 2, 2017 at 7:31 AM, Christoffer Dall <cd...@linaro.org> wrote: > Hi Jintack, > > On Wed, Feb 01, 2017 at 12:43:00PM -0500, Jintack Lim wrote: >> The ARM architecture defines the EL1 physical timer and the virtual timer, >> and it is reasonable for an OS to

Re: [RFC v3 00/10] Provide the EL1 physical timer to the VM

On Fri, Feb 3, 2017 at 7:33 AM, Christoffer Dall <cd...@linaro.org> wrote: > On Thu, Feb 02, 2017 at 09:51:13AM -0500, Jintack Lim wrote: >> On Thu, Feb 2, 2017 at 7:31 AM, Christoffer Dall <cd...@linaro.org> wrote: >> > Hi Jintack, >> > >> > On We

[RFC v4 07/10] KVM: arm/arm64: Set a background timer to the earliest timer expiration

When scheduling a background timer, consider both of the virtual and physical timer and pick the earliest expiration time. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm/kvm/arm.c| 3 ++-

[RFC v4 01/10] KVM: arm/arm64: Abstract virtual timer context into separate structure

Abstract virtual timer context into a separate structure and change all callers referring to timer registers, irq state and so on. No change in functionality. This is about to become very handy when adding the EL1 physical timer. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu>

[RFC v4 04/10] KVM: arm/arm64: Add the EL1 physical timer context

Add the EL1 physical timer context. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Acked-by: Christoffer Dall <christoffer.d...@linaro.org> --- include/kvm/arm_arch_timer.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_

[RFC v4 00/10] Provide the EL1 physical timer to the VM

and restore enable field back to arch_timer_cpu structure Jintack Lim (10): KVM: arm/arm64: Abstract virtual timer context into separate structure KVM: arm/arm64: Move cntvoff to each timer context KVM: arm/arm64: Decouple kvm timer functions from virtual timer KVM: arm/arm64: Add the

[RFC v4 09/10] KVM: arm64: Add the EL1 physical timer access handler

KVM traps on the EL1 phys timer accesses from VMs, but it doesn't handle those traps. This results in terminating VMs. Instead, set a handler for the EL1 phys timer access, and inject an undefined exception as an intermediate step. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Re

[RFC v4 06/10] KVM: arm/arm64: Update the physical timer interrupt level

Now that we maintain the EL1 physical timer register states of VMs, update the physical timer interrupt level along with the virtual one. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Acked-by: Christoffer Dall <christoffer.d...@linaro.org> --- virt/kvm/arm/arch_timer.c | 4

[RFC v4 03/10] KVM: arm/arm64: Decouple kvm timer functions from virtual timer

Now that we have a separate structure for timer context, make functions generic so that they can work with any timer context, not just the virtual timer context. This does not change the virtual timer functionality. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Acked-by: Marc Z

[RFC v4 08/10] KVM: arm/arm64: Set up a background timer for the physical timer emulation

use the virtual timer since the physical timer is always not enabled. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> --- virt/kvm/arm/arch_timer.c | 25 - 1 file changed, 24 insertions(+), 1 delet

[RFC v4 05/10] KVM: arm/arm64: Initialize the emulated EL1 physical timer

Initialize the emulated EL1 physical timer with the default irq number. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm/kvm/reset.c | 9 - arch/arm64/kvm/reset.c | 9 -

Re: [RFC v4 00/10] Provide the EL1 physical timer to the VM

On Fri, Feb 3, 2017 at 11:14 AM, Marc Zyngier <marc.zyng...@arm.com> wrote: > On 03/02/17 15:19, Jintack Lim wrote: >> The ARM architecture defines the EL1 physical timer and the virtual timer, >> and it is reasonable for an OS to expect to be able to access both. >&g

Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

Hi Marc, On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier <marc.zyng...@arm.com> wrote: > On Fri, Jan 27 2017 at 01:05:00 AM, Jintack Lim <jint...@cs.columbia.edu> > wrote: >> Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL. >> Now VMs are able

Re: [RFC v2 03/10] KVM: arm/arm64: Decouple kvm timer functions from virtual timer

On Sun, Jan 29, 2017 at 7:01 AM, Marc Zyngier <marc.zyng...@arm.com> wrote: > On Fri, Jan 27 2017 at 01:04:53 AM, Jintack Lim <jint...@cs.columbia.edu> > wrote: >> Now that we have a separate structure for timer context, make functions >> general so that they c

Re: [RFC v2 02/10] KVM: arm/arm64: Move cntvoff to each timer context

On Mon, Jan 30, 2017 at 9:51 AM, Marc Zyngier <marc.zyng...@arm.com> wrote: > On 30/01/17 14:45, Christoffer Dall wrote: >> On Sun, Jan 29, 2017 at 11:54:05AM +, Marc Zyngier wrote: >>> On Fri, Jan 27 2017 at 01:04:52 AM, Jintack Lim <jint...@cs.columbia.edu> &g

Re: [RFC v2 03/10] KVM: arm/arm64: Decouple kvm timer functions from virtual timer

Hi Christoffer, On Mon, Jan 30, 2017 at 9:49 AM, Christoffer Dall <christoffer.d...@linaro.org> wrote: > On Thu, Jan 26, 2017 at 08:04:53PM -0500, Jintack Lim wrote: >> Now that we have a separate structure for timer context, make functions >> general so that they can work w

Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

Hi Peter, On Mon, Jan 30, 2017 at 12:26 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 30 January 2017 at 17:08, Jintack Lim <jint...@cs.columbia.edu> wrote: >> On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier <marc.zyng...@arm.com> wrote: >>> Shouldn't

Re: [RFC v2 02/10] KVM: arm/arm64: Move cntvoff to each timer context

On Sun, Jan 29, 2017 at 6:54 AM, Marc Zyngier <marc.zyng...@arm.com> wrote: > On Fri, Jan 27 2017 at 01:04:52 AM, Jintack Lim <jint...@cs.columbia.edu> > wrote: >> Make cntvoff per each timer context. This is helpful to abstract kvm >> timer functions to w

Re: [RFC v2 02/10] KVM: arm/arm64: Move cntvoff to each timer context

On Mon, Jan 30, 2017 at 1:05 PM, Marc Zyngier <marc.zyng...@arm.com> wrote: > On 30/01/17 17:58, Jintack Lim wrote: >> On Sun, Jan 29, 2017 at 6:54 AM, Marc Zyngier <marc.zyng...@arm.com> wrote: >>> On Fri, Jan 27 2017 at 01:04:52 AM, Jintack Lim <jint...@cs.co

Re: [RFC v2 00/10] Provide the EL1 physical timer to the VM

Hi Marc, On Sun, Jan 29, 2017 at 10:55 AM, Marc Zyngier <marc.zyng...@arm.com> wrote: > Hi Jintack, > > On Fri, Jan 27 2017 at 01:04:50 AM, Jintack Lim <jint...@cs.columbia.edu> > wrote: >> The ARM architecture defines the EL1 physical timer and the virtual

[RFC v2 08/10] KVM: arm/arm64: Set up a background timer for the physical timer emulation

use the virtual timer since the physical timer is always not enabled. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- virt/kvm/arm/arch_timer.c | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/virt/kvm/arm/arch_timer.c b/virt/k

[RFC v2 02/10] KVM: arm/arm64: Move cntvoff to each timer context

make sense. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/include/asm/kvm_host.h | 6 +++--- arch/arm64/include/asm/kvm_host.h | 4 ++-- include/kvm/arm_arch_timer.h | 8 +++- virt/kvm/arm/arch_timer.c | 26 -- virt/kvm/arm/hyp

[RFC v2 05/10] KVM: arm/arm64: Initialize the emulated EL1 physical timer

Initialize the emulated EL1 physical timer with the default irq number. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/kvm/reset.c | 9 - arch/arm64/kvm/reset.c | 9 - include/kvm/arm_arch_timer.h | 3 ++- virt/kvm/arm/arch_timer.c

[RFC v2 03/10] KVM: arm/arm64: Decouple kvm timer functions from virtual timer

Now that we have a separate structure for timer context, make functions general so that they can work with any timer context, not just the virtual timer context. This does not change the virtual timer functionality. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/kvm

[RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL. Now VMs are able to use the EL1 physical timer. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/kvm/sys_regs.c| 32 +--- include/kvm/arm_arch_timer.h | 2 ++ virt/k

[RFC v2 09/10] KVM: arm64: Add the EL1 physical timer access handler

KVM traps on the EL1 phys timer accesses from VMs, but it doesn't handle those traps. This results in terminating VMs. Instead, set a handler for the EL1 phys timer access, and inject an undefined exception as an intermediate step. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> ---

[RFC v2 01/10] KVM: arm/arm64: Abstract virtual timer context into separate structure

Abstract virtual timer context into a separate structure and change all callers referring to timer registers, irq state and so on. No change in functionality. This is about to become very handy when adding the EL1 physical timer. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu>

[RFC v2 07/10] KVM: arm/arm64: Set a background timer to the earliest timer expiration

When scheduling a background timer, consider both of the virtual and physical timer and pick the earliest expiration time. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/kvm/arm.c| 3 ++- virt/kvm/arm/arch_timer.

[RFC v2 06/10] KVM: arm/arm64: Update the physical timer interrupt level

Now that we maintain the EL1 physical timer register states of VMs, update the physical timer interrupt level along with the virtual one. Note that the emulated EL1 physical timer is not mapped to any hardware timer, so we call a proper vgic function. Signed-off-by: Jintack Lim <j

[RFC v2 00/10] Provide the EL1 physical timer to the VM

cpu structure Jintack Lim (10): KVM: arm/arm64: Abstract virtual timer context into separate structure KVM: arm/arm64: Move cntvoff to each timer context KVM: arm/arm64: Decouple kvm timer functions from virtual timer KVM: arm/arm64: Add the EL1 physical timer context KVM: arm/arm64: Initial

Re: [RFC 00/55] Nested Virtualization on KVM/ARM

Hi Christoffer, On Wed, Feb 22, 2017 at 1:23 PM, Christoffer Dall <cd...@linaro.org> wrote: > Hi Jintack, > > > On Mon, Jan 09, 2017 at 01:23:56AM -0500, Jintack Lim wrote: > > Nested virtualization is the ability to run a virtual machine inside > another > >

Re: [RFC 00/55] Nested Virtualization on KVM/ARM

gt; On Mon, Jan 09, 2017 at 01:23:56AM -0500, Jintack Lim wrote: >> Nested virtualization is the ability to run a virtual machine inside another >> virtual machine. In other words, it’s about running a hypervisor (the guest >> hypervisor) on top of another hypervisor (the host hyp

Re: [RFC 0/8] Provide the EL1 physical timer to the VM

On Tue, Jan 17, 2017 at 12:09 PM, Marc Zyngier <marc.zyng...@arm.com> wrote: > On 26/12/16 17:11, Jintack Lim wrote: >> The ARM architecture defines the EL1 physical timer and the virtual >> timer, and it is reasonable for an OS to expect to be able to access >> both

[PATCH] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

guest OS to access physical timer. So, fix it. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/include/asm/kvm_timer.h | 33 +++ arch/arm64/include/asm/kvm_timer.h | 62 include/clocksource/arm_arch_timer.h | 6 ++--

[PATCH] arm64: head.S: Fix CNTHCTL_EL2 access on VHE system

e host kernel runs in EL2. It is a hypervisor's responsibility to configure them before entering a VM, which runs in EL0 and EL1. Second, EL0 accesses are configured in the later stage of boot process. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/kernel/head.S | 8

[PATCH] arm64: head.S: Fix CNTHCTL_EL2 access on VHE system

e host kernel runs in EL2. It is a hypervisor's responsibility to configure them before entering a VM, which runs in EL0 and EL1. Second, EL0 accesses are configured in the later stage of boot process. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/kernel/head.S | 8

Re: [PATCH] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

On Mon, Nov 28, 2016 at 1:39 PM, Marc Zyngier <marc.zyng...@arm.com> wrote: > On 28/11/16 17:43, Marc Zyngier wrote: >> Hi Jintack, Hi Marc, >> >> On 28/11/16 16:46, Jintack Lim wrote: >>> Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H b

Re: [PATCH] arm64: head.S: Fix CNTHCTL_EL2 access on VHE system

On Mon, Nov 28, 2016 at 11:56 AM, Marc Zyngier <marc.zyng...@arm.com> wrote: > On 28/11/16 16:43, Jintack Lim wrote: >> From: Jintack <jint...@cs.columbia.edu> >> >> Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit. >> EL1PCEN and

[PATCH v2] arm64: head.S: Fix CNTHCTL_EL2 access on VHE system

e host kernel runs in EL2. It is a hypervisor's responsibility to configure them before entering a VM, which runs in EL0 and EL1. Second, EL0 accesses are configured in the later stage of boot process. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Acked-by: Marc Zyngier <marc.

Re: [PATCH] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

On Tue, Nov 29, 2016 at 11:53 AM, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: > On 29/11/16 09:36, Marc Zyngier wrote: >> >> On 29/11/16 03:28, Jintack Lim wrote: >>> >>> On Mon, Nov 28, 2016 at 1:39 PM, Marc Zyngier <marc.zyng...@arm.com> >>

Re: [PATCH] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

On Tue, Nov 29, 2016 at 4:36 AM, Marc Zyngier <marc.zyng...@arm.com> wrote: > On 29/11/16 03:28, Jintack Lim wrote: >> On Mon, Nov 28, 2016 at 1:39 PM, Marc Zyngier <marc.zyng...@arm.com> wrote: >>> On 28/11/16 17:43, Marc Zyngier wrote: >>>> Hi Jintack,

Re: [RFC 00/55] Nested Virtualization on KVM/ARM

On Mon, Jan 9, 2017 at 10:05 AM, David Hildenbrand wrote: > >> Even though this work is not complete (see limitations below), I'd >> appreciate >> early feedback on this RFC. Specifically, I'm interested in: >> - Is it better to have a kernel config or to make it configurable at

Re: [RFC 4/8] KVM: arm/arm64: Initialize the emulated EL1 physical timer

On Mon, Jan 9, 2017 at 7:02 AM, Christoffer Dall <christoffer.d...@linaro.org> wrote: > On Mon, Dec 26, 2016 at 12:12:02PM -0500, Jintack Lim wrote: >> Initialize the emulated EL1 physical timer with the default irq number. >> >> Signed-off-by: Jintack Lim <jint...@cs

Re: [PATCH 2/3] KVM: arm64: Access CNTHCTL_EL2 bit fields correctly on VHE systems

Fri, Jan 13, 2017 at 11:31:32AM +0000, Marc Zyngier wrote: >>>> >>>> From: Jintack Lim <jint...@cs.columbia.edu> >>>> > ... > > >>>> /* >>>> * __boot_cpu_mode records what mode CPUs were booted in. >

Re: [RFC 4/8] KVM: arm/arm64: Initialize the emulated EL1 physical timer

On Tue, Jan 10, 2017 at 2:34 PM, Christoffer Dall <christoffer.d...@linaro.org> wrote: > On Tue, Jan 10, 2017 at 12:03:00PM -0500, Jintack Lim wrote: >> On Mon, Jan 9, 2017 at 7:02 AM, Christoffer Dall >> <christoffer.d...@linaro.org> wrote: >> > On Mon, Dec 2

Re: [RFC 8/8] KVM: arm/arm64: Emulate the EL1 phys timer register access

On Tue, Jan 10, 2017 at 2:40 PM, Christoffer Dall <christoffer.d...@linaro.org> wrote: > On Tue, Jan 10, 2017 at 12:36:36PM -0500, Jintack Lim wrote: >> On Mon, Jan 9, 2017 at 7:16 AM, Christoffer Dall >> <christoffer.d...@linaro.org> wrote: >> > On Mon, Dec 2

Re: [RFC 8/8] KVM: arm/arm64: Emulate the EL1 phys timer register access

On Mon, Jan 9, 2017 at 7:16 AM, Christoffer Dall <christoffer.d...@linaro.org> wrote: > On Mon, Dec 26, 2016 at 12:12:06PM -0500, Jintack Lim wrote: >> Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL. >> Now the VM is able to use the EL1 physical ti

Re: [RFC 6/8] KVM: arm/arm64: Update the physical timer interrupt level

On Mon, Jan 9, 2017 at 7:14 AM, Christoffer Dall <christoffer.d...@linaro.org> wrote: > On Mon, Dec 26, 2016 at 12:12:04PM -0500, Jintack Lim wrote: >> Now that we maintain the EL1 physical timer register states of the VM, >> update the physical timer interrupt level along

Re: [RFC 7/8] KVM: arm/arm64: Set up a background timer for the physical timer emulation

Hi Christoffer, thanks for the review! On Mon, Jan 9, 2017 at 7:13 AM, Christoffer Dall <christoffer.d...@linaro.org> wrote: > On Mon, Dec 26, 2016 at 12:12:05PM -0500, Jintack Lim wrote: >> Set a background timer for the EL1 physical timer emulation while VMs are >> run

[PATCH v3] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

for guests, and that's it. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- v2->v3: - Perform the initialization including CPU hotplug case. - Move has_vhe() to asm/virt.h v1->v2: - Skip configuring cnthctl_el2 in world switch path on VHE system. - Write patch based o

Re: [PATCH v2] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

Hi Marc, On Thu, Dec 1, 2016 at 8:30 AM, Marc Zyngier <marc.zyng...@arm.com> wrote: > Hi Jintack, > > On 01/12/16 11:38, Jintack Lim wrote: >> Current KVM world switch code is unintentionally setting wrong bits to >> CNTHCTL_EL2 when E2H == 1, which may allow guest OS

Re: [PATCH] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

On Wed, Nov 30, 2016 at 8:31 AM, Marc Zyngier <marc.zyng...@arm.com> wrote: > On 29/11/16 21:05, Jintack Lim wrote: >> On Tue, Nov 29, 2016 at 11:53 AM, Suzuki K Poulose >> <suzuki.poul...@arm.com> wrote: >>> On 29/11/16 09:36, Marc Zyngier wrote: >>&g

[PATCH v2] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

for guests, and that's it. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- v2: Skip configuring cnthctl_el2 in world switch path on VHE system. This patch is based on linux-next. --- arch/arm/kvm/arm.c | 1 + include/kvm/arm_arch_timer.h | 1 + virt/kvm/arm/arch_t

Re: [PATCH v3] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

On Tue, Dec 6, 2016 at 6:17 AM, Marc Zyngier <marc.zyng...@arm.com> wrote: > On 01/12/16 19:32, Jintack Lim wrote: >> Current KVM world switch code is unintentionally setting wrong bits to >> CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical >

Re: [PATCH v3] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

Hi Christoffer, Thanks for the review. On Tue, Dec 6, 2016 at 7:12 AM, Christoffer Dall <christoffer.d...@linaro.org> wrote: > On Tue, Dec 06, 2016 at 11:17:40AM +, Marc Zyngier wrote: >> On 01/12/16 19:32, Jintack Lim wrote: >> > Current KVM world switch code is unint

[RFC 09/55] KVM: arm64: Set shadow EL1 registers for virtual EL2 execution

state. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/kvm/context.c | 71 1 file changed, 71 insertions(+) diff --git a/arch/arm64/kvm/context.c b/arch/a

[RFC 02/55] KVM: arm64: Add nesting config option

From: Christoffer Dall <christoffer.d...@linaro.org> Add an option that allows nested hypervisor support. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/kvm/Kconfig | 6 ++ 1 file cha

[RFC 07/55] KVM: arm/arm64: Add virtual EL2 state emulation framework

stoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/include/asm/kvm_emulate.h | 4 ++ arch/arm/kvm/arm.c | 5 ++ arch/arm64/include/asm/kvm_emulate.h | 4 ++ arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/context.c

[RFC 08/55] KVM: arm64: Set virtual EL2 context depending on the guest exception level

From: Christoffer Dall <christoffer.d...@linaro.org> Set up virutal EL2 context to hardware if the guest exception level is EL2. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/

[RFC 00/55] Nested Virtualization on KVM/ARM

the guest hypervisor's stage 2 permission faults KVM: arm64: Emulate TLBI instruction KVM: arm64: Fixes to toggle_cache for nesting Jintack Lim (28): KVM: arm64: Add EL2 execution context for nesting KVM: arm64: Emulate taking an exception to the guest hypervisor KVM: arm64: Handle EL2

[RFC 19/55] KVM: arm64: Trap CPACR_EL1 access in virtual EL2

in EL0/EL1 from the guest hypervisor's perspective. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/kvm/hyp/switch.c | 10 +++--- arch/arm64/kvm/sys_regs.c | 10 +- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/hyp/switch.c

[RFC 04/55] KVM: arm64: Allow userspace to set PSR_MODE_EL2x

From: Christoffer Dall <christoffer.d...@linaro.org> We were not allowing userspace to set a more privileged mode for the VCPU than EL1, but now that we support nesting with a virtual EL2 mode, do allow this! Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off

[RFC 14/55] KVM: arm64: Take account of system instruction traps

-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/include/asm/kvm_coproc.h | 2 +- arch/arm64/kvm/handle_exit.c| 2 +- arch/arm64/kvm/sys_regs.c | 49 - arch/arm64/kvm/trace.h | 2 +- 4 files changed, 46 insertions(+), 9 del

[RFC 05/55] KVM: arm64: Add vcpu_mode_el2 primitive to support nesting

From: Christoffer Dall <christoffer.d...@linaro.org> When running a nested hypervisor we occasionally have to figure out if the mode we are switching into is the virtual EL2 mode or a regular EL0/1 mode. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by:

[RFC 35/55] KVM: arm/arm64: Support mmu for the virtual EL2 execution

y more. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/include/asm/kvm_asm.h | 6 ++-- arch/arm/include/asm/kvm_emulate.h | 4 +++ arch/arm/include/asm/kvm_host.h | 14 ++--- arch/arm/inc

[RFC 51/55] KVM: arm64: Expose physical address of vcpu interface

Expose physical address of vgic virtual cpu interface. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- include/kvm/arm_vgic.h | 1 + virt/kvm/arm/vgic/vgic-v2.c | 6 ++ 2 files changed, 7 insertions(+) diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 5

[RFC 33/55] KVM: arm/arm64: Remove unused params in mmu functions

inaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/kvm/mmu.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c index a5265ed..57cb671 100644 --- a/arch/arm/kvm/mmu.c +++ b/arch/arm/kvm/mmu.

[RFC 40/55] KVM: arm/arm64: Handle vttbr_el2 write operation from the guest hypervisor

in the shadow page table is not valid any more. So ummap it. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/include/asm/kvm_host.h | 1 + arch/arm/kvm/arm.c| 1 + arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/include/asm/kvm_mmu.h | 6 arch/arm

[RFC 34/55] KVM: arm/arm64: Abstract stage-2 MMU state into a separate structure

ed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/include/asm/kvm_asm.h| 7 +- arch/arm/include/asm/kvm_host.h | 26 --- arch/arm/kvm/arm.c| 34 + arch/arm/kvm/hyp/switch.c

[RFC 36/55] KVM: arm64: Invalidate virtual EL2 TLB entries when needed

; Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/kvm/arm.c | 6 ++ arch/arm/kvm/mmu.c | 16 2 files changed, 22 insertions(+) diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index aa8771d..371b38e7 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/k

[RFC 47/55] KVM: arm/arm64: Forward the guest hypervisor's stage 2 permission faults

ive S2 entry than the operation required. Check if this is the case, and inject a fault if it is. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/include/asm/kvm_mmu.h | 7 +++ arch/arm/kvm/mmu.c

[RFC 46/55] KVM: arm64: Add more info to the S2 translation result

ed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/include/asm/kvm_mmu.h | 3 +++ arch/arm64/kvm/mmu-nested.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/inc

[RFC 37/55] KVM: arm64: Setup vttbr_el2 on each VM entry

toffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/kvm/context.c | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/kvm/context.c b/arch/arm64/kvm/context.c index a93ffe4..b2c0220 100644 --- a/arch/a

[RFC 52/55] KVM: arm/arm64: Create a vcpu mapping for the nested VM

Create a mapping from the nested VM's cpu interface to the hardware virtual cpu interface. This is to allow the nested VM to access virtual cpu interface directly. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/include/asm/kvm_mmu.h | 3 +++ arch/arm/kvm

[RFC 39/55] KVM: arm/arm64: Add mmu context for the nesting

the guest hypervisor's point of view. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/include/asm/kvm_host.h | 3 ++ arch/arm/kvm/arm.c | 1 + arch/arm64/include/asm/kvm_emulate.h | 13 - arch/arm64/include/asm/kvm_host.h| 19 +

[RFC 55/55] KVM: arm64: Enable nested virtualization

Now that everything is ready, we enable nested virtualization by setting the HCR NV and NV1 bit. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/include/asm/kvm_arm.h | 1 + arch/arm64/kvm/hyp/switch.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff

[RFC 41/55] KVM: arm/arm64: Unmap/flush shadow stage 2 page tables

xample by clearing out an entire shadow stage-2 table. Probably we can do smarter with some sort of rmap structure. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/include/asm/kvm_mmu.h | 7

[RFC 44/55] KVM: arm/arm64: Move kvm_is_write_fault to header file

From: Christoffer Dall <christoffer.d...@linaro.org> Move this little function to the header files for arm/arm64 so other code can make use of it directly. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- ar

[RFC 48/55] KVM: arm64: Emulate TLBI instruction

r Dall <christoffer.d...@linaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/kvm/sys_regs.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index ddb641c..b0a057d 100644 --

[RFC 49/55] KVM: arm64: Fixes to toggle_cache for nesting

re EL1 register). We also reduce the scope of the flush operation to only flush shadow stage 2 page table state of the particular VCPU toggling the caches instead of the shadow stage 2 state of all possible VCPUs. Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Jinta

[RFC 32/55] KVM: arm/arm64: register GICH iodev for the guest hypervisor

Register a device for the virtual interface control block(GICH) access from the guest hypervisor. TODO: Get GICH address from DT, which is hardcoded now. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/include/uapi/asm/kvm.h | 6 ++ include/kvm/arm_

[RFC 30/55] KVM: arm/arm64: Inject irqs to the guest hypervisor

If we have a pending IRQ for the guest and the guest expects IRQs to be handled in its virtual EL2 mode (the virtual IMO bit is set) and it is not already running in virtual EL2 mode, then we have to emulate an IRQ exception. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Sign

[RFC 15/55] KVM: arm64: Trap EL1 VM register accesses in virtual EL2

inaro.org> Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/kvm/hyp/switch.c | 2 ++ arch/arm64/kvm/sys_regs.c | 7 ++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 83037cd..c05c48f 10064

[RFC 22/55] KVM: arm64: Handle PSCI call from the guest

for the psci call. On ARMv8.3, even if EL3 is not implemented, a smc instruction executed at non-secure EL1 is trapped to EL2 if HCR_EL2.TSC==1, rather than being treated as UNDEFINED. So, the host hypervisor can handle this psci call without any confusion. Signed-off-by: Jintack Lim <jint...@cs.columbia.

[RFC 12/55] KVM: arm64: Handle EL2 register access traps

of traps. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/kvm/sys_regs.c | 119 ++ arch/arm64/kvm/sys_regs.h | 7 +++ 2 files changed, 126 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 7

[RFC 27/55] KVM: arm/arm64: Emulate GICH interface on GICv2

Emulate GICH interface accesses from the guest hypervisor. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> Signed-off-by: Shih-Wei Li <shih...@cs.columbia.edu> Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm64/kvm/Makefile| 1 +

[RFC 53/55] KVM: arm64: Reflect shadow VMPIDR_EL2 value to MPIDR_EL1

A non-secure EL0 or EL1 read of MPIDR_EL1 should return the value of VMPIDR_EL2. We emulate this by copying the virtual VMPIDR_EL2 value to MPIDR_EL1 when entering VM's EL0 or EL1. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm64/kvm/context.c | 6 ++ 1 file chan

[RFC 50/55] KVM: arm/arm64: Abstract kvm_phys_addr_ioremap() function

calls this function with the VM's mmu context. Signed-off-by: Jintack Lim <jint...@cs.columbia.edu> --- arch/arm/kvm/mmu.c | 18 +- arch/arm64/include/asm/kvm_mmu.h | 3 +++ 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/arm/kvm/mmu.c b/ar

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