Re: [PATCH v5 0/4] vfio: type1: support for ARM SMMUS with VFIO_IOMMU_TYPE1

On Thu, Mar 05, 2015 at 05:54:26PM +, Alex Williamson wrote: On Thu, 2015-03-05 at 18:34 +0100, Eric Auger wrote: Ironically, since the correction of the IOMMU_CAP_CACHE_COHERENCY bug (https://lkml.org/lkml/2015/1/29/514) in vfio_iommu_type1.c, my Calxeda Midway VFIO use case is not

Re: [PATCH v4 06/12] KVM: arm64: guest debug, add SW break point support

Hi Alex, On Fri, May 15, 2015 at 03:27:09PM +0100, Alex Bennée wrote: This adds support for SW breakpoints inserted by userspace. We do this by trapping all guest software debug exceptions to the hypervisor (MDCR_EL2.TDE). The exit handler sets an exit reason of KVM_EXIT_DEBUG with the

Re: [PATCH] kvmtool: don't use PCI config space IRQ line field

On Thu, Jun 04, 2015 at 04:20:45PM +0100, Andre Przywara wrote: In PCI config space there is an interrupt line field (offset 0x3f), which is used to initially communicate the IRQ line number from firmware to the OS. _Hardware_ should never use this information, as the OS is free to write any

Re: stand-alone kvmtool

On Mon, Feb 23, 2015 at 05:23:58PM +, Pekka Enberg wrote: On 2/18/15 5:50 PM, Will Deacon wrote: Thanks for doing this. Since it looks unlikely that kvmtool will ever be merged back into the kernel tree, it makes sense to cut the dependency in my opinion. I am certainly OK

Re: [PATCH v3 06/10] arm: simplify MMIO dispatching

On Wed, Jun 24, 2015 at 02:30:05PM +0100, Andre Przywara wrote: do you want me to respin the whole series to address the remaining minor comments in the last four patches or do you want to take patch 01-06 already (which I think Marc has already agreed upon)? Then I would just send an updated

Re: [PATCH v2 01/11] KVM: arm: plug guest debug exploit

On Sun, Jun 14, 2015 at 05:13:05PM +0100, zichao wrote: I and marc are talking about how to plug the guest debug exploit in an easier way. I remembered that you mentioned disabling monitor mode had proven to be extremely fragile in practice on 32-bit ARM SoCs, what if I save/restore the

Re: [PATCH] kvmtool: don't use PCI config space IRQ line field

On Mon, Jun 15, 2015 at 11:45:38AM +0100, Andre Przywara wrote: On 06/05/2015 05:41 PM, Will Deacon wrote: On Thu, Jun 04, 2015 at 04:20:45PM +0100, Andre Przywara wrote: In PCI config space there is an interrupt line field (offset 0x3f), which is used to initially communicate the IRQ line

Re: [PATCH v5 10/12] KVM: arm64: guest debug, HW assisted debug support

Hi Alex, On Fri, May 29, 2015 at 10:30:26AM +0100, Alex Bennée wrote: This adds support for userspace to control the HW debug registers for guest debug. In the debug ioctl we copy the IMPDEF defined number of registers into a new register set called host_debug_state. There is now a new vcpu

Re: [PATCH v7 09/11] KVM: arm64: guest debug, HW assisted debug support

Hi Alex, On Wed, Jul 01, 2015 at 07:29:01PM +0100, Alex Bennée wrote: This adds support for userspace to control the HW debug registers for guest debug. In the debug ioctl we copy an IMPDEF registers into a new register set called host_debug_state. We use the recently introduced vcpu

Re: [PATCH] kvmtool: don't use PCI config space IRQ line field

Hi Andre, On Thu, Jun 18, 2015 at 06:19:53PM +0100, Andre Przywara wrote: I am tempted to remove shmem, since it's broken: a) there is no upstream driver, only some out-of-tree uio driver module in some Github repo Right, but that's the same for qemu and we've already made the jump of merging

Re: [PATCH v7 09/11] KVM: arm64: guest debug, HW assisted debug support

Hi Alex, On Thu, Jul 02, 2015 at 02:50:33PM +0100, Alex Bennée wrote: Are you happy with this?: [...] +/** + * kvm_arch_dev_ioctl_check_extension + * + * We currently assume that the number of HW registers is uniform + * across all CPUs (see cpuinfo_sanity_check). + */ int

Re: [PATCH v4 10/10] arm: use new irqchip parameter to create different vGIC types

On Fri, Jun 26, 2015 at 02:16:18PM +0100, Andre Przywara wrote: Currently we unconditionally create a virtual GICv2 in the guest. Add a --irqchip= parameter to let the user specify a different GIC type for the guest, when omitting this parameter it still defaults to --irqchip=gicv2. For now

Re: [PATCH 11/13] arm64: Panic when VHE and non VHE CPUs coexist

On Wed, Jul 08, 2015 at 05:19:14PM +0100, Marc Zyngier wrote: Having both VHE and non-VHE capable CPUs in the same system is likely to be a recipe for disaster. If the boot CPU has VHE, but a secondary is not, we won't be able to downgrade and run the kernel at EL1. Add CPU hotplug to the

Re: [PATCH 01/13] arm/arm64: Add new is_kernel_in_hyp_mode predicate

On Wed, Jul 08, 2015 at 05:19:04PM +0100, Marc Zyngier wrote: With ARMv8.1 VHE extension, it will be possible to run the kernel at EL2 (aka HYP mode). In order for the kernel to easily find out where it is running, add a new predicate that returns whether or not the kernel is in HYP mode.

Re: [PATCH 07/12] util/util.c: avoid clang error on vsnprintf

On Fri, Jul 17, 2015 at 05:02:13PM +0100, Andre Przywara wrote: clang by default doesn't seem to like printf calls with non-literal format strings. Add the proper pragma to disable this warning in the report function to make kvmtool compile with clang. Despite its GCC name, clang also accepts

Re: [PATCH 00/12] kvmtool: Improve portability

On Fri, Jul 17, 2015 at 05:02:06PM +0100, Andre Przywara wrote: Hi, Hi Andre, this is a collection of patches to bring kvmtool closer to standards compliance (with standards not necessarily meaning GNU only). With all those patches applied, you can compile kvmtool with newer C standards,

Re: [PATCH 06/12] kvm__set_dir(): avoid variable arguments call

On Fri, Jul 17, 2015 at 05:02:12PM +0100, Andre Przywara wrote: The clang compiler by default dislikes non-literal format strings in *printf functions, so it complains about kvm__set_dir() in kvm.c. Instead of suppressing this warning, lets change the code to avoid that unneeded var_args

Re: [RFC] vfio/type1: handle case where IOMMU does not support PAGE_SIZE size

On Wed, Oct 28, 2015 at 01:12:45PM +, Eric Auger wrote: > Current vfio_pgsize_bitmap code hides the supported IOMMU page > sizes smaller than PAGE_SIZE. As a result, in case the IOMMU > does not support PAGE_SIZE page, the alignment check on map/unmap > is done with larger page sizes, if any.

Re: [RFC] vfio/type1: handle case where IOMMU does not support PAGE_SIZE size

On Wed, Oct 28, 2015 at 06:48:41PM +0100, Eric Auger wrote: > On 10/28/2015 06:37 PM, Alex Williamson wrote: > > Ok, so with hopefully correcting my understand of what this does, isn't > > this effectively the same: > > > > diff --git a/drivers/vfio/vfio_iommu_type1.c > >

Re: [RFC] vfio/type1: handle case where IOMMU does not support PAGE_SIZE size

On Wed, Oct 28, 2015 at 10:27:28AM -0600, Alex Williamson wrote: > On Wed, 2015-10-28 at 13:12 +, Eric Auger wrote: > > diff --git a/drivers/vfio/vfio_iommu_type1.c > > b/drivers/vfio/vfio_iommu_type1.c > > index 57d8c37..13fb974 100644 > > --- a/drivers/vfio/vfio_iommu_type1.c > > +++

Re: [PATCH 2/2] arm64: KVM: Add workaround for Cortex-A57 erratum 834220

> +alternative_if_not ARM64_WORKAROUND_834220 > and x2, x1, #ESR_ELx_FSC_TYPE > cmp x2, #FSC_PERM > b.ne1f // Not a permission fault > +alternative_else > + nop // Use the permission fault path to > + nop //

Re: [PATCH 0/7] kvmtool: Cleanup kernel loading

On Fri, Oct 30, 2015 at 06:26:53PM +, Andre Przywara wrote: > Hi, Hello Andre, > this series cleans up kvmtool's kernel loading functionality a bit. > It has been broken out of a previous series I sent [1] and contains > just the cleanup and bug fix parts, which should be less controversial

Re: [PATCH v3 08/11] KVM: arm: implement dirty bit mechanism for debug registers

On Wed, Jul 08, 2015 at 11:50:22AM +0100, Zhichao Huang wrote: Are you happy with this?: You miss the reserved breakpoint, I think. I also still don't understand why this is preferable to trapping. Will ___ kvmarm mailing list

Re: [PATCH 01/18] ARM64: Move PMU register related defines to asm/pmu.h

On Mon, Jul 06, 2015 at 03:17:31AM +0100, shannon.z...@linaro.org wrote: From: Shannon Zhao shannon.z...@linaro.org To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel anup.pa...@linaro.org

Re: [PATCH v3 08/11] KVM: arm: implement dirty bit mechanism for debug registers

On Tue, Jul 07, 2015 at 11:06:57AM +0100, Zhichao Huang wrote: Chazy and me are talking about how to reduce the saving/restoring overhead for debug registers. We want to add a state in hw_breakpoint.c to indicate whether the host enable any hwbrpts or not (might export a fuction that kvm can

[GIT PULL] Late arm64 KVM fix for 4.2

Hi Linus, I appreciate that it's extremely late in the cycle, but we've uncovered a nasty bug in the arm64 KVM code which allows a badly behaved 32-bit guest to bring down the host. The fix is simple (it's what I believe we call a brown paper bag bug) and I don't think it makes sense to sit on

[PATCH] KVM: arm64: add workaround for Cortex-A57 erratum #852523

.@arm.com> Signed-off-by: Will Deacon <will.dea...@arm.com> --- arch/arm64/kvm/hyp.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S index 3c4f641451bb..c4016d411f4a 100644 --- a/arch/arm64/kvm/hyp.S +++ b/arch/arm64/kvm/hyp.

Re: [PATCH] KVM: arm64: add workaround for Cortex-A57 erratum #852523

On Mon, Sep 14, 2015 at 04:46:28PM +0100, Marc Zyngier wrote: > On 14/09/15 16:06, Will Deacon wrote: > > When restoring the system register state for an AArch32 guest at EL2, > > writes to DACR32_EL2 may not be correctly synchronised by Cortex-A57, > > which can lead to

[PATCH] KVM: arm64: remove all traces of the ThumbEE registers

Although the ThumbEE registers and traps were present in earlier versions of the v8 architecture, it was retrospectively removed and so we can do the same. Cc: Marc Zyngier <marc.zyng...@arm.com> Signed-off-by: Will Deacon <will.dea...@arm.com> --- arch/arm64/include/asm/kvm_arm.h

Re: [PATCH v6 02/21] KVM: ARM64: Define PMU data structure for each vcpu

On Tue, Dec 08, 2015 at 01:37:14PM +, Marc Zyngier wrote: > On 08/12/15 12:47, Shannon Zhao wrote: > > From: Shannon Zhao > > > > Here we plan to support virtual PMU for guest by full software > > emulation, so define some basic structs and functions preparing for >

Re: [PATCH 1/2] Add a rudimentary manpage

Hi Andre, of Phoronix fame, On Tue, Dec 22, 2015 at 02:00:46PM +, Andre Przywara wrote: > The kvmtool documentation is somewhat lacking, also it is not easily > accessible when living in the source tree only. > Add a good ol' manpage to document at least the basic commands and > their

Re: [PATCH 0/3] arm64: Kill ESR_LNX_EXEC

On Tue, May 31, 2016 at 05:53:11PM +0100, Catalin Marinas wrote: > On Tue, May 31, 2016 at 12:33:00PM +0100, Mark Rutland wrote: > > Mark Rutland (3): > > arm64: add macro to extract ESR_ELx.EC > > arm64/kvm: use ESR_ELx_EC to extract EC > > arm64: kill ESR_LNX_EXEC > > For the series: > >

Re: [PATCH 0/5] arm/arm64: KVM: Tighten memory protection flags

g: > - the text mapping read-only > - the rodata mapping read-only + no-exec > - everything else read-write + no-exec > > Of course, that's only valid when VHE is not in action. Tested on > Seattle and Cubietruck, based on 4.7-rc2. Looks good to me. For the series: Reviewed-by:

Re: [PATCH v10 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

On Fri, Jan 29, 2016 at 02:26:31PM +0800, Shannon Zhao wrote: > > > On 2016/1/29 2:06, Will Deacon wrote: > > On Thu, Jan 28, 2016 at 04:45:36PM +, Marc Zyngier wrote: > >> > On 28/01/16 16:31, Andrew Jones wrote: > >>> > > On Wed, Jan 27,

Re: [PATCH v10 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

On Thu, Jan 28, 2016 at 04:45:36PM +, Marc Zyngier wrote: > On 28/01/16 16:31, Andrew Jones wrote: > > On Wed, Jan 27, 2016 at 11:51:35AM +0800, Shannon Zhao wrote: > >> From: Shannon Zhao > >> > >> When we use tools like perf on host, perf passes the event type and

Re: [PATCH 00/10] KVM PCIe/MSI passthrough on ARM/ARM64

On Fri, Jan 29, 2016 at 10:25:52PM +0100, Eric Auger wrote: > On 01/29/2016 08:33 PM, Alex Williamson wrote: > >>> We know that x86 handles MSI vectors specially, so there is some > >>> hardware that helps the situation. It's not just that x86 has a fixed > >>> range for MSI, it's how it manages

Re: [PATCH 00/10] KVM PCIe/MSI passthrough on ARM/ARM64

On Wed, Feb 03, 2016 at 01:50:47PM +0100, Christoffer Dall wrote: > On Mon, Feb 01, 2016 at 02:03:51PM +, Will Deacon wrote: > > On Fri, Jan 29, 2016 at 10:25:52PM +0100, Eric Auger wrote: > > > On 01/29/2016 08:33 PM, Alex Williamson wrote: > > > >>>

Re: [PATCH v13 01/20] ARM64: Move PMU register related defines to asm/perf_event.h

On Wed, Feb 24, 2016 at 01:08:21PM +0800, Shannon Zhao wrote: > From: Shannon Zhao > > To use the ARMv8 PMU related register defines from the KVM code, we move > the relevant definitions to asm/perf_event.h header file and rename them > with prefix ARMV8_PMU_. > >

Re: [PATCH v13 01/20] ARM64: Move PMU register related defines to asm/perf_event.h

On Thu, Feb 25, 2016 at 10:02:00AM +0800, Shannon Zhao wrote: > On 2016/2/25 1:52, Will Deacon wrote: > > On Wed, Feb 24, 2016 at 01:08:21PM +0800, Shannon Zhao wrote: > >> From: Shannon Zhao <shannon.z...@linaro.org> > >> > >> To use the ARMv8 PMU rela

Re: [PATCH v13 01/20] ARM64: Move PMU register related defines to asm/perf_event.h

On Mon, Feb 29, 2016 at 01:59:49PM +, Marc Zyngier wrote: > On 29/02/16 13:07, Marc Zyngier wrote: > > On 25/02/16 02:02, Shannon Zhao wrote: > >> On 2016/2/25 1:52, Will Deacon wrote: > >>> On Wed, Feb 24, 2016 at 01:08:21PM +0800, Shannon Zhao wrote: > &

Re: [PATCH v13 01/20] ARM64: Move PMU register related defines to asm/perf_event.h

On Mon, Feb 29, 2016 at 01:07:23PM +, Marc Zyngier wrote: > On 25/02/16 02:02, Shannon Zhao wrote: > > On 2016/2/25 1:52, Will Deacon wrote: > >> On Wed, Feb 24, 2016 at 01:08:21PM +0800, Shannon Zhao wrote: > >>> From: Shannon Zhao <shannon.z...@linaro.org&

Re: [PATCH v2 00/21] arm64: Virtualization Host Extension support

On Mon, Jan 25, 2016 at 03:53:34PM +, Marc Zyngier wrote: > ARMv8.1 comes with the "Virtualization Host Extension" (VHE for > short), which enables simpler support of Type-2 hypervisors. > > This extension allows the kernel to directly run at EL2, and > significantly reduces the number of

Re: [PATCH v2 00/21] arm64: Virtualization Host Extension support

On Mon, Jan 25, 2016 at 04:37:39PM +, Marc Zyngier wrote: > On 25/01/16 16:26, Will Deacon wrote: > > On Mon, Jan 25, 2016 at 03:53:34PM +, Marc Zyngier wrote: > >> ARMv8.1 comes with the "Virtualization Host Extension" (VHE for > >> short), wh

Re: [PATCH v4 05/23] arm64: Add ARM64_HAS_VIRT_HOST_EXTN feature

On Thu, Feb 11, 2016 at 06:39:46PM +, Marc Zyngier wrote: > Add a new ARM64_HAS_VIRT_HOST_EXTN features to indicate that the > CPU has the ARMv8.1 VHE capability. > > This will be used to trigger kernel patching in KVM. > > Acked-by: Christoffer Dall > Acked-by:

Re: [PATCH v4 20/23] arm64: perf: Count EL2 events if the kernel is running in HYP

On Thu, Feb 11, 2016 at 06:40:01PM +, Marc Zyngier wrote: > When the kernel is running in HYP (with VHE), it is necessary to > include EL2 events if the user requests counting kernel or > hypervisor events. > > Reviewed-by: Christoffer Dall > Acked-by: Catalin

Re: [PATCH v4 23/23] arm64: Panic when VHE and non VHE CPUs coexist

On Thu, Feb 11, 2016 at 06:40:04PM +, Marc Zyngier wrote: > Having both VHE and non-VHE capable CPUs in the same system > is likely to be a recipe for disaster. > > If the boot CPU has VHE, but a secondary is not, we won't be > able to downgrade and run the kernel at EL1. Add CPU hotplug > to

Re: [PATCH v4 21/23] arm64: hw_breakpoint: Allow EL2 breakpoints if running in HYP

On Thu, Feb 11, 2016 at 06:40:02PM +, Marc Zyngier wrote: > With VHE, we place kernel {watch,break}-points at EL2 to get things > like kgdb and "perf -e mem:..." working. > > This requires a bit of repainting in the low-level encore/decode, > but is otherwise pretty simple. > >

Re: [PATCH v4 20/23] arm64: perf: Count EL2 events if the kernel is running in HYP

On Mon, Feb 15, 2016 at 06:23:35PM +, Marc Zyngier wrote: > On 15/02/16 17:22, Will Deacon wrote: > > On Thu, Feb 11, 2016 at 06:40:01PM +, Marc Zyngier wrote: > >> When the kernel is running in HYP (with VHE), it is necessary to > >> include EL2 events if the us

Re: [PATCH v4.1] arm64: hw_breakpoint: Allow EL2 breakpoints if running in HYP

y simple. > > Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> > --- > arch/arm64/include/asm/hw_breakpoint.h | 18 +- > 1 file changed, 13 insertions(+), 5 deletions(-) Acked-by: Will Deacon <will.dea...@arm.com> Will __

Re: [PATCH v4.1] arm64: perf: Count EL2 events if the kernel is running in HYP

; > Acked-by: Catalin Marinas <catalin.mari...@arm.com> > Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> > --- > arch/arm64/kernel/perf_event.c | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) Acked-by: Will Deacon <will.dea...@arm.com> Will

Re: [PATCH 1/3] irq: move IRQ routing into irq.c

Hi Andre, On Tue, Mar 01, 2016 at 04:49:36PM +, Andre Przywara wrote: > The current IRQ routing code in x86/irq.c is mostly implementing a > generic KVM interface which other architectures may use too. > Move the code to set up an MSI route into the generic irq.c file and > guard it with the

Re: [PATCH 2/3] MSI-X: update GSI routing after changed MSI-X configuration

On Tue, Mar 01, 2016 at 04:49:37PM +, Andre Przywara wrote: > When we set up GSI routing to map MSIs to KVM's GSI numbers, we > write the current device's MSI setup into the kernel routing table. > However the device driver in the guest can use PCI configuration space > accesses to change the

Re: [PATCH 3/3] virtio: fix endianness check for vhost support

On Tue, Mar 01, 2016 at 04:49:38PM +, Andre Przywara wrote: > Currently we deny any VHOST_* functionality if the architecture > supports guests with different endianness than the host. Most of the > time even on those architectures the endianness of guest and host are > the same, though, so we

Re: [PATCH 3/4] pre_init: add support for i386 also

On Wed, Feb 24, 2016 at 03:33:07PM +, Andre Przywara wrote: > Currently the pre_init support is provided only for x86_64. Since > having 32-bit x86 supported as well is not far off, just add an > implementation using i386 assembly instructions and the respective > syscall ABI. > >

Re: [PATCH 4/4] pre_init: add ARM implementations

On Wed, Feb 24, 2016 at 03:33:08PM +, Andre Przywara wrote: > The pre_init stub consists of two syscalls mouting the host's FS > via 9pfs and then calling the actual init binary, which can now > use normal dynamic linking. > Based on the x86 code provide an ARM and ARM64 implementation of >

Re: [PATCH 4/4] pre_init: add ARM implementations

On Wed, Mar 02, 2016 at 11:38:34PM +, André Przywara wrote: > On 02/03/16 03:00, Will Deacon wrote: > > On Wed, Feb 24, 2016 at 03:33:08PM +, Andre Przywara wrote: > >> The pre_init stub consists of two syscalls mouting the host's FS > >> via 9pfs and then cal

[PATCH] arm64: KVM: Add braces to multi-line if statement in virtual PMU code

^~ As it turns out, this particular case is harmless (we just do some &= operations with 0), but worth fixing nonetheless. Signed-off-by: Will Deacon <will.dea...@arm.com> --- virt/kvm/arm/pmu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/virt/kvm/arm/pmu.

Re: [PATCH] arm64: KVM: Add braces to multi-line if statement in virtual PMU code

On Fri, Apr 01, 2016 at 01:30:40PM +0200, Christoffer Dall wrote: > On Fri, Apr 01, 2016 at 12:12:22PM +0100, Will Deacon wrote: > > The kernel is written in C, not python, so we need braces around > > multi-line if statements. GCC 6 actually warns about this, thanks to the &g

Re: [PATCH v2 04/17] arm64: Introduce pmd_thp_or_huge

> Cc: Catalin Marinas <catalin.mari...@arm.com> > Cc: Steve Capper <steve.cap...@linaro.org> > Cc: Will Deacon <will.dea...@arm.com> > Acked-by: Christoffer Dall <christoffer.d...@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> > -

Re: [PATCH v2 01/17] arm64: Reuse TCR field definitions for EL1 and EL2

t; and VTCR_EL2 fields. > > This also fixes a bug where we assume TG0 in {V}TCR_EL2 is 1bit field. > > Cc: Catalin Marinas <catalin.mari...@arm.com> > Cc: Mark Rutland <mark.rutl...@arm.com> > Cc: Will Deacon <will.dea...@arm.com> > Cc: Marc Zyngier

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Wed, Feb 01, 2017 at 05:36:09PM +, Catalin Marinas wrote: > On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote: > > On Wed, Feb 01, 2017 at 11:29:22AM -0500, Christopher Covington wrote: > > > On 01/31/2017 12:56 PM, Marc Zyngier wrote: > > > > Given t

Re: [PATCH v4 3/4] arm64: Use __tlbi() macros in KVM code

On Wed, Feb 01, 2017 at 05:02:43PM +, Punit Agrawal wrote: > Will Deacon <will.dea...@arm.com> writes: > > > On Wed, Jan 25, 2017 at 08:39:43PM +0100, Christoffer Dall wrote: > >> On Wed, Jan 25, 2017 at 10:52:31AM -0500, Christopher Covington wrote: > >

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Wed, Feb 01, 2017 at 11:29:22AM -0500, Christopher Covington wrote: > On 01/31/2017 12:56 PM, Marc Zyngier wrote: > > Given that all ARMv8 CPUs can support SW_PAN, it is more likely to be > > enabled than the ARMv8.1 PAN. I'd vote for supporting the workaround in > > that case too, and hope

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin Marinas wrote: > On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote: > > On Wed, Feb 01, 2017 at 05:36:09PM +, Catalin Marinas wrote: > > > On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote: > > > &

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Wed, Feb 01, 2017 at 06:22:44PM +, Catalin Marinas wrote: > On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote: > > On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin Marinas wrote: > > > On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote: > > >

Re: [PATCH v4 3/4] arm64: Use __tlbi() macros in KVM code

On Wed, Jan 25, 2017 at 08:39:43PM +0100, Christoffer Dall wrote: > On Wed, Jan 25, 2017 at 10:52:31AM -0500, Christopher Covington wrote: > > Refactor the KVM code to use the __tlbi macros, which will allow an errata > > workaround that repeats tlbi dsb sequences to only change one location. > >

Re: [PATCH v4 3/4] arm64: Use __tlbi() macros in KVM code

On Wed, Jan 25, 2017 at 10:52:31AM -0500, Christopher Covington wrote: > Refactor the KVM code to use the __tlbi macros, which will allow an errata > workaround that repeats tlbi dsb sequences to only change one location. > This is not intended to change the generated assembly and comparing before

Re: [PATCH v4 4/4] arm64: Work around Falkor erratum 1009

On Wed, Jan 25, 2017 at 10:52:32AM -0500, Christopher Covington wrote: > During a TLB invalidate sequence targeting the inner shareable domain, > Falkor may prematurely complete the DSB before all loads and stores using > the old translation are observed. Instruction fetches are not subject to >

Re: [PATCH 1/2] arm64: kvm: reuse existing cache type/info related macros

cache type/info related macros and > replaces the hardcorded values. It also removes some of the comments > that become trivial with the macro names. > > Cc: Catalin Marinas <catalin.mari...@arm.com> > Cc: Will Deacon <will.dea...@arm.com> > Cc: Christoffer Dall <

Re: [PATCH V7 04/10] arm64: exception: handle Synchronous External Abort

On Thu, Jan 12, 2017 at 11:15:18AM -0700, Tyler Baicar wrote: > SEA exceptions are often caused by an uncorrected hardware > error, and are handled when data abort and instruction abort > exception classes have specific values for their Fault Status > Code. > When SEA occurs, before killing the

Re: [PATCH V7 04/10] arm64: exception: handle Synchronous External Abort

On Mon, Jan 16, 2017 at 01:09:22PM -0700, Baicar, Tyler wrote: > On 1/16/2017 4:53 AM, Will Deacon wrote: > >On Thu, Jan 12, 2017 at 11:15:18AM -0700, Tyler Baicar wrote: > >>SEA exceptions are often caused by an uncorrected hardware > >>error, and are handled when data

Re: [PATCH v3 6/9] kvm: arm/arm64: Add host pmu to support VM introspection

On Wed, Jan 18, 2017 at 01:01:40PM +, Punit Agrawal wrote: > Mark Rutland writes: > > > On Wed, Jan 18, 2017 at 11:21:21AM +, Marc Zyngier wrote: > >> On 10/01/17 11:38, Punit Agrawal wrote: > >> > +#define VM_MASK GENMASK_ULL(31, 0) > >> > +#define EVENT_MASK

Re: [RFC PATCH 4/7] arm64: tlbflush.h: add __tlbi() macro

atalin Marinas <catalin.mari...@arm.com> > Cc: Marc Zyngier <marc.zyng...@arm.com> > Cc: Will Deacon <will.dea...@arm.com> > [ rename helper to __tlbi, update commit log ] > Signed-off-by: Punit Agrawal <punit.agra...@arm.com> > --- > arch/arm64/include/asm

Re: [RFC PATCH 6/7] arm64: KVM: Handle trappable TLB instructions

Hi Punit, On Tue, Aug 16, 2016 at 11:45:11AM +0100, Punit Agrawal wrote: > The ARMv8 architecture allows trapping of TLB maintenane instructions > from EL0/EL1 to higher exception levels. On encountering a trappable TLB > instruction in a guest, an exception is taken to EL2. > > Add

Re: [RFC v2 PATCH 4/7] arm64: tlbflush.h: add __tlbi() macro

n.mari...@arm.com> > Cc: Marc Zyngier <marc.zyng...@arm.com> > Cc: Will Deacon <will.dea...@arm.com> > [ rename helper to __tlbi, update commit log ] > Signed-off-by: Punit Agrawal <punit.agra...@arm.com> > --- > arch/arm64/include/asm/tlbflush.h | 31

Re: [RFC PATCH 6/7] arm64: KVM: Handle trappable TLB instructions

On Fri, Aug 26, 2016 at 10:37:08AM +0100, Punit Agrawal wrote: > > Will Deacon <will.dea...@arm.com> writes: > >> The easiest thing to do is just TLBI VMALLE1IS for all trapped operations, > >> but you might want to see how that performs. > > > > Tha

Re: [PATCH 4/7] arm64: tlbflush.h: add __tlbi() macro

n.mari...@arm.com> > Cc: Marc Zyngier <marc.zyng...@arm.com> > [ rename helper to __tlbi, update comment and commit log ] > Signed-off-by: Punit Agrawal <punit.agra...@arm.com> > Reviewed-by: Will Deacon <will.dea...@arm.com> > --- > arch/arm64/include/asm/tlbflush.h |

Re: [PATCH 4/7] arm64: tlbflush.h: add __tlbi() macro

On Fri, Sep 23, 2016 at 05:07:10PM +0100, Will Deacon wrote: > On Tue, Sep 13, 2016 at 11:16:06AM +0100, Punit Agrawal wrote: > > From: Mark Rutland <mark.rutl...@arm.com> > > > > As with dsb() and isb(), add a __tlbi() helper so that we can avoid > > distract

Re: [PATCH v3 1/2] arm64: Add hypervisor safe helper for checking constant capabilities

Cc: Tirumalesh Chalamarla <tchalama...@cavium.com> > Cc: Marc Zyngier <marc.zyng...@arm.com> > Cc: Catalin Marinas <catalin.mari...@arm.com> > Cc: Will Deacon <will.dea...@arm.com> > Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> > --- >

Re: [PATCH 1/2] arm64: perf: Move ARMv8 PMU perf event definitions to asm/perf_event.h

D_CACHE0x04 > >>> +#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED 0x10 > >>> +#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES 0x11 > >>> +#define ARMV8_PMUV3_PERFCTR_BR_PRED 0x1

Re: [PATCH v3 1/1] KVM: ARM64: Fix the issues when guest PMCCFILTR is configured

ed-off-by: Wei Huang <w...@redhat.com> > --- > arch/arm64/include/asm/perf_event.h | 10 +- > arch/arm64/kernel/perf_event.c | 10 +- > virt/kvm/arm/pmu.c | 8 +++++--- > 3 files changed, 15 insertions(+), 13 deletions(-) Ack

Re: [PATCH] arm64: Work around Falkor erratum 1009

On Wed, Dec 07, 2016 at 03:04:31PM -0500, Christopher Covington wrote: > From: Shanker Donthineni > > During a TLB invalidate sequence targeting the inner shareable > domain, Falkor may prematurely complete the DSB before all loads > and stores using the old translation

Re: [PATCH v2] arm64: KVM: pmu: Reset PMSELR_EL0.SEL to a sane value before entering the guest

write_sysreg(0, pmselr_el0); > write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0); Curious, but why do you check MDCR.HPMN for PMSELR_EL0, but not for PMUSERENR_EL0? Anyway: Acked-by: Will Deacon <will.dea...@arm.com> Thanks, Will ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

Re: [PATCH 1/1] arm64: Correcting format specifier for printing 64 bit addresses

On Tue, Dec 06, 2016 at 03:26:37PM +, Catalin Marinas wrote: > On Mon, Dec 05, 2016 at 11:24:21AM +, Will Deacon wrote: > > On Mon, Dec 05, 2016 at 01:39:53PM +0530, Maninder Singh wrote: > > > This patch corrects format specifier for printing 64 bit addresses. >

Re: [PATCH v2] arm64: KVM: pmu: Reset PMSELR_EL0.SEL to a sane value before entering the guest

On Tue, Dec 06, 2016 at 05:29:18PM +0100, Christoffer Dall wrote: > On Tue, Dec 06, 2016 at 02:56:50PM +, Marc Zyngier wrote: > > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c > > index 83037cd..3b7cfbd 100644 > > --- a/arch/arm64/kvm/hyp/switch.c > > +++

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Thu, Jan 12, 2017 at 03:55:58PM +, Catalin Marinas wrote: > On Wed, Jan 11, 2017 at 06:22:08PM +, Marc Zyngier wrote: > > On 11/01/17 18:06, Catalin Marinas wrote: > > > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote: > > >> diff --git a/arch/arm64/mm/proc.S

Re: [PATCH v3 3/5] arm64: Create and use __tlbi_dsb() macros

On Fri, Jan 13, 2017 at 10:12:36AM -0500, Christopher Covington wrote: > On 01/12/2017 11:58 AM, Will Deacon wrote: > > On Wed, Jan 11, 2017 at 09:41:16AM -0500, Christopher Covington wrote: > >> +#define __tlbi_asm_dsb(as,

Re: [PATCH v3 3/5] arm64: Create and use __tlbi_dsb() macros

Hi Christopher, On Wed, Jan 11, 2017 at 09:41:16AM -0500, Christopher Covington wrote: > This refactoring will allow an errata workaround that repeats tlbi dsb > sequences to only change one location. This is not intended to change the > generated assembly and comparison of before and after

Re: [PATCH 1/1] arm64: Correcting format specifier for printing 64 bit addresses

rch/arm64/kernel/signal.c | 2 +- > arch/arm64/kvm/sys_regs.c | 8 ++-- > arch/arm64/mm/fault.c | 15 ++- > arch/arm64/mm/mmu.c| 4 ++-- > 4 files changed, 19 insertions(+), 10 deletions(-) Any reason not to fix kvm/trace.h too? Anyway, rest of this lo

Re: [PATCH 1/2] arm64: PMU: Do not use PMSELR_EL0 to access PMCCFILTR_EL0

On Fri, Dec 02, 2016 at 03:50:58PM +, Marc Zyngier wrote: > The ARMv8 architecture allows the cycle counter to be configured > by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0, > hence accessing PMCCFILTR_EL0. But it disallows the use of > PMSELR_EL0.SEL==0x1f to access the

Re: [PATCH 00/15] arm64/kvm: use common sysreg definitions

On Tue, Mar 28, 2017 at 10:29:31PM +0200, Christoffer Dall wrote: > On Tue, Mar 28, 2017 at 07:48:28PM +0100, Mark Rutland wrote: > > On Wed, Mar 22, 2017 at 06:35:13PM +, Mark Rutland wrote: > > > On Fri, Mar 10, 2017 at 06:35:55PM +, Will Deacon wrote: > > > &

Re: [PATCH 00/15] arm64/kvm: use common sysreg definitions

On Fri, Mar 10, 2017 at 08:17:22AM +, Marc Zyngier wrote: > On Thu, Mar 09 2017 at 5:07:12 pm GMT, Mark Rutland > wrote: > > Currently we duplicate effort in maintaining system register encodings > > across > > arm64's , KVM's sysreg tables, and other places. This >

Re: [PATCH] arm64: Add ASM modifier for xN register operands

On Mon, Apr 24, 2017 at 06:22:51PM +0100, Ard Biesheuvel wrote: > On 24 April 2017 at 18:00, Will Deacon <will.dea...@arm.com> wrote: > > Hi Matthias, > > > > On Thu, Apr 20, 2017 at 11:30:53AM -0700, Matthias Kaehlcke wrote: > >> Many inline assembly statements

Re: [PATCH] arm64: Add ASM modifier for xN register operands

Hi Matthias, On Thu, Apr 20, 2017 at 11:30:53AM -0700, Matthias Kaehlcke wrote: > Many inline assembly statements don't include the 'x' modifier when > using xN registers as operands. This is perfectly valid, however it > causes clang to raise warnings like this: > > warning: value size does not

Re: [RFC PATCH v2 02/19] arm64: Use the physical counter when available for read_cycles

pending on which timer is used for time keeping in the kernel > otherwise. We can do this using a static key to avoid a performance > penalty during runtime when reading the counter. > > Cc: Catalin Marinas <catalin.mari...@arm.com> > Cc: Will Deacon <will.dea...@arm.com> >

Re: [RFC PATCH v2 02/19] arm64: Use the physical counter when available for read_cycles

On Tue, Jul 25, 2017 at 07:36:47AM -0700, Christoffer Dall wrote: > On Tue, Jul 25, 2017 at 10:43:08AM +0100, Will Deacon wrote: > > On Mon, Jul 17, 2017 at 04:27:01PM +0200, Christoffer Dall wrote: > > > Currently get_cycles() is hardwired to arch_counter_get_cntvct() on >

Re: [RFC 21/55] KVM: arm64: Forward HVC instruction to the guest hypervisor

On Mon, Jul 03, 2017 at 11:51:26AM +0200, Christoffer Dall wrote: > On Mon, Jul 03, 2017 at 11:31:56AM +0200, Andrew Jones wrote: > > On Mon, Jul 03, 2017 at 11:08:50AM +0200, Christoffer Dall wrote: > > > On Mon, Jun 26, 2017 at 11:21:25AM -0400, Jintack Lim wrote: > > > > On Wed, Feb 22, 2017 at

Re: [PATCH v2] arm64: Add ASM modifier for xN register operands

On Fri, Apr 28, 2017 at 03:43:56PM +0100, Ard Biesheuvel wrote: > On 28 April 2017 at 15:33, Mark Rutland wrote: > > On Fri, Apr 28, 2017 at 08:18:52AM +0100, Ard Biesheuvel wrote: > OK, good. That is a departure from previous behavior of Clang, which > was causing build

Re: [PATCH] arm64: Add ASM modifier for xN register operands

On Mon, Apr 24, 2017 at 12:13:45PM -0700, Matthias Kaehlcke wrote: > El Mon, Apr 24, 2017 at 06:34:14PM +0100 Will Deacon ha dit: > > On Mon, Apr 24, 2017 at 06:22:51PM +0100, Ard Biesheuvel wrote: > > > AIUI, Clang now always complains for missing register width modifie

Re: [PATCH 10/11] arm64/kvm: context-switch ptrauth registers

On Tue, Aug 01, 2017 at 03:26:07PM +0100, Mark Rutland wrote: > On Tue, Aug 01, 2017 at 01:00:14PM +0200, Christoffer Dall wrote: > > On Wed, Jul 19, 2017 at 05:01:31PM +0100, Mark Rutland wrote: > > > When pointer authentication is supported, a guest may wish to use it. > > > This patch adds the

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