Andrew Jones writes:
> As a side effect of leaving Red Hat I won't be able to use my Red Hat
> email address anymore. I'm also changing the name of my gitlab group.
>
> Signed-off-by: Andrew Jones
> Signed-off-by: Andrew Jones
Reviewed-by: Alex Bennée
Andrew Jones writes:
> On Tue, Nov 30, 2021 at 02:11:34PM +0000, Alex Bennée wrote:
>>
>> Andrew Jones writes:
>>
>> > On Fri, Nov 19, 2021 at 04:30:47PM +, Alex Bennée wrote:
>> >>
>> >> Andrew Jones writes:
>> >>
&
would it take to enable such a feature?
--
Alex Bennée
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Alex Bennée writes:
> Hi,
>
> Not a great deal has changed from the last posting although I have
> dropped the additional unittests.cfg in favour of setting "nodefault"
> for the tests. Otherwise the clean-ups are mainly textual (removing
> printfs, random newli
-size 1 in QEMU to limit the code generation buffer size.
Signed-off-by: Alex Bennée
Message-Id: <2028184650.661575-11-alex.ben...@linaro.org>
---
v9
- moved back to unittests.cfg
- fixed some missing accel tags
- s/printf/report_info/
---
arm/Makefile.arm | 2 +
arm/Makefile
k" use WaitForEvent sleep
- "excl" use load/store exclusive semantics
Also two more options allow the test to be tweaked
- "noshuffle" disables the memory shuffling
- "count=%ld" set your own per-CPU increment count
Signed-off-by: Alex Bennée
Message-Id: <2
res.
I've imported a few more of the barrier primatives from the Linux source
tree so we consistently use macros.
The arm64 barrier primitives trip up on -Wstrict-aliasing so this is
disabled in the Makefile.
Signed-off-by: Alex Bennée
CC: Will Deacon
Message-Id: <2028184650.661575-9-alex.ben.
:
- "page" flush each page in turn (one per function)
- "self" do the flush after each computation cycle
- "verbose" report progress on each computation cycle
Signed-off-by: Alex Bennée
CC: Mark Rutland
Message-Id: <2028184650.661575-7-alex.ben...@linaro
This will allow TCG tests to alter things such as tb-size.
Signed-off-by: Alex Bennée
Message-Id: <2028184650.661575-10-alex.ben...@linaro.org>
---
arm/run | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arm/run b/arm/run
index a390ca5a..73c6c83a 100755
--- a/a
of
kvm-unit-tests.
Signed-off-by: Alex Bennée
CC: Timothy B. Terriberry
Acked-by: Andrew Jones
Message-Id: <2028184650.661575-6-alex.ben...@linaro.org>
---
arm/Makefile.common | 1 +
lib/prng.h | 82 ++
lib/prng.c
he
details are in the commits bellow the ---.
I've also tweaked .git/config so get_maintainer.pl should ensure
direct delivery of the patches ;-)
Alex Bennée (9):
docs: mention checkpatch in the README
arm/flat.lds: don't drop debug during link
Makefile: add GNU global tags support
lib: add isaac prng li
If you have ctags you might as well offer gtags as a target.
Signed-off-by: Alex Bennée
Message-Id: <2028184650.661575-4-alex.ben...@linaro.org>
---
Makefile | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index b80c31f8..0b7c03ac
-data.elf -o 0x4008
Signed-off-by: Alex Bennée
Message-Id: <2028184650.661575-3-alex.ben...@linaro.org>
---
arm/flat.lds | 1 -
1 file changed, 1 deletion(-)
diff --git a/arm/flat.lds b/arm/flat.lds
index 6fb459ef..47fcb649 100644
--- a/arm/flat.lds
+++ b/arm/flat.lds
@@ -62,7
Signed-off-by: Alex Bennée
Acked-by: Andrew Jones
Message-Id: <2028184650.661575-2-alex.ben...@linaro.org>
Acked-by: Thomas Huth
---
v9
- slightly more weaselly statement about checkpatch
---
README.md | 3 +++
1 file changed, 3 insertions(+)
diff --git a/README.md b/README.md
Andrew Jones writes:
> On Wed, Dec 01, 2021 at 04:20:02PM +0000, Alex Bennée wrote:
>>
>> Andrew Jones writes:
>>
>> > On Thu, Nov 18, 2021 at 06:46:44PM +, Alex Bennée wrote:
>> >> The upcoming MTTCG tests don't need to be run for normal KVM
Andrew Jones writes:
> On Thu, Nov 18, 2021 at 06:46:44PM +0000, Alex Bennée wrote:
>> The upcoming MTTCG tests don't need to be run for normal KVM unit
>> tests so lets add the facility to have a custom set of tests.
>
> I think an environment variable override
Andrew Jones writes:
> On Fri, Nov 19, 2021 at 04:30:47PM +0000, Alex Bennée wrote:
>>
>> Andrew Jones writes:
>>
>> > On Fri, Nov 12, 2021 at 02:08:01PM +, Alex Bennée wrote:
>> >>
>> >> Andrew Jones writes:
>> >>
&
Andrew Jones writes:
> On Thu, Nov 18, 2021 at 06:46:41PM +0000, Alex Bennée wrote:
>> Signed-off-by: Alex Bennée
>> ---
>> README.md | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/README.md b/README.md
>> index b498aaf..5db48e5
Hi,
changes since v3:
- dropped the pending LPI test altogether
Alex Bennée (3):
arm64: remove invalid check from its-trigger test
arm64: enable its-migration tests for TCG
arch-run: do not process ERRATA when running under TCG
scripts/arch-run.bash | 4 +++-
arm/gic.c
.
Signed-off-by: Alex Bennée
---
scripts/arch-run.bash | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/scripts/arch-run.bash b/scripts/arch-run.bash
index 43da998..f1f4456 100644
--- a/scripts/arch-run.bash
+++ b/scripts/arch-run.bash
@@ -267,7 +267,9 @@ env_file
With the support for TCG emulated GIC we can also test these now.
Signed-off-by: Alex Bennée
Reviewed-by: Eric Auger
Reviewed-by: Andrew Jones
Cc: Shashi Mallela
Message-Id: <20210525172628.2088-4-alex.ben...@linaro.org>
---
v3
- add its-migrate-unmapped-collection
---
arm/unittes
While an IRQ is not "guaranteed to be visible until an appropriate
invalidation" it doesn't stop the actual implementation delivering it
earlier if it wants to. This is the case for QEMU's TCG and as tests
should only be checking architectural compliance this check is
invalid.
Signed-of
Andrew Jones writes:
> On Fri, Nov 12, 2021 at 02:08:01PM +0000, Alex Bennée wrote:
>>
>> Andrew Jones writes:
>>
>> > On Fri, Nov 12, 2021 at 11:47:31AM +, Alex Bennée wrote:
>> >> Hi,
>> >>
>> >> Sorry this has been s
-size 1 in QEMU to limit the code generation buffer size.
Signed-off-by: Alex Bennée
---
v5
- added armv8 version of the tcg tests
- max out at -smp 4 in unittests.cfg
- add up IRQs sent and delivered for PASS/FAIL
- take into account error count
- add "rounds=" parameter
-
of
kvm-unit-tests.
Signed-off-by: Alex Bennée
CC: Timothy B. Terriberry
Acked-by: Andrew Jones
---
arm/Makefile.common | 1 +
lib/prng.h | 82 ++
lib/prng.c | 162
3 files changed, 245 insertions(+)
create
This will allow TCG tests to alter things such as tb-size.
Signed-off-by: Alex Bennée
---
arm/run | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arm/run b/arm/run
index a390ca5..73c6c83 100755
--- a/arm/run
+++ b/arm/run
@@ -58,8 +58,8 @@ if $qemu $M -device '?' 2>
res.
I've imported a few more of the barrier primatives from the Linux source
tree so we consistently use macros.
The arm64 barrier primitives trip up on -Wstrict-aliasing so this is
disabled in the Makefile.
Signed-off-by: Alex Bennée
CC: Will Deacon
---
v8
- move to mttcgtests.cfg
- fix checkpa
k" use WaitForEvent sleep
- "excl" use load/store exclusive semantics
Also two more options allow the test to be tweaked
- "noshuffle" disables the memory shuffling
- "count=%ld" set your own per-CPU increment count
Signed-off-by: Alex Bennée
---
v2
- Do
:
- "page" flush each page in turn (one per function)
- "self" do the flush after each computation cycle
- "verbose" report progress on each computation cycle
Signed-off-by: Alex Bennée
CC: Mark Rutland
---
v2
- rename to tlbflush-test
- made makefile change
The upcoming MTTCG tests don't need to be run for normal KVM unit
tests so lets add the facility to have a custom set of tests.
Signed-off-by: Alex Bennée
---
run_tests.sh | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/run_tests.sh b/run_tests.sh
index 9f233c5
Signed-off-by: Alex Bennée
---
README.md | 2 ++
1 file changed, 2 insertions(+)
diff --git a/README.md b/README.md
index b498aaf..5db48e5 100644
--- a/README.md
+++ b/README.md
@@ -182,3 +182,5 @@ the code files. We also start with common code and finish
with unit test
code. git-diff's
-data.elf -o 0x4008
Signed-off-by: Alex Bennée
---
arm/flat.lds | 1 -
1 file changed, 1 deletion(-)
diff --git a/arm/flat.lds b/arm/flat.lds
index 6fb459e..47fcb64 100644
--- a/arm/flat.lds
+++ b/arm/flat.lds
@@ -62,7 +62,6 @@ SECTIONS
/DISCARD/ : {
*(.note*)
*(.interp
If you have ctags you might as well offer gtags as a target.
Signed-off-by: Alex Bennée
---
Makefile | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index b80c31f..0b7c03a 100644
--- a/Makefile
+++ b/Makefile
@@ -122,6 +122,9 @@ cscope
warnings make no sense for kvm-unit-tests).
I dropped an additional test which attempts to test for data flush
behaviour but it still needs some work:
https://github.com/stsquad/kvm-unit-tests/commit/712eb3a287df24cdeff00ef966d68aef6ff2b8eb
Alex Bennée (10):
docs: mention checkpatch in the README
Andrew Jones writes:
> On Fri, Nov 12, 2021 at 11:47:31AM +0000, Alex Bennée wrote:
>> Hi,
>>
>> Sorry this has been sitting in my tree so long. The changes are fairly
>> minor from v2. I no longer split the tests up into TCG and KVM
>> versions and inst
Andrew Jones writes:
> On Fri, Nov 12, 2021 at 11:47:31AM +0000, Alex Bennée wrote:
>> Hi,
>>
>> Sorry this has been sitting in my tree so long. The changes are fairly
>> minor from v2. I no longer split the tests up into TCG and KVM
>> versions and inst
With the support for TCG emulated GIC we can also test these now.
Signed-off-by: Alex Bennée
Reviewed-by: Eric Auger
Reviewed-by: Andrew Jones
Cc: Shashi Mallela
Message-Id: <20210525172628.2088-4-alex.ben...@linaro.org>
---
v3
- add its-migrate-unmapped-collection
---
arm/unittes
.
Signed-off-by: Alex Bennée
---
scripts/arch-run.bash | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/scripts/arch-run.bash b/scripts/arch-run.bash
index 43da998..f1f4456 100644
--- a/scripts/arch-run.bash
+++ b/scripts/arch-run.bash
@@ -267,7 +267,9 @@ env_file
While an IRQ is not "guaranteed to be visible until an appropriate
invalidation" it doesn't stop the actual implementation delivering it
earlier if it wants to. This is the case for QEMU's TCG and as tests
should only be checking architectural compliance this check is
invalid.
Signed-of
Hi,
Sorry this has been sitting in my tree so long. The changes are fairly
minor from v2. I no longer split the tests up into TCG and KVM
versions and instead just ensure that ERRATA_FORCE is always set when
run under TCG.
Alex Bennée (3):
arm64: remove invalid check from its-trigger test
Andrew Jones writes:
> On Tue, Jun 01, 2021 at 05:49:01PM +0100, Alex Bennée wrote:
>>
>> Auger Eric writes:
>>
>> > Hi Alex,
>> >
>> > On 5/25/21 7:26 PM, Alex Bennée wrote:
>> >> When running the test in TCG we are basically runn
Auger Eric writes:
> Hi Alex,
>
> On 5/25/21 7:26 PM, Alex Bennée wrote:
>> When running the test in TCG we are basically running on bare metal so
>> don't rely on having a particular kernel errata applied.
>>
>> You might wonder why we handle this with a
QEMU is able to give a counter for instructions retired under TCG but
you need to enable -icount for it to work. Split the tests into
kvm/tcg variants to support this.
[AJB: I wonder if the solution is to have a totally separate
unittests.cfg for TCG mode here?]
Signed-off-by: Alex Bennée
While an IRQ is not "guaranteed to be visible until an appropriate
invalidation" it doesn't stop the actual implementation delivering it
earlier if it wants to. This is the case for QEMU's TCG and as tests
should only be checking architectural compliance this check is
invalid.
Signed-of
feature implementation
Date: Thu, 29 Apr 2021 19:41:53 -0400
Message-Id: <20210429234201.125565-1-shashi.mall...@linaro.org>
The only real change from the last version was to drop the IMPDEF
behaviour check instead of trying to work around it for the TCG case.
Please review.
Alex Ben
The very fact that QEMU drops the deprecation warning while running is
enough to confuse the its-migration test into failing. The boolean
options server and wait have accepted the long form options for a long
time.
Signed-off-by: Alex Bennée
Cc: Shashi Mallela
---
scripts/arch-run.bash | 4
eval "$@" which unwraps the -append
leading to any second parameter being split and leaving QEMU very
confused and the test hanging. This seemed simpler than re-writing all
the test running logic in something sane ;-)
Signed-off-by: Alex Bennée
Cc: Shashi Mallela
---
arm/gic.c
With the support for TCG emulated GIC we can also test these now.
Signed-off-by: Alex Bennée
Cc: Shashi Mallela
---
arm/unittests.cfg | 2 --
1 file changed, 2 deletions(-)
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index f776b66..1a39428 100644
--- a/arm/unittests.cfg
+++ b/arm
Alex Bennée writes:
> Marc Zyngier writes:
>
>> On Wed, 28 Apr 2021 15:00:15 +0100,
>> Alexandru Elisei wrote:
>>>
>>> I interpret that as that an INVALL guarantees that a change is
>>> visible, but it the change can become visible even without
t; should be dropped completely, rather than trying to sidestep it for
> TCG.
All three parts of that section?
report(check_acked(, -1, -1),
"dev2/eventid=20 still does not trigger any LPI");
report(check_acked(, 0, 8195),
&quo
Marc Zyngier writes:
> On 2021-04-28 11:18, Alex Bennée wrote:
>> A few of the its-trigger tests rely on IMPDEF behaviour where caches
>> aren't flushed before invall events. However TCG emulation doesn't
>> model any invall behaviour and as we can't probe for it we need
o
some limitations in the run_migration() script in the last patch.
Alex Bennée (4):
arm64: split its-trigger test into KVM and TCG variants
scripts/arch-run: don't use deprecated server/nowait options
arm64: enable its-migration tests for TCG
arm64: split its-migrate-unmapped-collection in
With the support for TCG emulated GIC we can also test these now. You
need to call run_tests.sh with -a to trigger the
its-migrate-unmapped-collection test which obviously doesn't need the
KVM errata to run in TCG system emulation mode.
Signed-off-by: Alex Bennée
---
arm/unittests.cfg | 3
"$@" which unwraps the -append
leading to any second parameter being split and leaving QEMU very
confused and the test hanging. This seemed simpler than re-writing all
the test running logic in something sane ;-)
Signed-off-by: Alex Bennée
Cc: Shashi Mallela
---
arm/gic.c | 7 ++
.
Signed-off-by: Alex Bennée
Cc: Shashi Mallela
---
arm/gic.c | 60 +++
arm/unittests.cfg | 11 -
2 files changed, 45 insertions(+), 26 deletions(-)
diff --git a/arm/gic.c b/arm/gic.c
index 98135ef..96a329d 100644
--- a/arm/gic.c
+++ b/arm
The very fact that QEMU drops the deprecation warning while running is
enough to confuse the its-migration test into failing. The boolean
options server and wait have accepted the long form options for a long
time.
Signed-off-by: Alex Bennée
---
scripts/arch-run.bash | 4 ++--
1 file changed, 2
Marc Zyngier writes:
> On 2020-08-04 15:44, Alex Bennée wrote:
>> Marc Zyngier writes:
>>
>>> On 2020-08-04 13:44, Alex Bennée wrote:
>>>> The VIRTIO_PCI support is an idealised PCI bus, we don't need a bunch
>>>> of bloat for real worl
Ard Biesheuvel writes:
> On Tue, 4 Aug 2020 at 14:45, Alex Bennée wrote:
>>
>> Hi,
>>
>> When building guest kernels for virtualisation we were bringing in a
>> bunch of stuff from physical hardware which we don't need for our
>> idealised fixable virt
Marc Zyngier writes:
> On 2020-08-04 13:44, Alex Bennée wrote:
>> The VIRTIO_PCI support is an idealised PCI bus, we don't need a bunch
>> of bloat for real world hardware for a VirtIO guest.
>
> Who says this guest will only have virtio devices?
This is true - altho
-thunder*
-rwxr-xr-x 1 alex alex 85639808 Aug 3 17:12 vmlinux*
Signed-off-by: Alex Bennée
---
drivers/pci/controller/Makefile | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 8fad4781a5d3..3b9b72f5773a
The VIRTIO_PCI support is an idealised PCI bus, we don't need a bunch
of bloat for real world hardware for a VirtIO guest.
Signed-off-by: Alex Bennée
---
kernel/configs/kvm_guest.config | 1 +
1 file changed, 1 insertion(+)
diff --git a/kernel/configs/kvm_guest.config b/kernel/configs
85652472 Aug 3 16:48 vmlinux*
-rwxr-xr-x 1 alex alex 86033880 Aug 3 16:39 vmlinux.orig*
Signed-off-by: Alex Bennée
Cc: Robert Richter
Cc: linux-...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
---
arch/arm64/Kconfig.platforms| 2 ++
arch/arm64/configs/defconfig| 1
PCI_QUIRKS from the KVM guest build as a virtual
PCI device should be quirk free.
This is my first time hacking around Kconfig so I hope I've got the
balance between depends and selects right but please let be know if it
could be specified in a cleaner way.
Alex Bennée (3):
arm64: allow de
Alexandru Elisei writes:
> Hi,
>
> On 1/10/20 4:05 PM, Alex Bennée wrote:
>> This was an attempt to replicate a QEMU bug. However to trigger the
>> bug you need to have an offset set in EL2 which kvm-unit-tests is
>> unable to do. However it does exercise some m
This was an attempt to replicate a QEMU bug. However to trigger the
bug you need to have an offset set in EL2 which kvm-unit-tests is
unable to do. However it does exercise some more corner cases.
Bug: https://bugs.launchpad.net/bugs/1859021
Signed-off-by: Alex Bennée
---
arm/timer.c | 27
Dave Martin writes:
> On Thu, Apr 25, 2019 at 01:30:29PM +0100, Alex Bennée wrote:
>>
>> Dave Martin writes:
>>
>> > Currently, the way error codes are generated when processing the
>> > SVE register access ioctls in a bit haphazard.
>
x-arm.org/git?p=linux-dm.git;a=shortlog;h=refs/heads/sve-kvm-fixes/v2/head
>
> Tested with qemu and kvmtool on ThunderX2, and with kvmtool on the Arm
> Fast model (to exercise SVE support).
These all look good to me:
Reviewed-by: Alex Bennée
--
Alex Bennée
_
; /* Handle the KVM_REG_ARM64_SVE_VLS pseudo-reg as a special case: */
> if (reg->id == KVM_REG_ARM64_SVE_VLS)
> return set_sve_vls(vcpu, reg);
>
> - /* Otherwise, reg is an architectural SVE register... */
> + /* Try to interpret reg ID as an architectural SVE register... */
> + ret = sve_reg_to_region(, vcpu, reg);
> + if (ret)
> + return ret;
>
> if (!kvm_arm_vcpu_sve_finalized(vcpu))
> return -EPERM;
>
> - if (sve_reg_to_region(, vcpu, reg))
> - return -ENOENT;
> -
> if (copy_from_user(vcpu->arch.sve_state + region.koffset, uptr,
> region.klen))
> return -EFAULT;
--
Alex Bennée
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(Documentation only.)
>
> * Patch 27: KVM: arm64/sve: Document KVM API extensions for SVE
>
>(Documentation only.)
I've finished going through the series. Aside from a few minor nits and
the discussion you've already had with drew happy with it. Have a
general:
Reviewed-by: A
> *
> @@ -1346,7 +1418,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
> ID_SANITISED(ID_AA64PFR1_EL1),
> ID_UNALLOCATED(4,2),
> ID_UNALLOCATED(4,3),
> - ID_UNALLOCATED(4,4),
> + { SYS_DESC(SYS_ID_AA64ZFR0_EL1), access_id_aa64zfr0_el1, .get_user =
>
t;> > > >
>> > > > +/* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
>> > > > +#define vcpu_sve_pffr(vcpu) ((void *)((char
>> > > > *)((vcpu)->arch.sve_state) + \
>> > > > +
>
register access
> support.
>
> Since SVE is an opt-in feature for userspace, this will not affect
> existing users.
>
> Signed-off-by: Dave Martin
> Reviewed-by: Julien Thierry
> Tested-by: zhang.lei
Reviewed-by: Alex Bennée
>
> ---
>
> Changes s
const struct sys_reg_desc *rd);
> };
this makes me wonder what sort of machines will see different register
visibility depending on which vcpu you are running on?
Otherwise is looks good to me:
Reviewed-by: Alex Bennée
--
Alex Bennée
_
on.
>
> Signed-off-by: Dave Martin
> Reviewed-by: Julien Grall
> Reviewed-by: Peter Maydell
Reviewed-by: Alex Bennée
> ---
> Documentation/virtual/kvm/api.txt | 24
> 1 file changed, 24 insertions(+)
>
> diff --git a/Documentation/virtual/kvm/a
Dave Martin writes:
> This series contains some cleanups applicable to the SVE KVM support
> patches merged into kvmarm/next. These arose from Andrew Jones'
> review.
Does this mean these won't get merged into the original series before
the final merging upstream?
--
Al
bled Pauth but no firmware underneath it?
Either we've got something wrong or we'll need to rethink what features
the user can have enabled by -cpu max on a direct kernel boot.
--
Alex Bennée
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are
> of course welcome!)
I've finished my pass for this revision. Sorry it took so long to get to
it.
--
Alex Bennée
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are not recommended except for testing and
> +experimentation purposes. Architecturally compliant guest OSes will
> +work, but may or may not make effective use of the resulting
> +configuration.
> +
> +After a successful KVM_ARM_SVE_CONFIG_SET, KVM_ARM_SVE_CONFIG_GET
; unsigned int ioctl, unsigned long arg)
> {
> - return -EINVAL;
> + void __user *userp = (void __user *)arg;
> +
> + switch (ioctl) {
> + case KVM_ARM_SVE_CONFIG:
> + return kvm_vcpu_s
.sve_max_vl)));
> +
> + return 0;
> +}
> +
> /**
> * kvm_reset_vcpu - sets core registers and sys_regs to reset value
> * @vcpu: The VCPU pointer
> @@ -103,6 +148,7 @@ int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm,
> long ext)
> int kvm_reset_vcpu(str
t;>
>> I could add a special meaning for an empty kvm_sve_vls, such that
>> it doesn't enable SVE on the affected vcpu. That retains the ability
>> to create heterogeneous guests while still following the above flow.
>>
> I think making sure that userspace
Dave Martin writes:
> On Wed, Nov 21, 2018 at 04:09:03PM +0000, Alex Bennée wrote:
>>
>> Dave Martin writes:
>>
>> > This patch includes the SVE register IDs in the list returned by
>> > KVM_GET_REG_LIST, as appropriate.
>> >
>&g
Dave Martin writes:
> On Wed, Nov 21, 2018 at 04:16:42PM +0000, Alex Bennée wrote:
>>
>> Dave Martin writes:
>>
>> > KVM will need to interrogate the set of SVE vector lengths
>> > available on the system.
>> >
>> >
q_to_bit() and bit_to_vq() are not intended for use outside these
> functions, so they are given a __ prefix to warn people not to use
> them unless they really know what they are doing.
Personally I wouldn't have bothered with the __ but whatever:
Reviewed-by: Alex Bennée
>
> Signe
_arm_get_fw_num_regs(vcpu);
> res += NUM_TIMER_REGS;
> @@ -357,6 +398,10 @@ int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64
> __user *uindices)
> uindices++;
> }
>
> + ret = copy_sve_reg_indices(vcpu, );
> + if (ret)
> +
> + case KVM_REG_ARM_CORE: return set_core_reg(vcpu, reg);
> + case KVM_REG_ARM_FW:return kvm_arm_set_fw_reg(vcpu, reg);
> + case KVM_REG_ARM64_SVE: return set_sve_reg(vcpu, reg);
> + }
>
> if (is_timer_reg(reg->id))
> return set_timer_reg(vcpu, reg);
The kernel coding-style.rst seems mute on the subject of default
handling in switch but it's probably worth having a:
default: break; /* falls through */
to be explicit.
It's out of scope for this review but I did get a bit confused as the
KVM_REG_ARM_COPROC_SHIFT registers seems to be fairly spread out across
the files. We have demux_c15_get/set in sys_regs but doesn't look as
though it touches the rest of the emulation logic and we have
kvm_arm_get/set_fw_reg which are "special" PCSI registers. I guess this
is because COPROC_SHIFT has been used for a bunch of disparate core and
non-core and special registers.
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away and just moves things around a little bit. So I
>> guess it could makes sense for the fast(ish) path although I'd be
>> interested in knowing if it made any real difference to the numbers.
>> After all the first read should be well cached and moving it through the
>> st
Dave Martin writes:
> On Mon, Nov 19, 2018 at 04:36:01PM +0000, Alex Bennée wrote:
>>
>> Dave Martin writes:
>>
>> > In order to give each vcpu its own view of the SVE registers, this
>> > patch adds context storage via a new sve_state pointer in struc
Dave Martin writes:
> On Mon, Nov 19, 2018 at 04:48:36PM +0000, Alex Bennée wrote:
>>
>> Dave Martin writes:
>>
>> > The Arm SVE architecture defines registers that are up to 2048 bits
>> > in size (with some possibility of further future expansion
ve space for another few bits that
is the last one without changing the mask.
Reviewed-by: Alex Bennée
>
> struct kvm_reg_list {
> __u64 n; /* number of regs */
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ixup_guest_exit(struct kvm_vcpu
> *vcpu, u64 *exit_code)
>* and restore the guest context lazily.
>* If FP/SIMD is not implemented, handle the trap and inject an
>* undefined instruction exception to the guest.
> + * Similarly for trapped SVE accesses.
>*/
> - if (system_supports_fpsimd() &&
> - kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_FP_ASIMD)
> - return __hyp_switch_fpsimd(vcpu);
> + guest_has_sve = vcpu_has_sve(vcpu);
I'm not sure if it's worth fishing this out here given you are already
passing vcpu down the chain.
> + if (__hyp_trap_is_fpsimd(vcpu, guest_has_sve))
> + return __hyp_switch_fpsimd(vcpu, guest_has_sve);
>
> if (!__populate_fault_info(vcpu))
> return true;
Otherwise:
Reviewed-by: Alex Bennée
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Dave Martin writes:
> On Thu, Nov 15, 2018 at 03:39:01PM +0000, Alex Bennée wrote:
>>
>> Dave Martin writes:
>>
>> > Due to the way the effective SVE vector length is controlled and
>> > trapped at different exception levels, certain mismatches in th
cess_id_aa64zfr0_el1, .get_user =
> get_id_aa64zfr0_el1, .set_user = set_id_aa64zfr0_el1, .check_present =
> sve_check_present },
> +#else
> ID_UNALLOCATED(4,4),
> +#endif
> ID_UNALLOCATED(4,5),
> ID_UNALLOCATED(4,6),
> ID_UNALLOCATED(4,7),
> @@ -1307,6 +1407,9 @@ static const struct sys_reg_desc sys_reg_descs[] = {
>
> { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1,
> 0x00C50078 },
> { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
> +#ifdef CONFIG_ARM64_SVE
> + { SYS_DESC(SYS_ZCR_EL1), access_zcr_el1, reset_unknown, ZCR_EL1,
> ~0xfUL, .get_user = get_zcr_el1, .set_user = set_zcr_el1, .check_present =
> sve_check_present },
> +#endif
> { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
> { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
> { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
Overlong lines.
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ID register
> fields such as ID_AA64PFR0_EL1.SVE for example.
>
> This patch propagates vcpu into read_id_reg() so that future
> patches can add run-time checks on the guest configuration here.
>
> For now, there is no functional change.
>
> Signed-off-by: Dave Martin
Revi
Dave Martin writes:
> Since SVE will be enabled or disabled on a per-vcpu basis, a flag
> is needed in order to track which vcpus have it enabled.
>
> This patch adds a suitable flag and a helper for checking it.
>
> Signed-off-by: Dave Martin
Reviewed-by: Alex Bennée
found */
> + sve_max_virtualisable_vl = SVE_VQ_MAX;
> + else if (WARN_ON(b == SVE_VQ_MAX - 1))
> + /* No virtualisable VLs? This is architecturally forbidden. */
> + sve_max_virtualisable_vl = SVE_VQ_MIN;
>
p, nor do we need to
> fake a debug exception from the guest.
>
> Signed-off-by: Mark Rutland
> Cc: Alex Bennée
> Cc: Christoffer Dall
> Cc: Marc Zyngier
> Cc: Peter Maydell
Reviewed-by: Alex Bennée
Tested-by: Alex Bennée
For reference I'm leaving this kernel boot soaking o
way of applying
> consistent single-step logic, and it prevents us from being able to fail
> an MMIO instruction with a synchronous exception.
>
> Clean this up by only advancing the CPU state *after* the effects of the
> instruction are emulated.
>
> Signed-off-by: Mark Rutland
>
Mark Rutland writes:
> On Thu, Nov 08, 2018 at 02:38:43PM +, Peter Maydell wrote:
>> On 8 November 2018 at 14:28, Alex Bennée wrote:
>> >
>> > Mark Rutland writes:
>> >> One problem is that I couldn't spot when we advance the PC for an MMIO
>>
Mark Rutland writes:
> On Thu, Nov 08, 2018 at 12:40:11PM +0000, Alex Bennée wrote:
>> Mark Rutland writes:
>> > On Wed, Nov 07, 2018 at 06:01:20PM +, Mark Rutland wrote:
>> >> On Wed, Nov 07, 2018 at 05:10:31PM +, Alex Bennée wrote:
>> >&g
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