Re: [PATCH v2] arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening

2018-03-10 Thread Shanker Donthineni
Hi Will, On 03/09/2018 07:48 AM, Will Deacon wrote: > Hi SHanker, > > On Mon, Mar 05, 2018 at 11:06:43AM -0600, Shanker Donthineni wrote: >> The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC >> V1.1 Calling Convention to mitigate CVE-2017-5715. This patch

Re: [PATCH] arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening

2018-03-10 Thread Shanker Donthineni
Hi Will, On 03/06/2018 09:25 AM, Will Deacon wrote: > On Mon, Mar 05, 2018 at 12:03:33PM -0600, Shanker Donthineni wrote: >> On 03/05/2018 11:15 AM, Will Deacon wrote: >>> On Mon, Mar 05, 2018 at 10:57:58AM -0600, Shanker Donthineni wrote: >>>> On 03/05/20

[PATCH v7] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-03-07 Thread Shanker Donthineni
org> Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- Changes since v6: -Both I-Cache and D-Cache changes are symmetric as Will suggested. -Remove Kconfig option. -Patch __flush_icache_all(). Changes since v5: -Addressed Mark's review comments. Changes since v4: -Moved patc

Re: [PATCH v6] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-03-06 Thread Shanker Donthineni
Hi Will, On 03/06/2018 12:48 PM, Shanker Donthineni wrote: > Hi Will, > > On 03/06/2018 09:23 AM, Will Deacon wrote: >> Hi Shanker, >> >> On Tue, Mar 06, 2018 at 08:47:27AM -0600, Shanker Donthineni wrote: >>> On 03/06/2018 07:44 AM, Will Deacon wrote: >

Re: [PATCH v6] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-03-06 Thread Shanker Donthineni
Hi Will, On 03/06/2018 09:23 AM, Will Deacon wrote: > Hi Shanker, > > On Tue, Mar 06, 2018 at 08:47:27AM -0600, Shanker Donthineni wrote: >> On 03/06/2018 07:44 AM, Will Deacon wrote: >>> I think this is a slight asymmetry with the code for the I-side. On

Re: [PATCH v6] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-03-06 Thread Shanker Donthineni
Hi Will On 03/06/2018 07:44 AM, Will Deacon wrote: > Hi Shanker, > > On Wed, Feb 28, 2018 at 10:14:00PM -0600, Shanker Donthineni wrote: >> The DCache clean & ICache invalidation requirements for instructions >> to be data coherence are discoverable thro

Re: [PATCH] arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening

2018-03-05 Thread Shanker Donthineni
Hi Will, On 03/05/2018 11:15 AM, Will Deacon wrote: > On Mon, Mar 05, 2018 at 10:57:58AM -0600, Shanker Donthineni wrote: >> Hi Will, >> >> On 03/05/2018 09:56 AM, Will Deacon wrote: >>> Hi Shanker, >>> >>> On Fri, Mar 02, 2018 at 03:50:18PM -0

[PATCH v2] arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening

2018-03-05 Thread Shanker Donthineni
The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead of Silicon provider service ID 0xC2001700. Signed-off-by: Shanker Donthineni <sh

Re: [PATCH] arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening

2018-03-05 Thread Shanker Donthineni
Hi Will, On 03/05/2018 09:56 AM, Will Deacon wrote: > Hi Shanker, > > On Fri, Mar 02, 2018 at 03:50:18PM -0600, Shanker Donthineni wrote: >> The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC >> V1.1 Calling Convention to mitigate CVE-2017-5715. This patch

[PATCH] arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening

2018-03-02 Thread Shanker Donthineni
The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead of Silicon provider service ID 0xC2001700. Signed-off-by: Shanker Donthineni <sh

[PATCH v6] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-02-28 Thread Shanker Donthineni
org> Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- Changes since v5: -Addressed Mark's review comments. Changes since v4: -Moved patching ARM64_HAS_CACHE_DIC inside invalidate_icache_by_line -Removed 'dsb ishst' for ARM64_HAS_CACHE_DIC as Mark suggested. Changes since v

[PATCH v5] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-02-24 Thread Shanker Donthineni
org> Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- Changes since v4: -Moved patching ARM64_HAS_CACHE_DIC inside invalidate_icache_by_line -Removed 'dsb ishst' for ARM64_HAS_CACHE_DIC as Mark suggested. Changes since v3: -Added preprocessor guard CONFIG_xxx to code snippe

[PATCH v4] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-02-22 Thread Shanker Donthineni
org> Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- Changes since v3: -Added preprocessor guard CONFIG_xxx to code snippets in cache.S -Changed barrier attributes from ISH to ISHST. Changes since v2: -Included barriers, DSB/ISB with DIC set, and DSB with IDC set. -Single

Re: [PATCH v3] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-02-21 Thread Shanker Donthineni
Hi Mark, On 02/21/2018 09:09 AM, Mark Rutland wrote: > On Wed, Feb 21, 2018 at 07:49:06AM -0600, Shanker Donthineni wrote: >> The DCache clean & ICache invalidation requirements for instructions >> to be data coherence are discoverable through new fields in CTR_EL0. >>

[PATCH v3] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-02-21 Thread Shanker Donthineni
org> Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- Changes since v2: -Included barriers, DSB/ISB with DIC set, and DSB with IDC set. -Single Kconfig option. Changes since v1: -Reworded commit text. -Used the alternatives framework as Catalin suggested.

Re: [PATCH v2] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-02-21 Thread Shanker Donthineni
Hi Catalin, On 02/21/2018 05:12 AM, Catalin Marinas wrote: > On Mon, Feb 19, 2018 at 08:59:06PM -0600, Shanker Donthineni wrote: >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index f55fe5b..4061210 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kco

[PATCH v2] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

2018-02-19 Thread Shanker Donthineni
org> Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- Changes since v1: -Reworded commit text. -Used the alternatives framework as Catalin suggested. -Rebased on top of https://patchwork.kernel.org/patch/10227927/ arch/arm64/Kconfig | 21 +++ arch/a

Re: [PATCH] arm64: Add support for new control bits CTR_EL0.IDC and CTR_EL0.IDC

2018-02-19 Thread Shanker Donthineni
Thanks Catalin for your comments. On 02/19/2018 11:18 AM, Catalin Marinas wrote: > On Mon, Feb 19, 2018 at 10:35:30AM -0600, Shanker Donthineni wrote: >> On 02/19/2018 08:38 AM, Catalin Marinas wrote: >>> On the patch, I'd rather have an alternative framework entry for no V

Re: [PATCH] arm64: Add support for new control bits CTR_EL0.IDC and CTR_EL0.IDC

2018-02-19 Thread Shanker Donthineni
Hi Will, On 02/19/2018 08:43 AM, Will Deacon wrote: > Hi Shanker, > > On Fri, Feb 16, 2018 at 06:57:46PM -0600, Shanker Donthineni wrote: >> Two point of unification cache maintenance operations 'DC CVAU' and >> 'IC IVAU' are optional for implementors as per ARMv8 specifi

Re: [PATCH] arm64: Add support for new control bits CTR_EL0.IDC and CTR_EL0.IDC

2018-02-19 Thread Shanker Donthineni
Hi Catalin, On 02/19/2018 08:38 AM, Catalin Marinas wrote: > On Fri, Feb 16, 2018 at 06:57:46PM -0600, Shanker Donthineni wrote: >> Two point of unification cache maintenance operations 'DC CVAU' and >> 'IC IVAU' are optional for implementors as per ARMv8 specification. >&

[PATCH] KVM: arm/arm64: No need to zero CNTVOFF in kvm_timer_vcpu_put() for VHE

2018-02-19 Thread Shanker Donthineni
. — CNTVCT is read from Non-secure EL0. So, no need to zero CNTVOFF_EL2/CNTVOFF for VHE case. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- virt/kvm/arm/arch_timer.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/virt/kvm/arm/arch_timer.c b/virt/k

[PATCH] arm64: Add support for new control bits CTR_EL0.IDC and CTR_EL0.IDC

2018-02-16 Thread Shanker Donthineni
== 0b000 or (CLIDR_EL1.LoUIS == 0b000 && CLIDR_EL1.LoUU == 0b000). 1: Data cache clean to the point of unification is not required for instruction to data coherence. Signed-off-by: Philip Elcan <pel...@codeaurora.org> Signed-off-by: Shanker Donthineni <shank...@codeaurora.org

[PATCH] arm64: Add missing Falkor part number for branch predictor hardening

2018-02-11 Thread Shanker Donthineni
References to CPU part number MIDR_QCOM_FALKOR were dropped from the mailing list patch due to mainline/arm64 branch dependency. So this patch adds the missing part number. Fixes: ec82b567a74f ("arm64: Implement branch predictor hardening for Falkor") Signed-off-by: Shanker Donthin

Re: [PATCH] irqchip/gic-v3: Use wmb() instead of smb_wmb() in gic_raise_softirq()

2018-02-01 Thread Shanker Donthineni
Hi Will, Thanks for your quick reply. On 02/01/2018 04:33 AM, Will Deacon wrote: > Hi Shanker, > > On Wed, Jan 31, 2018 at 06:03:42PM -0600, Shanker Donthineni wrote: >> A DMB instruction can be used to ensure the relative order of only >> memory accesses before and aft

[PATCH] irqchip/gic-v3: Use wmb() instead of smb_wmb() in gic_raise_softirq()

2018-01-31 Thread Shanker Donthineni
ensures that no instructions that appear in program order after the DSB instruction, can execute until the DSB instruction has completed. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- drivers/irqchip/irq-gic-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

Re: [PATCH] arm64: Implement branch predictor hardening for Falkor

2018-01-08 Thread Shanker Donthineni
able in upstream v4.15-rc7 branch. Please merge v2 patch. On 01/08/2018 01:10 PM, Shanker Donthineni wrote: > Hi Will, > > On 01/08/2018 12:44 PM, Will Deacon wrote: >> On Mon, Jan 08, 2018 at 05:09:33PM +, Will Deacon wrote: >>> On Fri, Jan 05, 2018 at 02:28:59PM -06

[PATCH v2 1/2] arm64: Define cputype macros for Falkor CPU

2018-01-08 Thread Shanker Donthineni
-by: Shanker Donthineni <shank...@codeaurora.org> Signed-off-by: Will Deacon <will.dea...@arm.com> --- This patch is availble at https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch/arm64?h=v4.15-rc7=c622cc013cece073722592cff1ac6643a33b1622 arch/arm64/include/a

[PATCH v2 2/2] arm64: Implement branch predictor hardening for Falkor

2018-01-08 Thread Shanker Donthineni
Falkor is susceptible to branch predictor aliasing and can theoretically be attacked by malicious code. This patch implements a mitigation for these attacks, preventing any malicious entries from affecting other victim contexts. Signed-off-by: Shanker Donthineni <shank...@codeaurora.

Re: [PATCH] arm64: Implement branch predictor hardening for Falkor

2018-01-08 Thread Shanker Donthineni
Hi Will, On 01/08/2018 12:44 PM, Will Deacon wrote: > On Mon, Jan 08, 2018 at 05:09:33PM +, Will Deacon wrote: >> On Fri, Jan 05, 2018 at 02:28:59PM -0600, Shanker Donthineni wrote: >>> Falkor is susceptible to branch predictor aliasing and can >>> theoretically be

Re: [PATCH] arm64: Implement branch predictor hardening for Falkor

2018-01-08 Thread Shanker Donthineni
Hi Andrew, On 01/08/2018 03:28 AM, Andrew Jones wrote: > Hi Shanker, > > On Fri, Jan 05, 2018 at 02:28:59PM -0600, Shanker Donthineni wrote: > ... >> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c >> index cb0fb37..daf53a5 100644 &g

[PATCH] arm64: Implement branch predictor hardening for Falkor

2018-01-05 Thread Shanker Donthineni
Falkor is susceptible to branch predictor aliasing and can theoretically be attacked by malicious code. This patch implements a mitigation for these attacks, preventing any malicious entries from affecting other victim contexts. Signed-off-by: Shanker Donthineni <shank...@codeaurora.

[PATCH v5 2/2] arm64: Add software workaround for Falkor erratum 1041

2017-12-11 Thread Shanker Donthineni
to 0 when HCR_EL2[VM] has a value of 1). To avoid the errant behavior, software must execute an ISB immediately prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- Changes since v3: Rebased to kernel v4.

[PATCH v5 1/2] arm64: Define cputype macros for Falkor CPU

2017-12-11 Thread Shanker Donthineni
-by: Shanker Donthineni <shank...@codeaurora.org> --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 235e77d..cbf08d7 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch

Re: [RESEND PATCH v4 2/2] arm64: Add software workaround for Falkor erratum 1041

2017-12-11 Thread Shanker Donthineni
Thanks Mark, I'll post v5 patch without alternatives. On 12/11/2017 04:45 AM, Mark Rutland wrote: > Hi, > > On Sun, Dec 10, 2017 at 08:03:43PM -0600, Shanker Donthineni wrote: >> +/** >> + * Errata workaround prior to disable MMU. Insert an ISB immediately prior >&g

[RESEND PATCH v4 2/2] arm64: Add software workaround for Falkor erratum 1041

2017-12-10 Thread Shanker Donthineni
to 0 when HCR_EL2[VM] has a value of 1). To avoid the errant behavior, software must execute an ISB immediately prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- Changes since v3: Rebased to kernel v4.

[RESEND PATCH v4 1/2] arm64: Define cputype macros for Falkor CPU

2017-12-10 Thread Shanker Donthineni
-by: Shanker Donthineni <shank...@codeaurora.org> --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 235e77d..cbf08d7 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch

Re: [PATCH v4 2/2] arm64: Add software workaround for Falkor erratum 1041

2017-12-04 Thread Shanker Donthineni
Hi Will, On 12/03/2017 07:35 AM, Shanker Donthineni wrote: > Hi Will, thanks for your review comments. > > On 12/01/2017 05:24 AM, Will Deacon wrote: >> On Mon, Nov 27, 2017 at 05:18:00PM -0600, Shanker Donthineni wrote: >>> The ARM architecture defines the memory loca

Re: [PATCH v4 2/2] arm64: Add software workaround for Falkor erratum 1041

2017-12-03 Thread Shanker Donthineni
Hi Will, thanks for your review comments. On 12/01/2017 05:24 AM, Will Deacon wrote: > On Mon, Nov 27, 2017 at 05:18:00PM -0600, Shanker Donthineni wrote: >> The ARM architecture defines the memory locations that are permitted >> to be accessed as the result of a speculative in

[PATCH v4 0/2] Implement a software workaround for Falkor erratum 1041

2017-11-27 Thread Shanker Donthineni
series got dropped to accommodate review comments. Apply the workaround where it's required. Posted wrong the patches in v2. Shanker Donthineni (2): arm64: Define cputype macros for Falkor CPU arm64: Add software workaround for Falkor erratum 1041 Documentation/arm64/silicon-errata.txt | 1

[PATCH v4 1/2] arm64: Define cputype macros for Falkor CPU

2017-11-27 Thread Shanker Donthineni
-by: Shanker Donthineni <shank...@codeaurora.org> --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 235e77d..cbf08d7 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch

[PATCH v4 2/2] arm64: Add software workaround for Falkor erratum 1041

2017-11-27 Thread Shanker Donthineni
to 0 when HCR_EL2[VM] has a value of 1). To avoid the errant behavior, software must execute an ISB immediately prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- Changes since v3: Rebased to kernel v4.

Re: [PATCH v2 2/2] arm64: Add software workaround for Falkor erratum 1041

2017-11-12 Thread Shanker Donthineni
Hi, Sorry, I've posted a wrong patch which causes the compilation errors. Please disregard this patch, I posted v3 patch to fix the build issue. https://patchwork.kernel.org/patch/10055077/ On 11/12/2017 07:16 PM, Shanker Donthineni wrote: > The ARM architecture defines the memory locati

[PATCH v3 1/2] arm64: Define cputype macros for Falkor CPU

2017-11-12 Thread Shanker Donthineni
-by: Shanker Donthineni <shank...@codeaurora.org> --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 235e77d..cbf08d7 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch

[PATCH v3 2/2] arm64: Add software workaround for Falkor erratum 1041

2017-11-12 Thread Shanker Donthineni
to 0 when HCR_EL2[VM] has a value of 1). To avoid the errant behavior, software must execute an ISB immediately prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- Changes since v1: Apply the workaround wher

[PATCH v3 0/2] Implement a software workaround for Falkor erratum 1041

2017-11-12 Thread Shanker Donthineni
E1041. Shanker Donthineni (2): arm64: Define cputype macros for Falkor CPU arm64: Add software workaround for Falkor erratum 1041 Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 10 ++ arch/arm64/include/asm/assembler.h | 18

[PATCH v2 0/2] Implement a software workaround for Falkor erratum 1041

2017-11-12 Thread Shanker Donthineni
SCTLR_ELn[M] is changed to 0 to fix the Falkor erratum 1041. Patch2 from V1 series got dropped to accommodate review comments. Apply the workaround where it's required. Patch1: - CPUTYPE definitions for Falkor CPU. Patch2: - Actual workaround changes for erratum E1041. Shanker Donthineni (2

[PATCH v2 2/2] arm64: Add software workaround for Falkor erratum 1041

2017-11-12 Thread Shanker Donthineni
to 0 when HCR_EL2[VM] has a value of 1). To avoid the errant behavior, software must execute an ISB immediately prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- Documentation/arm64/silicon-errata.txt | 1 +

[PATCH v2 1/2] arm64: Define cputype macros for Falkor CPU

2017-11-12 Thread Shanker Donthineni
-by: Shanker Donthineni <shank...@codeaurora.org> --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 235e77d..cbf08d7 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch

Re: [PATCH 3/3] arm64: Add software workaround for Falkor erratum 1041

2017-11-12 Thread Shanker Donthineni
Hi James, On 11/10/2017 04:24 AM, James Morse wrote: > Hi Shanker, > > On 09/11/17 15:22, Shanker Donthineni wrote: >> On 11/09/2017 05:08 AM, James Morse wrote: >>> On 04/11/17 21:43, Shanker Donthineni wrote: >>>> On 11/03/2017 10:11 AM, Robin Murphy wro

Re: [PATCH 3/3] arm64: Add software workaround for Falkor erratum 1041

2017-11-09 Thread Shanker Donthineni
Hi James, On 11/09/2017 05:08 AM, James Morse wrote: > Hi Shanker, Robin, > > On 04/11/17 21:43, Shanker Donthineni wrote: >> On 11/03/2017 10:11 AM, Robin Murphy wrote: >>> On 03/11/17 03:27, Shanker Donthineni wrote: >>>> The ARM architecture defines the

Re: [PATCH 3/3] arm64: Add software workaround for Falkor erratum 1041

2017-11-04 Thread Shanker Donthineni
Hi Robin, Thanks for your review comments. On 11/03/2017 10:11 AM, Robin Murphy wrote: > On 03/11/17 03:27, Shanker Donthineni wrote: >> The ARM architecture defines the memory locations that are permitted >> to be accessed as the result of a speculative instruction fetch from

[PATCH 3/3] arm64: Add software workaround for Falkor erratum 1041

2017-11-02 Thread Shanker Donthineni
to executing the MSR that will change SCTLR_ELn[M] from 1 to 0. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 10 ++ arch/arm64/include/asm/assembler.h | 17 + arch

[PATCH 0/3] Implement a software workaround for Falkor erratum 1041

2017-11-02 Thread Shanker Donthineni
SCTLR_ELn[M] is changed to 0 to fix the Falkor erratum 1041. Patch1: - CPUTYPE definitions for Falkor CPU. Patch2: - Define two ASM helper macros to read/write SCTLR_ELn register. Patch3: - Actual workaround changes for erratum E1041. Shanker Donthineni (3): arm64: Define cputype macros

[PATCH 1/3] arm64: Define cputype macros for Falkor CPU

2017-11-02 Thread Shanker Donthineni
-by: Shanker Donthineni <shank...@codeaurora.org> Signed-off-by: Neil Leeder <nlee...@codeaurora.org> --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 235e77d..cbf08d7 10064

[PATCH 2/3] arm64: Prepare SCTLR_ELn accesses to handle Falkor erratum 1041

2017-11-02 Thread Shanker Donthineni
This patch introduces two helper macros read_sctlr and write_sctlr to access system register SCTLR_ELn. Replace all MSR/MRS references to sctlr_el1{el2} with macros. This should cause no behavioral change. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- arch/arm64/inclu

Re: [PATCH v4 00/26] KVM/ARM: Add support for GICv4

2017-10-08 Thread Shanker Donthineni
Hi Marc, I've tested this patch series on QDF2400 server platform using NVME card, the basic functionality works fine and the below log messages shows around 70 interrupts are delivered to vCPU directly. Tested-by: Shanker Donthineni <shank...@codeaurora.org> >From guest kernel: /

[PATCH] arm64: KVM: Reject non-compliant HVC calls from guest kernel

2017-08-07 Thread Shanker Donthineni
/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- arch/arm64/include/asm/esr.h | 4 arch/arm64/kvm/handle_exit.c | 12 +++- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/arch

[PATCH] KVM: arm/arm64: Fix bug in advertising KVM_CAP_MSI_DEVID capability

2017-07-08 Thread Shanker Donthineni
then we don't advertise KVM_CAP_MSI_DEVID capability. Update the field msis_require_devid to true inside vgic_its_create() to fix the issue. Fixes: 0e4e82f154e3 ("vgic-its: Enable ITS emulation as a virtual MSI controller") Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>

Re: [PATCH v2 38/52] KVM: arm/arm64: GICv4: Wire init/teardown of per-VM support

2017-07-08 Thread Shanker Donthineni
s_gicv4 && vgic_has_its(kvm)) > + vgic_v4_teardown(kvm); > } > > void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu) > -- Shanker Donthineni Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is

RE: [PATCH v2 00/52] irqchip: KVM: Add support for GICv4

2017-07-01 Thread Shanker Donthineni
after reviewing giant v2 series. Tested-by: Shanker Donthineni <shank...@codeaurora.org> -Original Message- From: linux-arm-kernel [mailto:linux-arm-kernel-boun...@lists.infradead.org] On Behalf Of Marc Zyngier Sent: Wednesday, June 28, 2017 10:03 AM To: linux-ker...@vger.kernel.org;

Re: [RFC PATCH 24/33] irqchip/gic-v3-its: Add VPE scheduling

2017-03-16 Thread Shanker Donthineni
anyway I > understand this will force the HW to read the LPI pending table. It's not a good idea to set PendLast bit always. There is no correctness issue but causes a huge impact on the system performance. No need to read pending table contents from memory if

Re: [PATCH v2] arm64: kvm: Use has_vhe() instead of hyp_alternate_select()

2017-03-06 Thread Shanker Donthineni
Hi Marc, On 03/06/2017 02:34 AM, Marc Zyngier wrote: Hi Shanker, On Mon, Mar 06 2017 at 2:33:18 am GMT, Shanker Donthineni <shank...@codeaurora.org> wrote: Now all the cpu_hwcaps features have their own static keys. We don't need a separate function hyp_alternate_select() to patch t

[PATCH v2] arm64: kvm: Use has_vhe() instead of hyp_alternate_select()

2017-03-05 Thread Shanker Donthineni
the better code with a fewer instructions. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- v2: removed 'Change-Id: Ia8084189833f2081ff13c392deb5070c46a64038' from commit arch/arm64/kvm/hyp/debug-sr.c | 12 ++ arch/arm64/kvm/hyp/switch.c

[PATCH] arm64: kvm: Use has_vhe() instead of hyp_alternate_select()

2017-03-05 Thread Shanker Donthineni
the better code with a fewer instructions. Change-Id: Ia8084189833f2081ff13c392deb5070c46a64038 Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- arch/arm64/kvm/hyp/debug-sr.c | 12 ++ arch/arm64/kvm/hyp/switch.c| 50 +++---

Re: [RFC PATCH 24/33] irqchip/gic-v3-its: Add VPE scheduling

2017-02-13 Thread Shanker Donthineni
+ +/* * ITS registers, offsets from ITS_base */ #define GITS_CTLR 0x -- Shanker Donthineni Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundati

Re: [RFC PATCH 28/33] irqchip/gic-v3-its: Support VPE doorbell invalidation even when !DirectLPI

2017-02-13 Thread Shanker Donthineni
ce_ids - 1, 0); How do we know this 'devid' is not being used by real hardware devices? I think we need some kind check in its_msi_prepare() to skip this device or WARN. Unfortunately Qualcomm doesn't support Direct LPI feature. -- Shanker Donthineni Qualcomm Datacenter Technologies, Inc. as an af

Re: [RFC PATCH 24/33] irqchip/gic-v3-its: Add VPE scheduling

2017-02-13 Thread Shanker Donthineni
lt;< 62) +#define GICR_PENDBASER_Valid (1ULL << 63) + +/* * ITS registers, offsets from ITS_base */ #define GITS_CTLR 0x -- Shanker Donthineni Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qua

Re: [RFC PATCH 23/33] irqchip/gic-v3-its: Add VPENDBASER/VPROPBASER accessors

2017-02-13 Thread Shanker Donthineni
_CTLR.RWP == 0. -- Shanker Donthineni Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. ___ kvmarm maili

Re: [RFC PATCH 21/33] irqchip/gic-v3-its: Add VPE irq domain allocation/teardown

2017-02-13 Thread Shanker Donthineni
(GFP_KERNEL); + if (vpt_page) { Change to 'if (!vpt_page)'. -- Shanker Donthineni Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux

Re: [RFC PATCH 17/33] irqchip/gic-v3-its: Add VLPI configuration hook

2017-02-13 Thread Shanker Donthineni
return 0; + } + + case PROP_UPDATE_VLPI: + { + return 0; + } + + default: + return -EINVAL; + } Missing a return statement. -- Shanker Donthineni Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Te

Re: [RFC PATCH 11/33] irqchip/gic-v3-its: Split out pending table allocation

2017-02-13 Thread Shanker Donthineni
would easier to enable 24bit LPI later. Actually Qualcomm server chips support 24bit IDBITS. -- Shanker Donthineni Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collabo

Re: [RFC PATCH 10/33] irqchip/gic-v4-its: Allow use of indirect VCPU tables

2017-02-13 Thread Shanker Donthineni
); err = its_setup_baser(its, baser, cache, shr, psz, order, indirect); if (err < 0) { -- Shanker Donthineni Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Au

Re: [RFC PATCH 06/33] irqchip/gic-v3-its: Add probing for VLPI properties

2017-02-13 Thread Shanker Donthineni
goto out_free_its; + } + + pr_info("ITS@%pa: Using ITS number %d\n", >start, its_number); + } else { + pr_info("ITS@%pa: Single VMOVP capable\n", >start); + } Can we move to a separate function for code readability purp

Re: [RFC PATCH 02/33] irqchip/gic-v3: Add VLPI/DirectLPI discovery

2017-02-13 Thread Shanker Donthineni
pi &= !!(typer & GICR_TYPER_DirectLPIS); + + return 1; +} + +static void gic_update_vlpi_properties(void) +{ + gic_scan_rdist_properties(__gic_update_vlpi_properties); + pr_info("%sVLPI support, %sdirect LPI support\n", Would be better if we keep one space after 'no'?

Re: [RFC PATCH 01/33] irqchip/gic-v3: Add redistributor iterator

2017-02-13 Thread Shanker Donthineni
return 0; + /* We couldn't even deal with ourselves... */ WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", -smp_processor_id(), mpidr); +smp_processor_id(), + (unsigned long)cpu_logical_map(smp_processor_id()));

[RESEND PATCH] KVM: arm/arm64: vgic: Stop injecting the MSI occurrence twice

2017-02-03 Thread Shanker Donthineni
validation checks. No need to call the function vgic_its_inject_msi() second time to avoid an unnecessary overhead in IRQ queue logic. It also avoids the possibility of VM seeing the MSI twice. Simple fix, return -1 if the argument 'level' value is zero. Signed-off-by: Shanker Donthineni <sh

[PATCH v3] arm64: KVM: Optimize __guest_enter/exit() to save a few instructions

2016-08-30 Thread Shanker Donthineni
in tpidr_el2. The function __guest_exit() calling convention is slightly modified, caller only pushes the regs x0-x1 to stack instead of regs x0-x3. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> --- Tested this

Re: [PATCH v2] arm64: KVM: Save four instructions in __guest_enter/exit()

2016-08-30 Thread Shanker Donthineni
Hi Marc, On 08/30/2016 05:54 AM, Marc Zyngier wrote: On 30/08/16 10:55, Christoffer Dall wrote: On Mon, Aug 29, 2016 at 10:51:14PM -0500, Shanker Donthineni wrote: We are doing an unnecessary stack push/pop operation when restoring the guest registers x0-x18 in __guest_enter(). This patch

[PATCH v2] arm64: KVM: Save four instructions in __guest_enter/exit()

2016-08-29 Thread Shanker Donthineni
in tpidr_el2. The function __guest_exit() prototype is simplified and caller pushes the regs x0-x1 to stack instead of regs x0-x3. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- Changes since v1: Incorporated Cristoffer suggestions. __guest_exit prototype is changed to

Re: [PATCH] arm64: KVM: Save two instructions in __guest_enter()

2016-08-29 Thread Shanker Donthineni
, Shanker Donthineni wrote: We are doing an unnecessary stack push/pop operation when restoring the guest registers x0-x18 in __guest_enter(). This patch saves the two instructions by using x18 as a base register. No need to store the vcpu context pointer in stack because it is redundant

[PATCH] arm64: KVM: Save two instructions in __guest_enter()

2016-08-09 Thread Shanker Donthineni
information is available in tpidr_el2. Signed-off-by: Shanker Donthineni <shank...@codeaurora.org> --- arch/arm64/kvm/hyp/entry.S | 66 ++ 1 file changed, 32 insertions(+), 34 deletions(-) diff --git a/arch/arm64/kvm/hyp/entry.S b/arch/arm64/k

Re: [PULL 00/29] KVM/ARM Changes for v4.7

2016-05-17 Thread Shanker Donthineni
your board. > > Regards, > -- Shanker Donthineni Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ___ kvmarm mailing

Re: [PULL 00/29] KVM/ARM Changes for v4.7

2016-05-17 Thread Shanker Donthineni
020 > 8003ffe14010 >> 3fe0: 0a482550 8003c040 0800f000 > 8003c0403a30 >> 4000: 8003c0403b50 8003c0403a30 > >> 4020: >

Re: [PATCH v6 10/10] clocksource: arm_arch_timer: Remove arch_timer_get_timecounter

2016-04-23 Thread Shanker Donthineni
On 04/11/2016 10:33 AM, Julien Grall wrote: > The only call of arch_timer_get_timecounter (in KVM) has been removed. > > Signed-off-by: Julien Grall <julien.gr...@arm.com> > Acked-by: Christoffer Dall <christoffer.d...@linaro.org> Tested-by: Shanker Donthineni <shan

Re: [PATCH v6 09/10] KVM: arm/arm64: vgic: Rely on the GIC driver to parse the firmware tables

2016-04-23 Thread Shanker Donthineni
ll <julien.gr...@arm.com> > Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> > Tested-by: Shanker Donthineni <shank...@codeaurora.org> Using the Qualcomm Technologies QDF2XXX server with PAGE_SIZE=4K. > --- > Cc: Marc Zyngier <marc.zyng...@arm.com> >

Re: [PATCH v6 08/10] KVM: arm/arm64: arch_timer: Rely on the arch timer to parse the firmware tables

2016-04-23 Thread Shanker Donthineni
newly function > arch_timer_get_kvm_info() > which return all the information required by the virtual timer code. > > Signed-off-by: Julien Grall <julien.gr...@arm.com> > Acked-by: Christoffer Dall <christoffer.d...@linaro.org> > Tested-by: Shanker Donthineni <shank...@codeaurora.org&

Re: [PATCH v6 07/10] irqchip/gic-v3: Parse and export virtual GIC information

2016-04-23 Thread Shanker Donthineni
er <ja...@lakedaemon.net> > Cc: Marc Zyngier <marc.zyng...@arm.com> > Tested-by: Shanker Donthineni <shank...@codeaurora.org> Using the Qualcomm Technologies QDF2XXX server platform. -- Shanker Donthineni Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc

Re: [PATCH v6 06/10] irqchip/gic-v3: Gather all ACPI specific data in a single structure

2016-04-23 Thread Shanker Donthineni
Dall <christoffer.d...@linaro.org> > Reviewed-by: Hanjun Guo <hanjun@linaro.org> > Tested-by: Shanker Donthineni <shank...@codeaurora.org> Using the Qualcomm Technologies QDF2XXX server platform. -- Shanker Donthineni Qualcomm Technologies, Inc. on behalf of Qualcomm Innovat

Re: [PATCH v6 04/10] irqchip/gic-v2: Parse and export virtual GIC information

2016-04-23 Thread Shanker Donthineni
t; Introduce a new structure and set of helpers to get/set the virtual GIC > information. Also fill up the structure for GICv2. > > Signed-off-by: Julien Grall <julien.gr...@arm.com> > Tested-by: Shanker Donthineni <shank...@codeaurora.org> Using the Qualcomm Technolo

Re: [PATCH v6 03/10] irqchip/gic-v2: Gather ACPI specific data in a single structure

2016-04-23 Thread Shanker Donthineni
fic, gather all the > information in a single structure. > > Signed-off-by: Julien Grall <julien.gr...@arm.com> > Acked-by: Christofer Dall <christoffer.d...@linaro.org> > Acked-by: Hanjun Guo <hanjun....@linaro.org> > Tested-by: Shanker Donthineni <shank...@codeauror

Re: [PATCH v6 02/10] clocksource: arm_arch_timer: Extend arch_timer_kvm_info to get the virtual IRQ

2016-04-23 Thread Shanker Donthineni
kvm_info to get the virtual > IRQ. > > Note that the KVM code will be modified in a subsequent patch. > > Signed-off-by: Julien Grall <julien.gr...@arm.com> > Acked-by: Christoffer Dall <christoffer.d...@linaro.org> > Tested-by: Shanker Donthineni <shank...@codeaurora.o

Re: [PATCH v6 01/10] clocksource: arm_arch_timer: Gather KVM specific information in a structure

2016-04-23 Thread Shanker Donthineni
y: Christoffer Dall <christoffer.d...@linaro.org> > Tested-by: Shanker Donthineni <shank...@codeaurora.org> Using the Qualcomm Technologies QDF2XXX server platform. > --- > Cc: Daniel Lezcano <daniel.lezc...@linaro.org> > Cc: Thomas Gleixner <t...@linutronix.de&

Re: [PATCH v5 6/9] irqchip/gic-v3: Parse and export virtual GIC information

2016-04-11 Thread Shanker Donthineni
q = irq; >>> + >>> +if (acpi_data.vcpu_base) { >> >> Sorry, I'm not familiar with KVM, but I got a question here, will >> KVM works without valid vcpu_base in GICv3 mode? > Yes, KVM works without vcpu_base in GICv3 mode. The vcpu_base will be used for emu

Re: [PATCH v5 6/9] irqchip/gic-v3: Parse and export virtual GIC information

2016-04-08 Thread Shanker Donthineni
_info); > +} > > static int __init > gic_acpi_init(struct acpi_subtable_header *header, const unsigned long > end) > @@ -1159,6 +1265,8 @@ gic_acpi_init(struct acpi_subtable_header *header, > const unsigned long end) >

Re: Intermittent guest kernel crashes with v4.5-rc6.

2016-03-03 Thread Shanker Donthineni
On 03/03/2016 08:03 AM, Marc Zyngier wrote: > On 03/03/16 13:25, Shanker Donthineni wrote: >> >> On 03/02/2016 11:35 AM, Marc Zyngier wrote: >>> On 02/03/16 15:48, Shanker Donthineni wrote: >>> >>>> We haven't started running heavy workloads in VMs. S

Re: Intermittent guest kernel crashes with v4.5-rc6.

2016-03-03 Thread Shanker Donthineni
On 03/02/2016 11:35 AM, Marc Zyngier wrote: > On 02/03/16 15:48, Shanker Donthineni wrote: > >> We haven't started running heavy workloads in VMs. So far we >> have noticed this random nature behavior only during guest >> kernel boot (at EL1). >> >> We didn'

Re: Intermittent guest kernel crashes with v4.5-rc6.

2016-03-02 Thread Shanker Donthineni
On 03/02/2016 09:09 AM, Marc Zyngier wrote: > On 02/03/16 14:59, Shanker Donthineni wrote: >> Hi Marc, >> >> Thanks for your quick reply. >> >> On 03/02/2016 08:16 AM, Marc Zyngier wrote: >>> On 02/03/16 13:56, Shanker Donthineni wrote: >>

Re: Intermittent guest kernel crashes with v4.5-rc6.

2016-03-02 Thread Shanker Donthineni
Hi Marc, Thanks for your quick reply. On 03/02/2016 08:16 AM, Marc Zyngier wrote: On 02/03/16 13:56, Shanker Donthineni wrote: For some reason v4.5-rc6 kernel is not stable for guest machines on Qualcomm server platforms. We are getting IABT translation faults while booting the guest kernel

Intermittent guest kernel crashes with v4.5-rc6.

2016-03-02 Thread Shanker Donthineni
an_flat_dt+0x9c/0xd0 [0.00] pc : [] lr : [] pstate: 83c5 [0.00] sp : ffc000d47e80 [0.00] x29: ffc000d47e80 x28: 00000000 -- Shanker Donthineni Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc.