On 2015/9/3 0:08, Christoffer Dall wrote:
> On Mon, Aug 10, 2015 at 09:26:07PM +0800, Zhichao Huang wrote:
>> Enable trapping of the debug registers unconditionally, allowing guests to
>> use the debug infrastructure.
>>
>> Signed-off-by: Zhichao Huang <zhichao
On 2015/9/2 19:38, Christoffer Dall wrote:
>
> I really think that we should read the register, clear the bits you care
> about (MDBGen and HDBGen) and then write back the register.
>
> So, if I recall correctly, this is to avoid having to set HDCR_TDE
> below?
>
> Given Will's concerns about
On 2015/9/3 0:01, Christoffer Dall wrote:
> On Mon, Aug 10, 2015 at 09:26:05PM +0800, Zhichao Huang wrote:
>>
>> -static bool trap_debug32(struct kvm_vcpu *vcpu,
>> +/* Indicate whether the guest has enabled any break/watch points or not. */
>> +static bool guest_d
On 2015/9/2 22:53, Christoffer Dall wrote:
>> +/* Reads cp14 registers from hardware.
>> + * Writes cp14 registers in-order to the CP14 struct pointed to by r10
>> + *
>> + * Assumes vcpu pointer in vcpu reg
>> + *
>> + * Clobbers r2-r12
>> + */
>> +.macro save_debug_state
>> +
the debug mode(DBGDSCR) in the guest world all
the time, preventing the guests to mess with the host state.
However, it is a precursor for later patches which will need to do
more to world switch debug states while necessary.
Cc: sta...@vger.kernel.org
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
/kvmarm/2015-May/014847.html
[3]: https://lists.cs.columbia.edu/pipermail/kvmarm/2015-June/015167.html
Zhichao Huang (15):
KVM: arm: plug guest debug exploit
KVM: arm: rename pm_fake handler to trap_raz_wi
KVM: arm: enable to use the ARM_DSCR_MDBGEN macro from KVM assembly
code
KVM: arm
pm_fake doesn't quite describe what the handler does (ignoring writes
and returning 0 for reads).
As we're about to use it (a lot) in a different context, rename it
with a (admitedly cryptic) name that make sense for all users.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
Reviewed
Add #ifndef __ASSEMBLY__ in hw_breakpoint.h, in order to use
the ARM_DSCR_MDBGEN macro from KVM assembly code.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
Reviewed-by: Alex Bennee alex.ben...@linaro.org
Acked-by: Christoffer Dall christoffer.d...@linaro.org
---
arch/arm/include/asm
There are too many cp15 traps, so we don't reuse the cp15 trace event
but add a new trace event to trace the access of debug registers.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
Acked-by: Christoffer Dall christoffer.d...@linaro.org
---
arch/arm/kvm/coproc.c | 14 ++
arch
Add handlers for all the 32-bit debug registers.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/include/asm/kvm_asm.h | 12
arch/arm/include/asm/kvm_host.h | 3 +
arch/arm/kernel/asm-offsets.c | 1 +
arch/arm/kvm/coproc.c | 124
Avoid world-switching all the debug registers when neither the host
nor the guest has configured any [WB]points.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/kvm/interrupts_head.S | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git
Enable trapping of the debug registers unconditionally, allowing guests to
use the debug infrastructure.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
---
arch/arm/kvm/interrupts_head.S | 2 +-
1 file changed, 1 insertion(+), 1
As we're about to trap a bunch of CP14 registers, let's rework
the CP15 handling so it can be generalized and work with multiple
tables.
We stop trapping access here, because we haven't finished our trap
handlers. We will enable trapping agian until everything is OK.
Signed-off-by: Zhichao Huang
Every guest entry, we need to keep track of host use of the debug
registers.
We only call the function upon guest entry, after preempt_disable()
and local_irq_disable(), so there is no race for it.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/include/asm/kvm_asm.h| 3
We trap debug register accesses from guest all the time, and read the
BCR/WCR to indicate whether the guest has enabled any break/watch points
or not.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/include/asm/kvm_asm.h | 2 ++
arch/arm/kvm/coproc.c | 75
As we're about to implement a lazy world switch for debug registers,
we add a function reading the break/watch control variables directly to
indicate whether the host has enabled any break/watch points or not.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/include/asm
an indication for KVM, and it's low-overhead.
We will only call it upon guest entry, so there is also no race for it.
On July 7, 2015 6:24:06 PM GMT+08:00, Will Deacon will.dea...@arm.com wrote:
On Tue, Jul 07, 2015 at 11:06:57AM +0100, Zhichao Huang wrote:
Chazy and me are talking about how
of reading from real
hardware registers, and to decide whether we need a world switch or
not.
Does it acceptable?
On July 3, 2015 7:56:11 PM GMT+08:00, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Fri, Jul 03, 2015 at 05:54:47PM +0800, Zhichao Huang wrote:
On June 30, 2015 5:20:20 PM
On June 30, 2015 5:20:20 PM GMT+08:00, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Mon, Jun 22, 2015 at 06:41:31PM +0800, Zhichao Huang wrote:
The trapping code keeps track of the state of the debug registers,
allowing for the switch code to implement a lazy switching strategy
On June 30, 2015 9:15:22 PM GMT+08:00, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Mon, Jun 22, 2015 at 06:41:32PM +0800, Zhichao Huang wrote:
Implement switching of the debug registers. While the number
of registers is massive, CPUs usually don't implement them all
(A15 has 6
On June 30, 2015 9:20:29 PM GMT+08:00, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Mon, Jun 22, 2015 at 06:41:30PM +0800, Zhichao Huang wrote:
Add handlers for all the 64-bit debug registers.
There is an overlap between 32 and 64bit registers. Make sure that
64-bit registers
The trapping code keeps track of the state of the debug registers,
allowing for the switch code to implement a lazy switching strategy.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/include/asm/kvm_asm.h | 3 +++
arch/arm/include/asm/kvm_host.h | 3 +++
arch/arm/kernel
Add handlers for all the 32-bit debug registers.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/include/asm/kvm_asm.h | 12
arch/arm/include/asm/kvm_host.h | 3 +
arch/arm/kernel/asm-offsets.c | 1 +
arch/arm/kvm/coproc.c | 122
We now have multiple tables for the various system registers
we trap. Make sure we check the order of all of them, as it is
critical that we get the order right (been there, done that...).
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/kvm/coproc.c | 26
The trapping code keeps track of the state of the debug registers,
allowing for the switch code to implement a lazy switching strategy.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/include/asm/kvm_asm.h | 3 +++
arch/arm/include/asm/kvm_host.h | 3 +++
arch/arm/kernel
Add handlers for all the 32-bit debug registers.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/include/asm/kvm_asm.h | 12
arch/arm/include/asm/kvm_host.h | 3 +
arch/arm/kernel/asm-offsets.c | 1 +
arch/arm/kvm/coproc.c | 122
Add handlers for all the 64-bit debug registers.
There is an overlap between 32 and 64bit registers. Make sure that
64-bit registers preceding 32-bit ones.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/kvm/coproc.c | 12
1 file changed, 12 insertions(+)
diff
reset functions
- Disable debug mode if we don't need it to reduce unnecessary switch
[1]: https://lists.cs.columbia.edu/pipermail/kvmarm/2015-May/014729.html
Zhichao Huang (11):
KVM: arm: plug guest debug exploit
KVM: arm: rename pm_fake handler to trap_raz_wi
KVM: arm: enable to use
As we're about to trap a bunch of CP14 registers, let's rework
the CP15 handling so it can be generalized and work with multiple
tables.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/kvm/coproc.c | 176 ++---
arch/arm/kvm
We now have multiple tables for the various system registers
we trap. Make sure we check the order of all of them, as it is
critical that we get the order right (been there, done that...).
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/kvm/coproc.c | 26
for later patches which will need to do
more to world switch debug states while necessary.
Cc: sta...@vger.kernel.org
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/include/asm/kvm_coproc.h | 3 +-
arch/arm/kvm/coproc.c | 60 +++
arch
Add #ifndef __ASSEMBLY__ in hw_breakpoint.h, in order to use
the ARM_DSCR_MDBGEN macro from KVM assembly code.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/include/asm/hw_breakpoint.h | 54 +++-
1 file changed, 29 insertions(+), 25 deletions
Until now we enable debug mode all the time even if we don't
actually need it.
Inspired by the implementation in arm64, disable debug mode if
we don't need it. And then we are able to reduce unnecessary
registers saving/restoring when the debug mode is disabled.
Signed-off-by: Zhichao Huang
Add handlers for all the 32-bit debug registers.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/include/asm/kvm_asm.h | 12
arch/arm/include/asm/kvm_host.h | 3 +
arch/arm/kernel/asm-offsets.c | 1 +
arch/arm/kvm/coproc.c | 122
Add handlers for all the 64-bit debug registers.
There is an overlap between 32 and 64bit registers. Make sure that
64-bit registers preceding 32-bit ones.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/kvm/coproc.c | 12
1 file changed, 12 insertions(+)
diff
We now have multiple tables for the various system registers
we trap. Make sure we check the order of all of them, as it is
critical that we get the order right (been there, done that...).
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/kvm/coproc.c | 26
As we're about to trap a bunch of CP14 registers, let's rework
the CP15 handling so it can be generalized and work with multiple
tables.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/kvm/coproc.c | 176 ++---
arch/arm/kvm
pm_fake doesn't quite describe what the handler does (ignoring writes
and returning 0 for reads).
As we're about to use it (a lot) in a different context, rename it
with a (admitedly cryptic) name that make sense for all users.
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm
for later patches which will need to do
more to world switch debug states while necessary.
Cc: sta...@vger.kernel.org
Signed-off-by: Zhichao Huang zhichao.hu...@linaro.org
---
arch/arm/include/asm/kvm_coproc.h | 3 +-
arch/arm/kvm/coproc.c | 60 +++
arch
the effort, at least for the time being.
This has been tested on a Cortex-A15 platform, running 32bit guests.
The patches for this series are based off v4.1-rc3 and can be found
at:
https://git.linaro.org/people/zhichao.huang/linux.git
branch: guest-debug/4.1-rc3-v1
Zhichao Huang (10):
KVM: arm: plug
On Tue, Mar 31, 2015 at 04:08:04PM +0100, Alex Bennée wrote:
This adds support for SW breakpoints inserted by userspace.
We do this by trapping all BKPT exceptions in the
hypervisor (MDCR_EL2_TDE).
why should we trap all debug exceptions?
The trap for cp14 register r/w seems enough to record
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